JPH02119333A - Delay insertion/desertion circuit - Google Patents

Abstract

PURPOSE:To prevent the synchronizing step out of a multiframe due to the insertion/deserting of delay from occurring by holding a multiframe signal transiently by separating it from an input signal, and outputting it with a regulated phase. CONSTITUTION:The multiframe signal is separated from the input signal 1 at a separation circuit 11, and the multiframe signal is sent to a memory circuit 12, and also, the input signal other than the multiframe signal is sent to an insertion circuit 13. The memory circuit 12 holds the multiframe signal transiently, and outputs it with a prescribed phase, and sends it to a selection circuit 14, and also, sends it to a delay circuit 15, and sends the signal to the selection circuit 14 after inserting the delay of one frame. The selection circuit 14 selects either the output signal of the memory circuit 12 or that of the delay circuit 15 by a selection control signal generated from a comparison result at a phase comparison circuit 20, and outputs it to the insertion circuit 13. The insertion circuit 13 superposes the multiframe signal on the signal again, and sends it to a selection circuit 18 and a delay circuit 16.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applied to a time division multiplex communication system. INDUSTRIAL APPLICATION This invention is utilized for the delay insertion/extraction circuit of a frame alignment circuit.

[4 Already Required] The present invention provides a delay insertion/removal circuit that inserts/removes a delay for an input signal and similarly delays a multi-frame signal by -frames. This is designed to eliminate multi-frame synchronization loss that occurs.

[Conventional technology]

FIG. 2 is a block diagram of a conventional delay insertion/extraction circuit.

Conventionally, a delay insertion/extraction circuit has a delay circuit 1 as shown in FIG.
6.17, it is composed of a selection circuit 18, a memory circuit 19, and a phase comparison circuit 20. The selection circuit 18 selects the input signal 1 from the transmission line and the output of the delay circuit 16 that delays the input signal 1 by a predetermined amount based on the control information of the phase comparison circuit 200, and also selects the frame pulse 2 from the transmission line and the frame pulse 2 from the transmission line. The output of the delay circuit 17 which delays the pulse 2 by a predetermined W3 is selected and output. The phase comparison circuit 20 compares the phases of the frame pulse 2 from the transmission line and the device MJ frame pulse 4, and selects the selection circuit 18 based on a specified reference value of the phase difference between the frame pulse 2 and the device internal reference frame pulse 4. The delay circuits 16 and 17 are inserted and removed under control.

That is, the writing phase and the reading phase in the memory circuit 19 are maintained at a predetermined phase difference or more, preventing a collision between the writing phase and the reading phase in the memory circuit 19, and maintaining the continuity of the input signal 1. and transmits output signal 3.

[Problem that the invention seeks to solve]

However, in such a conventional delay insertion/extraction circuit, since the memory circuit 19 is only written and read in units of one frame, it is difficult to insert/extract delay in a signal in which a multi-frame signal is superimposed. Even if frame synchronization is maintained on a frame-by-frame basis when this is done, the signal output from the memory circuit 19 has the disadvantage that multi-frame synchronization is lost.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks, and it is an object of the present invention to provide a delay insertion/extraction circuit that does not cause multi-frame synchronization loss caused by delay insertion/extraction.

[Means for solving problems]

In a delay insertion/extraction circuit, the present invention includes a separating circuit that separates a multi-frame signal from an input signal on a transmission path, a memory circuit that temporarily holds this multi-frame signal and outputs it with a specified phase, and an output signal of this memory circuit. a third delay circuit that delays the output signal by one frame; and a second delay circuit that selects either the output signal of the memory circuit or the output signal of the third delay circuit based on the control of the phase comparison circuit. The present invention is characterized by comprising a selection circuit, and an insertion circuit that inserts the output signal of the second selection circuit into the output signal of the separation circuit and supplies it as received data to the first selection circuit and the first delay circuit. do.

[Effect]

The separation circuit separates the multi-frame signal from the input signal on the transmission path. The memory circuit temporarily holds this multi-frame signal and outputs it with a specified phase.

The third delay circuit delays the output signal of the memory circuit by one frame. The second selection circuit selects and outputs either the output signal of the memory circuit or the output of the third delay circuit based on the control of the phase comparison circuit.

The insertion circuit inserts the output signal of the selection circuit into the output signal of the separation circuit and provides the result to the first selection circuit and the first delay circuit. The above operation can eliminate multi-frame synchronization loss caused by insertion and removal of delays.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings. 1st
The figure is a block diagram of a delay insertion/extraction circuit according to an embodiment of the present invention. In FIG. 1, the delay insertion/extraction circuit includes a delay circuit 16 as a first delay circuit that manually delays received data by a predetermined amount, and a second delay circuit that manually delays the transmission path frame pulse signal 2 by a predetermined amount. The circuit includes a delay circuit 17, which selects and outputs the received data and the output signal of the delay circuit 16, and selects and outputs either the transmission line frame pulse signal 2 or the output signal of the delay circuit 17. a selection circuit 18 as one selection circuit; a memory circuit 19 that outputs an output signal 3 by replacing the received signal outputted by the selection circuit 18 or the output signal of the delay circuit 16 with the internal reference phase in the opposing device; A phase comparison circuit 20 is provided which compares the phase of the transmission path frame pulse signal 2 outputted by the circuit 17 and the intra-device reference frame pulse 4 in the opposing device and controls the selection circuit 18 based on the comparison result.

Here, the features of the present invention include a separation circuit 11 that separates a multi-frame signal from an input signal 1 on a transmission path, a memory circuit 12 that temporarily holds this multi-frame signal and outputs it with a specified phase, and a memory circuit that The delay circuit 15 serves as a third delay circuit that delays the output signal of the memory circuit 12 by one frame, and either the output signal of the memory circuit 12 or the output signal of the delay circuit 15 is controlled based on the control of the phase comparator circuit 20. A selection circuit 14 is used as a second selection circuit to select, and the output signal of this selection circuit 14 is inserted into the output signal of the separation circuit 11 to receive data as a selection circuit 18 and a delay circuit 1.
6 and an insertion circuit 13 for providing the same.

The operation of the delay insertion/extraction circuit having such a configuration will be explained. In FIG. 1, an input signal 1 is separated into a multi-frame signal by a separation circuit 11, and the multi-frame signal is
The signal is sent to the memory circuit 12, and input signals other than the multi-frame signal are sent to the insertion circuit 13. The memory circuit 12 temporarily holds the multi-frame signal, outputs it at a predetermined phase, and sends it to the selection circuit 14.The memory circuit 12 also sends it to the delay circuit 15, and after inserting a delay of one frame, sends it out to the selection circuit 14. .

The selection circuit 14 selects either the output signal of the memory circuit 12 or the output signal of the delay circuit 15 based on the selection control signal generated from the comparison result of the phase comparison circuit 20 and outputs it to the insertion circuit 13. The insertion circuit 13 superimposes the multi-frame signal again and sends it to the selection circuit 18 and the delay circuit 16. In addition, the transmission path frame pulse 2 is transmitted to the selection circuit 1.
8 and delay circuit 17. In the selection circuit 18, the output signal of the insertion circuit 13, the output signal of the delay circuit 16, the transmission line frame pulse 2, and the output of the delay circuit 17 are selected based on the comparison result of the phase comparison circuit 20, and the multi-frames are superimposed. Send the input signal to the memory circuit 19,
It also sends the frame clock to the phase comparator circuit 20.

The memory circuit 19 replaces the input signal from the transmission line with the reference phase within the device and sends out an output signal 3.

The phase comparator circuit 20 compares the phases of the transmission line frame pulse 2 and the internal reference frame pulse 4 to adjust the delay of the selection circuit 18 so as to prevent a collision between the read phase and the write phase in the memory circuit 19. Generates a selection control signal for insertion/removal. Further, based on the comparison result of the phase comparator circuit 20, delays are inserted and removed in the multi-frame signal. Since the memory circuit 19 only performs phase management in units of one frame, multi-frame synchronization is performed using the output signal of the memory circuit 19 to prevent collision between the write phase and the successive phase in the direction of inserting a delay. If this happens, a delay corresponding to one frame of the multiframe signal is inserted/removed to cause multiframe synchronization loss.

〔Effect of the invention〕

As described above, the present invention has the excellent effect of eliminating multi-frame synchronization loss caused by inserting and removing delays.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a delay insertion/extraction circuit according to an embodiment of the present invention. FIG. 2 is a block diagram of a conventional delay insertion/extraction circuit. 1... Input signal, 2... Transmission line frame pulse, 3
...Output signal, 4...Internal reference frame pulse,
11... Separation circuit, 12.19... Memory circuit, 1
3... Insertion circuit, 14.18... Selection circuit, 15.
16.17...delay circuit, 20...phase comparison circuit.

Claims (1)

[Claims] 1. A first delay circuit (1
6), a second delay circuit (17) that delays the transmission line frame pulse signal by a predetermined amount, and selects and outputs the received data and the output signal of the first delay circuit, and outputs the received data and the output signal of the first delay circuit; a first selection circuit (18) that selects and outputs either the signal or the output signal of the second delay circuit;
and a phase comparison circuit (20
), the delay insertion/removal circuit includes a separation circuit that separates the multi-frame signal from the input signal from the transmission line, a memory circuit that temporarily holds this multi-frame signal and outputs it with a specified phase, and a a third delay circuit that delays the output signal by one frame; and a second delay circuit that selects either the output signal of the memory circuit or the output signal of the third delay circuit based on control of the phase comparison circuit. A selection circuit, and an insertion circuit that inserts the output signal of the second selection circuit into the output signal of the separation circuit and supplies it as the received data to the first selection circuit and the first delay circuit. Features a delay insertion/extraction circuit.