JP3139180B2 - Multiplex controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplexing control device in a transmission system for multiplexing and transmitting a digital audio signal during a synchronization period of a digital video signal.

[0002]

2. Description of the Related Art As a transmission system for multiplexing a digital audio signal with a digital video signal and transmitting the digital audio signal, there is a method of transmitting a digital audio signal by time-division multiplexing during a horizontal and vertical synchronization period of the digital video signal. Standardization work is progressing as an interface between SMPTE
259M).

In such a transmission system, an audio signal input between one line of the video signal is multiplexed and transmitted in the next or subsequent horizontal synchronization period, so that a buffer RAM for the audio signal is required. In a composite video signal, audio signal data is multiplexed in the sync chip level portion of the synchronization signal period. However, there is an equivalent pulse period in which the sync chip level portion is narrow. Since the audio signal data to be transmitted during this period is collectively transmitted during the vertical synchronization period without performing multiplexing, the amount of audio signal data in the buffer RAM greatly changes as shown in FIG. Also, in the case of the component video signal, it is general that the multiplexing of the audio signal is not performed in the vicinity of the line where the video signal is switched, so that the audio signal data amount in the buffer RAM also varies.

FIG. 2 shows a block diagram of a conventional multiplex control device. The input digital video signal A is supplied to the multiplexing timing generation circuit 6 and the multiplexing circuit 8. On the other hand, the input digital audio signal B is generally serial,
After being converted to parallel data D by the audio input circuit 1,
The data is input to the buffer RAM 4 together with the write clock.
The buffer RAM 4 includes a write address counter 4a, a read address counter 4b, and a RAM 4c having two ports for reading and writing. The write address counter is incremented by a write clock C, and the read address counter is incremented by a read clock K. I do.

A multiplex timing generator 6 detects a synchronization period of a video signal to be multiplexed with an audio signal, and generates timing signals M and N for multiplexing. In response to the timing signal M, the audio signal data formatter 7 outputs the read clock K to the buffer RAM 4, reads the audio signal data, converts the data into a packet in a format that can be multiplexed with the video signal, and outputs the packet. This packet O
Is supplied to the multiplexing circuit 8, and the multiplexing circuit 8 switches the digital video signal A or the audio signal data packet O to time division in accordance with the timing signal N and outputs the multiplexed video signal P.

The read and write addresses of the buffer RAM overflow when the power is turned on and when the buffer RAM overflows or underflows.
It is reset to an initial value by a reset signal Q from the underflow detection circuit 9.

[0007]

In the multiplexing control circuit having such a configuration, the average value of the data amount of the audio signal in the buffer RAM changes depending on which line the video signal is input from first. For example, in the transmission of a composite video signal, a case is considered where the amount of audio data in the buffer RAM changes as shown in FIG. 4A during one field. If the video signal input at the time of power-on is during the equivalent pulse period before the vertical synchronizing period, the audio signal data amount at this time becomes an initial state, and as shown in FIG. Assuming that the average value of the data amount becomes small, and that the video signal input at power-on is during the equivalent pulse period after the vertical synchronization period as shown in FIG. 4C, the audio data amount in the buffer RAM is reduced. The average value increases.

As described above, the fact that the average value of the audio data amount in the buffer RAM fluctuates depending on the state when the power is turned on means that the delay time of the transmitted audio signal with respect to the video signal varies. It is extremely inconvenient to delay the video signal later to secure the synchronism between the video signal and the audio signal.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has a constant delay amount of an audio signal with respect to a video signal.
An object of the present invention is to facilitate recovery of synchronization of a video signal and an audio signal.

[0010]

For this purpose, according to the present invention, there is provided a timing generator for generating a timing signal every n fields (n is an integer), a buffer RAM for adjusting a time axis of an audio signal, and Means for detecting the amount of data in the buffer RAM, and means for presetting a read address or a write address in the buffer RAM, wherein the amount of audio data in the buffer RAM for multiplexing or separating digital audio signals is Is checked every n fields, and if this deviates from the specified value, the buffer RAM
Shift the read or write address of
The audio data amount in the buffer RAM for every n fields is kept constant. Also, the specified value can be set arbitrarily.

[0011]

According to the present invention, according to the present invention, the delay of the audio signal with respect to the video signal can be kept constant, and the simultaneous recovery of the video signal and the audio signal can be easily restored. Further, it is possible to have a function of adjusting the delay time of the audio signal without adding a new circuit.

[0012]

FIG. 1 shows an embodiment of the present invention. The input digital video signal A is supplied to the field timing generation circuit 2, multiplex timing generation circuit 6, and multiplex circuit 8. On the other hand, the input digital audio signal B is generally serial, and is converted into parallel data D by the audio input circuit 1 and then, together with a write clock, is stored in a buffer RAM.
Enter 4 The buffer RAM 4 includes a write address counter 4a, a read address counter 4b, and a RAM 4c having two ports for reading and writing. The write address counter is incremented by a write clock C, and the read address counter is incremented by a read clock K. I do.

A multiplexing timing generation circuit 6 detects a synchronization period of a video signal to be multiplexed with an audio signal, and generates timing signals M and N for multiplexing. In response to the timing signal M, the audio signal data formatter 7 outputs the read clock K to the buffer RAM 4, reads the audio signal data, converts the data into a packet in a format that can be multiplexed with the video signal, and outputs the packet. This packet O
Is supplied to the multiplexing circuit 8, and the multiplexing circuit 8 switches the digital video signal A or the audio signal data packet O to time division in accordance with the timing signal N and outputs the multiplexed video signal P.

On the other hand, the field timing generation circuit 2 detects a field period from the video signal A, and generates a pulse once every n fields (n is an integer) as a field timing E. Here, n is the number of fields in which the number of samples of the audio signal in the period is a positive integer, the video signal is NTSC, and the sampling frequency of the audio signal is 48K.
In the case of Hz, the number of audio signal samples is exactly 8008 samples in the 5 frame period of the video signal, so that n = 10 may be selected. In the buffer RAM data amount inspection circuit 3,
At the timing of the frame timing E, an address difference between the read address G from the read address counter 4a and the write address F from the write address counter 4b is obtained, and if this is different from a specified value J set from outside, the read address counter is preset. The pulse H is output. As a result, a read address preset value I obtained by subtracting the specified value J from the write address F calculated by the read address setting circuit 5 is preset in the read address counter 4b. As a result, the effective audio signal data amount in the buffer RAM becomes equal to the specified value. As long as the audio signal is synchronized with the video signal, the audio signal data amount at the subsequent inspection timing becomes equal to the specified value. Also,
When the video signal or the audio signal is switched, the read address is preset at the inspection timing immediately after the switching, and also at the subsequent inspection timing, the audio signal data amount in the buffer RAM is equal to the specified value. Become.

Further, by making the specified value externally configurable, an audio signal data buffer R for multiplexing can be set.
The delay time of the audio signal with respect to the video signal can be controlled using the AM.

Further, the inspection timing is stored in a buffer RAM.
By setting the timing at which the amount of data in the memory is expected to be the smallest, the underflow of the buffer RAM can be prevented by setting the externally set specified value larger than 0, and the underflow of the buffer RAM can be easily prevented. Further, the delay time can be controlled.

In this embodiment, an example in which the field timing is generated from the video signal has been described. However, the field timing may be generated from another signal accompanying the video signal, for example, a composite sync signal.

In this embodiment, an example of a multiplexing apparatus has been described, but the present invention can be applied to a multiplexing / demultiplexing apparatus, and the present invention can be applied to both a multiplexing apparatus and a multiplexing / demultiplexing apparatus. If applied, the delay of the audio signal with respect to the video signal can be fixed to a constant value as a transmission path.

[0019]

As described above, according to the present invention, the timing generator for generating the timing signal every n fields (n is an integer) and the buffer RA for adjusting the time axis of the audio signal are provided.
M, means for detecting the amount of data in the buffer RAM, and means for presetting a read address or a write address in the buffer RAM. The amount of audio data is inspected every n fields, and if this deviates from a specified value, the read address or write address of the buffer RAM is shifted to keep the amount of audio data in the buffer RAM constant every n fields. The delay of the audio signal with respect to the video signal can be kept constant, and the recovery of the synchronization of the video signal and the audio signal can be facilitated. In addition, by setting the specified value arbitrarily, it is possible to have a function of adjusting the delay time of the audio signal without adding a new circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram of a multiplexing control circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional multiplexing control circuit.

FIG. 3 is a diagram showing a change in the amount of audio signal data in a buffer RAM during multiplexing;

FIG. 4 is a diagram showing a change in an audio signal data amount in a buffer RAM in a conventional example.

[Explanation of symbols]

 Reference Signs List 1 audio input circuit 2 field timing generation circuit 3 buffer RAM data amount inspection circuit 4 buffer RAM 5 read address setting circuit 6 multiplex timing generation circuit 7 audio signal data formatter 8 multiplexing circuit 9 overflow underflow detection circuit

Claims (3)

(57) [Claims] 1. A digital video signal according to claim 1, wherein
A multiplexing control device of a transmission device for multiplexing and transmitting a digital audio signal synchronized with a digital video signal, wherein the buffer temporarily stores the input digital audio signal.
RAM and the input digital video signal
The digital audio signal read from the buffer RAM
Overlapping multiplexing means, and the input digital video signal
In the buffer RAM every n fields (n is an integer)
Detecting the data amount of the digital audio signal stored in the
Detecting means and a read address in the buffer RAM
Or control means for presetting the write address.
The control means controls the digital data stored in the buffer RAM.
The data amount of the audio signal is converted into the n field of the digital video signal.
To maintain a constant value for each field in the buffer RAM.
Preset the write address or write address.
A multiplexing control device characterized by the above-mentioned. 2. The method as claimed in claim 1, wherein said control means keeps the temperature constant.
Data amount of the digital audio signal in the buffer RAM
2. The multiplexing control according to claim 1, wherein a predetermined value of the digital audio signal can be arbitrarily varied, and a time delay of the digital audio signal with respect to the digital video signal can be arbitrarily set.
Equipment . 3. The detecting means according to claim 1, wherein
2. The data amount of the digital audio signal is detected on a video line in the buffer RAM where the data amount of the digital audio signal is minimized.
A multiplexing control device as described in the above .