JPH06303585A - Multiplexing/demultiplexing control circuit - Google Patents

Abstract

PURPOSE:To provide a video/audio multiplex circuit for fixedly maintaining the delay of audio signals to video signals by less buffer memories. CONSTITUTION:The minimum value of the data amount of a buffer RAM is inspected over the fixed 'period of time in arm initial mode in a minimum value inspection circuit 11 and simultaneously, time position information at the time is held in a minimum value timing holding circuit 12. When no more address collision is present, a read address is set at a value for which a stipulated value is subtracted from a write address at a timing when the data amount is minimum, a butter RAM data amount is inspected at each timing of minimum data amount in a buffer RAM data amount inspection circuit 8 thereafter and it is confirmed that it coincides with the stipulated value. In the case of detecting non-coincidence, the initial mode is returned and operations are performed again from minimum value retrieval.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplexing and demultiplexing circuit in a transmission system which multiplexes and transmits a digital audio signal during a synchronizing period of a digital video signal.

[0002]

2. Description of the Related Art As a transmission method for transmitting a digital audio signal by multiplexing it with a digital video signal, there is a method of time-multiplexing and transmitting the digital audio signal in the horizontal and vertical synchronization periods of the digital video signal. Standardization work is in progress as an interface between SMPTE
259M).

In such a transmission system, since the audio signal input between one line of the video signal is multiplexed and transmitted in the next or subsequent horizontal synchronizing period, a buffer RAM for the audio signal is required. In the composite video signal, the audio signal data is multiplexed in the sync tip level part of the sync signal period, but there is an equivalent pulse period in which the sync tip level part is narrow. Since the audio signal data to be transmitted during this period are collectively transmitted during the vertical synchronization period without multiplexing, the audio signal data amount in the buffer RAM fluctuates greatly as shown in FIG. Also in the component video signal, it is general that the audio signal is not multiplexed in the vicinity of the line for switching the video signal, and thus the audio signal data amount in the buffer RAM also varies.

FIG. 2 shows an example of a block diagram of a conventional multiplexing / demultiplexing control device. The audio multiplexed digital video signal A is input to the audio data separation circuit 1 and the synchronization signal separation circuit 2, and the audio data separation circuit 1 outputs the audio data B.
However, the sync signal separation circuit 2 detects and separates the sync signal C. The audio data B is reformatted into normal parallel data D by the audio data deformatter 3 and input to the buffer RAM 4 together with the write clock E. The buffer RAM 4 is a write address counter 4a,
It comprises a read address counter 4b and a RAM 4c having two ports for reading and writing. The write clock E increments the write address counter and the read clock F increments the read address counter. The audio output circuit 5 reads the parallel audio data G from the buffer RAM 4 in synchronization with the audio clock I by the read clock F, converts it into a format such as AES / EBU, and outputs it as a serial digital audio signal H.

On the other hand, the synchronizing signal C is input to the field timing detection circuit 6 to detect lines, fields, frames, etc. of the video signal, for example, every audio frame cycle, that is, the video field cycle in which the audio sampling number is a positive integer. One pulse is output as the field timing signal J every time. The address difference calculation circuit 7 calculates the address difference (L−K) between the read address K from the read address counter 4a and the write address L from the write address counter 4b. The buffer RAM data amount inspection circuit 8 outputs a preset pulse M to the read address counter 4b when the address difference (L−K) at the timing of the field timing J is different from the specified value P set from the outside. As a result, the read address preset value N obtained by subtracting the specified value P from the write address L calculated by the read address setting circuit 9 is preset in the read address counter 4b. As a result, the effective audio signal data amount in the buffer RAM 4 becomes equal to the specified value. As long as the audio signal is synchronized with the video signal, the audio signal data amount at the subsequent inspection timing becomes equal to the specified value. When the video signal or the audio signal is switched, the read address is preset at the inspection timing immediately after the switching, and the audio signal data amount in the buffer RAM 4 is the specified value at the subsequent inspection timing. Is equal to

[0006]

In the multiplexing / separation control circuit having such a configuration, by mapping the multiplexing of audio data, it is possible to determine how many samples of audio data are multiplexed in which video line. Buffer RAM
May not be used effectively.

For example, consider a case where a buffer RAM capacity test is performed at the beginning of a certain video line. FIG. 4 shows the change in the buffer RAM capacity when the data is sent by mapping in which the audio data of 3 samples is multiplexed to each video line other than the vertical synchronization period is indicated by A. Similarly, except the vertical synchronization period. The change in the buffer RAM capacity when the data is sent by the mapping in which the audio data of 3 samples or 4 samples is multiplexed on each video line is shown by B.

As described above, since the height and the position of the peaks and valleys of the change in the buffer RAM capacity are changed by the mapping, the read / write address may possibly collide as shown in FIG. 4 in the worst case. Considering the worst state, it is necessary to use a RAM having a capacity that is at least twice the maximum amplitude of a possible change in the buffer RAM capacity, and set the specified value of the address difference to half the RAM capacity.

However, in this case, the RA always used
It is necessary to prepare double the RAM of M capacity, especially LSI
If the buffer RAM is provided inside, the chip cost will increase.

Further, in the normal buffer RAM control in which only the collision between the write address and the read address is detected and the read address is delayed from the write address at the time of collision,
Although the buffer RAM can be effectively used, the amount of audio data in the buffer RAM becomes indefinite, and therefore the delay time between the video signal and the audio signal changes every time the connection is made.

The present invention has been made in view of the above problems. The buffer RAM capacity is effectively used, the delay amount of the audio signal with respect to the video signal is kept constant, and the simultaneity of the video signal and the audio signal is kept. The purpose is to facilitate recovery.

[0012]

In order to achieve this object, the present invention detects a buffer memory for adjusting a time axis when multiplexing or separating a digital audio signal and a data amount in the buffer memory. And a preset means for presetting a read address or a write address in the buffer memory, inspecting the audio data amount in the buffer memory, detecting at least one of the maximum value and the minimum value, and detecting the value. The read address or the write address is manipulated so that the fluctuation of the audio data amount in the buffer memory falls within the buffer memory capacity.

Further, the audio data amount in the buffer memory is inspected for a certain period of time, and a storage means for storing the time position at which the maximum value or the minimum value detected during that period is stored is provided.
At the end of the inspection, the read address or write address is shifted so that the audio data amount at this time position becomes the specified value.After that, the audio data amount in the buffer memory is inspected at this position, and if it deviates from the specified value, the It is detected as a synchronization error with voice, and the process is repeated from the inspection of the amount of voice data in the buffer memory for a certain period.

Further, the delay time in the buffer memory can be arbitrarily set by externally designating this specified value.

[0015]

With the above means, according to the present invention, the delay of the audio signal with respect to the video signal can be kept constant by effectively using a small buffer memory, and recovery of simultaneity between the video signal and the audio signal can be facilitated. can do.

[0016]

FIG. 1 shows an embodiment of the present invention. The audio multiplexed digital video signal A is an audio data separation circuit 1
And the sync signal separation circuit 2, and the sound data separation circuit 1 detects the sound data B and the sync signal separation circuit 2 detects and separates the sync signal C, respectively. The audio data B is reformatted into normal parallel data D by the audio data deformatter 3 and input to the buffer RAM 4 together with the write clock E. The buffer RAM 4 is composed of a write address counter 4a, a read address counter 4b, and a RAM 4c having two ports for reading and writing. The write clock E causes the write address counter 4a and the read clock F causes the read address counter 4a. 4b is incremented respectively. The audio output circuit 5 reads the parallel audio data G from the buffer RAM 4 in synchronization with the audio clock I by the read clock F, converts it into a format such as AES / EBU, and outputs it as a serial digital audio signal H.

On the other hand, the synchronizing signal C is input to the field timing generation circuit 6, and the time position information R of the line, field, frame, etc. of the video signal is detected and output. One pulse is output as the field timing signal J for each video field cycle that is a positive integer.
In the address difference calculation circuit 7, the read address counter 4
Read address K from a and write address counter 4
The address difference (L−K) of the write address L from b is calculated.

First, it is assumed that the inspection mode signal S from the inspection mode determination circuit 10 indicates the minimum value inspection mode.
In this mode, the minimum value detection circuit 11 always detects the minimum value of the address difference (L-K). Each time the minimum value is updated, the time position hold signal T is output to the minimum position timing hold circuit 12, and the time position of the line, field, frame, etc. of the video signal is held at this timing. Also, in this mode, the buffer RAM
The address collision detection circuit 13 detects whether the address collision, that is, the address difference (L−K) becomes 0, and outputs the address collision detection signal U. The selection circuit 14 selects the address collision detection signal U as the read address preset signal M, and the read address setting circuit 9 outputs the value immediately after the write address as the preset data N. Therefore, when an address collision is detected, the read address becomes the value immediately after the write address. In accordance with this, the minimum value of the minimum value detection circuit 11 is updated to an appropriate value.

When it is detected that the address collision does not occur over a certain period such as the voice frame period,
The inspection mode determination circuit 10 switches the inspection mode signal S to the steady mode. In this mode, the variation of the audio data amount in the buffer RAM has already fallen within the buffer RAM capacity by the minimum value inspection mode, and the line, field, frame, etc. of the video signal whose data amount has the minimum value. Time position is the minimum value Timing hold circuit 1
It is held at 2. The coincidence between the minimum value time position V and the current time position information R is determined by the minimum value time position detection circuit 1
5 and outputs the time position coincidence signal W to the inspection mode determination circuit 10.

The inspection mode decision circuit 10 outputs only the first time position coincidence signal W as W'to the selection circuit 14 after the steady mode is entered. In this mode, the selection circuit 14 outputs this time position coincidence signal W'as the preset pulse M of the address counter. The read address setting circuit 9 subtracts the specified value P from the write address L and outputs the read address preset value N. Therefore, the read address preset value N is preset in the read address counter 4b. As a result, the effective audio signal data amount in the buffer RAM becomes equal to the specified value.

Thereafter, the buffer RAM data capacity inspection circuit 8
At the timing of the time position coincidence signal W, it is determined whether or not the address difference (L−K) coincides with the specified value P from the outside. As long as the audio signal is synchronized with the video signal, the audio signal data amount at the subsequent time position matching timing becomes equal to the specified value. If they do not match, it is determined that switching of the video signal or the audio signal has occurred, and the mismatch signal X is output. When the non-coincidence signal X is generated, the inspection mode determination circuit 10 sets the inspection mode signal S to the minimum value detection mode again, the minimum value detection circuit 11 initializes the minimum value, and the above algorithm is repeated.

In this embodiment, only the minimum value of the amount of data in the buffer RAM is obtained, but it is also possible to control the buffer RAM by obtaining the maximum value or both the maximum value and the minimum value. is there.

[0023]

As described above, according to the present invention, the delay of the audio signal with respect to the video signal can be kept constant with the minimum buffer memory capacity, and the simultaneity of the video signal and the audio signal can be recovered. Can be facilitated. Further, by making it possible to arbitrarily set the specified value, it is possible to have a function of adjusting the delay time of the audio signal without adding a new circuit.

[Brief description of drawings]

FIG. 1 is a block diagram of a multiplexing / demultiplexing control circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional multiplexing / demultiplexing control circuit.

FIG. 3 is a diagram showing fluctuations in audio signal data amount in a buffer RAM of the demultiplexing circuit.

FIG. 4 is a diagram showing fluctuations in audio signal data amount in a buffer RAM in a conventional example.

[Explanation of symbols]

 1 audio data separation circuit 2 sync signal separation circuit 3 audio data deformatter 4 buffer RAM 5 audio output circuit 6 field timing detection circuit 7 address difference calculation circuit 8 buffer RAM data amount inspection circuit 9 read address setting circuit 10 inspection mode determination circuit 11 Minimum value detection circuit 12 Minimum value timing hold circuit 13 Collision detection circuit 14 Selection circuit 15 Minimum value timing detection circuit

Claims (4)

[Claims] 1. A multiplexing / separation control circuit used in a transmission device for multiplexing and transmitting a digital audio signal synchronized with a video signal during a sync signal period of the digital video signal, the multiplexing / separation control circuit comprising: A buffer memory for adjusting the time axis when performing the above, a detection means for detecting the amount of data in the buffer memory, and a preset means for presetting a read address or a write address in the buffer memory. The audio data amount in the memory is inspected, at least one of the maximum value and the minimum value is detected, and the read address or the write address in the buffer memory is preset so that these values become a predetermined value. Multiplexing / demultiplexing control circuit. 2. The audio data amount in the buffer memory is inspected for a certain period of time, and a storage means for storing a time position at which the maximum value or the minimum value detected during that time is stored is provided. The read address or write address is shifted so that the data amount becomes the specified value, and then the audio data amount in the buffer memory is inspected at this position, and if it deviates from the specified value, it is detected as a synchronization error between video and audio. The multiplexing / demultiplexing control circuit according to claim 1, wherein 3. The multiplexing / demultiplexing according to claim 2, wherein when a synchronization error between a video signal and an audio signal is detected, the audio data amount in the buffer memory is checked again for a certain period. Control circuit. 4. The method according to any one of claims 1 to 3, wherein the prescribed value of the audio data amount can be arbitrarily changed, and the time delay of the audio signal with respect to the video signal can be arbitrarily set. Multiplexing / separation control circuit.