JPH06141015A - Phase matching circuit - Google Patents

Abstract

PURPOSE:To compress a circuit scale by providing a detection circuit for leading phase difference between first information input in a first frame and first information output in a reference frame, and detection circuit for the leading information in information input and pulse stuffing information in a second frame. CONSTITUTION:The forefront of the first frame is found out by first forefront designation information. The detection circuit 1 detects the leading position of the frame information of the first information represented by second forefront designation information. Also, the presence/absence of pulse staffing for the information part of the second frame is detected by the detection circuit 21. A pulse for writing the information part of the second frame is generated based on the presence/absence of pulse stuffing at a pulse generation circuit 22, and the information part is written on a temporary recording circuit 2. The input of the first information is compared with the output at a phase detection circuit 33, and the phase difference, the forefront designation information from the circuit 1, and the presence/absence information of pulse stuffing from the circuit 21 are compared with each other by a comparator 24, and the forefront designation information of data output and the presence/absence information of pulse stuffing are outputted to a circuit 25. Data from the circuit 2 are outputted as the first frame by the output of an address from the circuit 25.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase matching circuit for outputting data containing stuff information input from several routes in a reference frame after matching the phases.

[0002]

2. Description of the Related Art FIG. 6 shows, for example, Japanese Patent Laid-Open No. 2-205131.
It is the phase matching circuit shown in No. In the figure, 1 indicates the input data Din in time slots TS1 to TS.
Data D1 for 1 frame corresponding to 7 slots of 7
And the head instruction information D2 corresponding to the data slot TD, and outputs the head instruction information D2 to different circuits described later. Reference numeral 4 is head instruction information for correcting the head instruction information D2 input from the head instruction information detection circuit 1 according to a frame pulse (output instruction signal) G input from the head instruction circuit 3 to generate and output head instruction information D3. It is a correction circuit. Reference numeral 2 is a temporary storage circuit for writing the data D1 to the memory, and 5 is 1 output from the temporary storage circuit 2.
The head instruction information inserting circuit inserts the head instruction information D3 into the data D4 after the temporary storage of the frame and outputs the data to the reading side.

Next, the operation will be described. The input data Din input from the writing side is separated by the head instruction information detection circuit 1 into data D1 corresponding to the time slots TS1 to TS7 and head instruction information D2 corresponding to the time slot TD. The data D1 for one frame is stored in the temporary storage circuit 2. On the other hand, the head instruction information D2
Is input to the head instruction information correction circuit 4. The frame pulse G according to the instruction on the reading side is output to the temporary storage circuit 2 and the head instruction information correction circuit 4. The head instruction information correction circuit 4 outputs the head instruction information D3 corrected according to the frame pulse G to the head instruction information insertion circuit 5, where the delay data D4 of D1 from the temporary storage circuit.
And is read as output data Dout on the reading side.

The above is the conventional method of aligning the heads of actually effective information by using the head designating information when the input data has no staff information. When there is staff information, another conventional example is disclosed in Japanese Patent Laid-Open No. 3-26210. FIG. 7 shows this configuration. In the figure, 6 and 7 are memory circuits, 8 is a selection circuit for selecting an input signal and outputs of the memory circuits 6 and 7, and 9 is a control circuit for controlling the selection circuit according to stuff information.

The memory circuits 6 and 7 are memory circuits for giving a time delay of one time slot, and the respective transmission signals obtained by transmitting the input signals in cascade are input terminals (D1 and D2) of the selection circuit 8. ) Has been sent to. When positive staff, negative staff, etc. are generated in the staff processing, the following operation is performed. First, the control circuit 9 instructs to select the input terminal (D1) when a non-stuff instruction is given. When the positive stuff is instructed, the signal at the input end (D2) after the input end (D1) for only one time slot is selected, and when the negative stuff is instructed, the signal applied to each input end (D0) is also selected. Then, a selection control signal is generated so as to be output.

[0006]

Since the conventional phase matching circuit is constructed as described above, the memory for correcting the head designating information and its control circuit, and the memory for stuffing processing and its control circuit. However, there is a problem that the control becomes complicated as the circuit scale increases.

The present invention has been made to solve the above problems, and an object of the present invention is to modify head instruction information and perform stuff processing under a unified control to reduce the circuit scale and facilitate control. And

[0008]

In a phase matching circuit according to the present invention, in information transmission, a first information input detecting circuit for detecting a leading phase of a first information input in a first frame and a standard to be aligned. A first information output detection circuit for detecting a leading position of a first information output in a frame, and a phase difference detection for detecting a difference between a leading phase of the first information input and a leading phase of the first information output. Circuit, and the output of the commonly used phase difference detection circuit is added / subtracted to / from the leading phase detection value of each second information input in the plurality of second information frames to obtain each second information output. The start position is specified. Further, in the invention of claim 2, a phase difference detection circuit for detecting a difference between a leading phase of the first information input and a leading phase of the first information output in the first frame, and a plurality of phase difference detecting circuits in the first frame. Second included
Second identifying the beginning of the second information data in the frame
Information leading instruction information detection circuit, a stuff information detection circuit for detecting stuff information contained in the second frame, a temporary storage circuit for writing the second information data from a designated position and sequentially reading the second information data, An information partial instruction pulse generation circuit that outputs at least either the specified position of the write start of the temporary storage circuit or the read start position from the offset from the beginning of the second information data and the stuff information; An addition value quantized to the number of possible ranges of the head indication information of the second information obtained from the phase difference detection circuit, a phase difference of the output of the phase difference detection circuit, and an output of the head instruction information detection circuit, A comparison circuit for determining the head instruction information of each second information to be included in the reference frame to be aligned is provided from the output of the stuff information detection circuit.

[0009]

In the phase matching circuit according to the present invention, the difference between the leading position of the first information input in the first frame and the leading position of the first information output in the reference frame on the sending side is detected. Based on, the start position of the second information output in each second information frame is calculated. The phase matching circuit according to the second aspect of the invention includes a phase difference between the first information input and the first information output in the first frame, an offset from the beginning of each second information data, and a second frame. The writing position and the reading position with respect to the temporary storage circuit are determined from the stuff information therein, and the leading instruction information of the second information in the reference frame on the output side is determined.

[0010]

EXAMPLES Example 1. First, before describing an embodiment of the present invention, a data structure of a communication frame handled by a phase matching circuit which is an object of the present invention will be described.
FIG. 5 is a diagram for explaining the structure of a communication frame. In the figure, reference numeral 10 is a basic frame, and its head phase 13 is a fixed frame that arrives at a certain fixed cycle. In this frame, the first start indication information 14 is the basic frame 10
It is stored at a fixed offset position from the leading phase 13 of the above, and indicates the leading position 15 of the information of the basic frame.

Reference numeral 11 in FIG. 5B is the basic frame 1.
It is the first frame in which only the information part is extracted from 0 and shown. Reference numeral 12 in FIG. 5C is a detailed frame of the first frame in which the contents of the first frame 11 are written in more detail. However, the second frame is time-division multiplexed to form the first frame 11. By the way, the second head designating information 16 is stored at a fixed offset position from the head position 15 of the first frame, and this second head designating information indicates the head position 17 of the information of the second frame. There is. It is an object of the present invention to align the head position 15 of the information of the basic frame coming from each direction, that is, the head position of the first frame in the frame having this data structure with the reference phase. For this purpose, it is necessary to check what the value of the head position 17 of the information in each second frame is, rewrite the value of the head designating information 16 of the second frame, and adjust the information position. I won't.

An embodiment of the present invention will be described below. FIG. 1 is a configuration diagram of a phase matching circuit which is an embodiment of the present invention. In the figure, the phase alignment circuit 20 for the second frame is composed of the elements described below, and the second frame is multiplexed to form the first frame. The phase adjustment circuits 20 for the second frame are provided in parallel for the number of multiplexed channels. In the example below,
The 28 channels are multiplexed to form the first frame. 1 is the same second head indication information detection circuit as in the conventional example,
Reference numeral 2 is a temporary storage circuit for writing only the information of the portion corresponding to the output pulse of the information partial instruction pulse generating circuit described later. This storage circuit is actually a parallel circuit having the number of bits forming a word. As a new element, 21 is a stuff information detection circuit for the second frame, and 22 is a write position to the temporary storage circuit 2 corresponding to only the information part excluding the overhead part in the basic frame 10 in FIG. Information partial instruction pulse generation circuit 1 for generating a pulse
Is. Reference numeral 24 is a comparison circuit that determines whether or not the output stuff information is generated based on the output of the stuff information detection circuit 21 and the output phase of the phase difference detection circuit 33 described later. Two
Reference numeral 5 denotes an information partial instruction pulse generation circuit 2 that generates a pulse for controlling the reading of the temporary storage circuit 2 by the output of the comparison circuit 24. Reference numeral 26 is a second head instruction information / stuff information insertion circuit for newly inserting the second new head instruction information 16 and stuff information in FIG. 5 by the output of the comparison circuit 24.

Reference numeral 31 is a first information input phase detection circuit for detecting the leading position (15 in FIG. 5) of the information input in the first information frame, and 32 is the first information input phase detecting circuit in the reference frame to be aligned. To detect the reference phase of the information output of the first
2 is an information output phase detection circuit. Reference numeral 33 is a phase difference detection circuit that inputs the leading phases detected by both of them and outputs the phase difference. In the following example, the phase adjustment circuit for the second frame requires 28 channels, whereas the detection portion for the first frame can be shared and only one.

Next, the operation will be described. According to the first head designation information 14 in FIG. 5, the head 1 of the first frame
Find 5 The second head instruction information detection circuit 1 in FIG. 1 detects the head position 17 of the information of the first frame indicated by the second head instruction information 16 at a fixed offset position from this head position. In addition, the staff information detection circuit 2
In 1, the presence / absence of stuff for the information portion of the second frame is detected. A pulse for writing only the information portion of the second frame is generated by the information portion instruction pulse generation circuit 122 depending on the presence or absence of the detected stuff, and only the information portion of the second frame is temporarily stored according to this pulse. Write to 2.

This explanation will be described in more detail. Here, consider the position to be written in the temporary storage circuit 2. The capacity of the temporary storage memory is 8 words, that is, 8 bits in parallel × 8 bits (address 0 to 7), and the second head indication information is 0 to 0.
Consider, for example, the case of changing up to 103. A memory address to be written in the temporary storage circuit is centrally determined by an offset value from the head position of the second frame indicated by the second head instruction information 16, as shown in FIG. Only the information part of the frame is written to the temporary storage circuit. For example, when it is detected that the offset value is 18, the memory address 2 of the temporary storage circuit
It is written from (the third bit from the beginning).

On the other hand, in the phase difference detection circuit 33, the information leading phase 1 of the first frame which is the output of the phase detection circuit 31.
5 is compared with 5 and the first information output head phase which is the output of the phase detection circuit 32 at the reference phase to which this phase should be matched, and the phase difference is counted. Further, the addition value of the head indication information for obtaining the head indication information of the second frame is obtained from the phase difference with reference to the reception indication information. For example, FIG. 4 shows a conversion table of the phase difference / addition value when the possible phase difference in the first frame changes from 0 to 3239 and the start instruction information in the second frame changes from 0 to 103. In FIG. 4, the phase difference from 0 to 3239 is the total number of possible values of the head indication information of the second information of 28 channels 104.
The level is quantized at approximately equal intervals.

Next, in the comparison circuit 24, the phase difference output from the phase difference detection circuit 33, the added value calculated above, the head instruction information received by the second head instruction information detection circuit 1, and the stuff information. Information on the presence or absence of stuff, which is the output of the detection circuit 21, is input, and the information is compared, and the head instruction information for data output and the information on the presence or absence of stuff are output. An example of the operation algorithm of the comparison circuit 24 is shown in FIG.
Shown in.

In FIG. 2, the second head designating information inserted into the data output is the received head designating information added with the above addition value, and the stuff information bit received by the stuff information detecting circuit 21 is adjusted. I am trying. Figure 2
More specifically, the phase difference detection circuit 33 first detects the phase difference and the added value (step 41). When the stuff information detection circuit 21 receives the positive stuff (step 42), the positive stuff is generated at the output side in step 43. Similarly, when the information detection circuit 21 receives negative stuff (step 44), negative stuff is generated at the output side (step 45).

With this algorithm, it is possible to faithfully transfer the positive stuff information and generate a new stuff for the variation of the leading phase of the first frame. The comparison circuit 24 outputs the head instruction information for data output and the presence / absence of occurrence of positive stuff and negative stuff by this algorithm.

The information portion instruction pulse generation circuit 225 generates a pulse that determines the position (address) from which data is read from the temporary storage circuit 2 depending on the head instruction information and whether positive stuff or negative stuff is generated. The relationship between the offset from the head instruction information and the read address is unitarily determined as in the case of writing. For example, FIG. 3 shows an example in which the amount of memory is 8 words and the range of the head instruction information is 0 to 103. Show. Finally, the second head indication information /
In the stuff information insertion circuit 26, the value output from the comparison circuit 24 is set as the head instruction information and the stuff information and used as data. Eventually, we collect 28 channels
It is multiplexed and output as the first frame.

[0021]

As described above, according to the present invention, the phase difference detection circuit for detecting the difference between the leading phase of the first information input in the first frame and the leading phase of the first information output in the reference frame. , The head instruction information detection circuit for the second information input in the second frame,
Since the stuff information detection circuit, the temporary storage circuit, and the information part instruction pulse circuit are provided, the data position is changed depending on the presence or absence of the stuff, the head instruction information of the second information is rewritten, and the position of the second information data is changed. Changes can be made at the same time, which has the effect of reducing the circuit scale.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a phase matching circuit according to an embodiment of the present invention.

FIG. 2 is a flow chart diagram showing processing of a phase difference detection circuit and a comparison circuit according to an embodiment of the present invention.

FIG. 3 is a relationship diagram showing an example of addresses and head information of the temporary storage circuit according to the embodiment of the present invention.

FIG. 4 is a relationship diagram showing an example of quantizing a phase difference into an added value according to an embodiment of the present invention.

FIG. 5 is a configuration diagram showing a data structure of an embodiment of the present invention.

FIG. 6 is a configuration diagram of a conventional phase matching circuit.

FIG. 7 is a block diagram of a conventional stuff information processing circuit.

[Explanation of symbols]

 1 Leading Instruction Information Detection Circuit 2 Temporary Storage Circuit 20 Second Frame Phase Matching Circuit 21 Stuff Information Detection Circuit 22 Information Partial Instruction Pulse Generation Circuit 1 24 Comparison Circuit 25 Information Partial Instruction Pulse Generation Circuit 2 26 Start Instruction Information / Stuff Information Insertion circuit 31 First information input phase detection circuit 32 First information output phase detection circuit 33 Phase difference detection circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shinichi Kosuda 5-1-1, Ofuna, Kamakura City Mitsubishi Electric Corp. Communication Systems Research Laboratories

Claims (2)

[Claims] 1. A first information input detection circuit for detecting a leading phase of a first information input in a first frame, and first information for detecting a leading position of a first information output in a reference frame to be aligned. An output detection circuit; and a phase difference detection circuit for detecting a difference between the leading phase of the first information input and the leading phase of the first information output, each of the second information frames in the plurality of second information frames. A phase matching circuit for designating the start position of each second information output by adding / subtracting the output of the phase difference detection circuit commonly used to the start phase detection value of the information input. 2. A phase difference detection circuit for detecting a difference between a leading phase of a first information input and a leading phase of a first information output in a first frame, and a plurality of phase difference detection circuits are included in the first frame. A second information head indication information detection circuit for identifying the head of the second information data in the second frame; a stuff information detection circuit for detecting stuff information contained in the second frame; From the temporary storage circuit that writes the second information data from the designated position and sequentially reads it, the offset from the beginning of the second information data, and the stuff information, at least the designated position at which the writing of the temporary storage circuit is started. , The information partial instruction pulse generating circuit for outputting any of the read start positions, and the number of the possible range of the leading instruction information of the second information obtained from the phase difference detection circuit From the added value, the phase difference of the output of the phase difference detection circuit, the output of the head instruction information detection circuit, and the output of the stuff information detection circuit, the head of each second information to be included in the reference frame to be aligned. A phase matching circuit equipped with a comparison circuit that determines instruction information.