JP3093211B2 - Phase matching circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a phase matching circuit that matches and outputs data input from several routes.

[Conventional technology]

FIG. 3 is a block diagram of a conventional phase matching circuit.
FIG. 2A shows input data D input to the phase matching circuit.
Shows the _IN, FIG. 2 (C) shows the output data D _OUT to be output from the phase adjustment circuit.

First, the configuration of the input data D _IN will be described. Second
As shown in FIG. 7A, the input data D _IN includes time slots TS1 to TS7 constituting one frame and a time slot TD for storing the position of the time slot TS1, that is, the start position information indicating the start position of the frame. It is composed of As shown in FIG. 2A, the time slot TD is inserted between the time slots TS1 to TS7, and the insertion position is not limited.

Next, a conventional phase matching circuit will be described with reference to FIG. 1 is a head detecting circuit for outputting a frame pulse F for identifying a frame indicated by the head position information by detecting the head position information included in the input data D _IN inputted from the write side (not shown) . Reference numeral 2 denotes a temporary storage circuit for storing data for one frame, that is, time slots TS1 to TS7 and TD according to the frame pulse F. Reference numeral 3 denotes a head instruction circuit that outputs a frame pulse G in accordance with an instruction from a reading side (not shown). Next, the operation will be described. Top detection circuit 1 receives the input data D _IN from writing side, time slot TD
And outputs a frame pulse F. In accordance with the frame pulse F, the temporary storage circuit 2 stores data for one frame. The head instruction circuit 3 outputs a frame pulse G according to an instruction from the reading side.
In accordance with the frame pulse G, the temporary storage circuit 2 outputs one frame of data as read data _DOUT to the read side.

[Problems to be solved by the invention]

It was but connexion, enter a plurality of input data D _IN with different phases, to give the output data D _OUT to match the phases of the time slot TD for storing the head position information indicating the head position of the frame of their input data D _IN If the volumes of only the most to match the phase of the delayed in time slot TD of the input data D _iN phase the phase of the time slot TD other input data D _iN, minute phase difference between both time slot TD other Has a disadvantage that the frame of the input data D _IN must always be output with a delay. For example, when the phase difference between the two time slots TD occurs by three time slots, as shown by the dashed line in FIGS. 3 (a) and 3 (c), the input data having the phase advanced is shown.
D _IN is always the output data D delayed by three time slots
_I had to output it as _OUT .

[Means for solving the problem]

The phase matching circuit of the present invention has the following units.

(A) a head instruction information detecting circuit which inputs data having head instruction information indicating a head position of data, and separates and outputs the head instruction information and a data part other than the head instruction information; (b) a read side (C) a temporary storage circuit for inputting and storing a data part from the head instruction information detection circuit and outputting this data part in accordance with the output instruction signal; (D) a head instruction information correction circuit that corrects and outputs the head instruction information input from the head instruction information detection circuit according to the output instruction signal, and (e) temporarily stores the head instruction information corrected by the head instruction information correction circuit. A head instruction information insertion circuit that inserts and outputs the data into the data portion output from the circuit.

(Operation)

The time position of the time slot for storing the leading instruction information of the input data is changed, the phase of the time slot is adjusted, and the leading instruction information is modified according to the change of the time position.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, and the same reference numerals as those in FIG. 3 denote corresponding parts.

4 is a head instruction information detecting circuit configured to separate the head instruction information D2 corresponding to the data D1 and Detasurotsuto TD of one frame corresponding to the input data D _IN in time slot TS1～TS7. Reference numeral 5 denotes a head instruction information correction circuit that corrects head instruction information D2 input from the head instruction information detection circuit 4 according to a frame pulse (output instruction signal) G input from the head instruction circuit 3, and outputs head instruction information D3. is there. 6 is the data D1 for one frame output from the temporary storage circuit 2.
Head instruction information output from the head instruction information correction circuit 5
This is a head instruction information insertion circuit that inserts D3 and outputs it to the reading side.

Before describing the operation, the head instruction information will be described. As shown in FIG. 2 (a), the head instruction information indicates the relative position between the time slot TD in which the head instruction information is stored and the time slot TS1, that is, the head position of the frame. The lot TD may be inserted at any position. Also, output data D
_OUT phase adjustment is realized by adjusting the time positions of the time slots TD, and there is no need to adjust the time positions of the time slots TS1 to TS7. Therefore, in order to match the phases, it is necessary to change the position of the time slot TD and correct the head indication information of the time slot TD.

 Next, the operation will be described.

Input data D _IN input from the writing side is separated into a head instruction information D2 corresponding to the data D1 and the time slot TD corresponding to Yotsute time slots TS1~TS7 the head instruction information detecting circuit 4. Data D1 for one frame is stored in the temporary storage circuit 2. On the other hand, the head instruction information D2 is input to the head instruction information correction circuit 5. When the frame pulse G according to the instruction on the reading side is output to the temporary storage circuit 2 and the head instruction information correction circuit 5, data D1 is output from the temporary storage circuit 2 to the head instruction information insertion circuit 6. At the same time, the head instruction information D3 corrected according to the frame pulse G is output from the head instruction information correction circuit 5 to the head instruction information insertion circuit 6, where it is inserted into the data D1 and output data D _OUT to the reading side. Is read as

FIG. 2 (b) shows output data in this embodiment. As can be seen from FIG. 2B, the delay at the head position of the data frame is the time slot TD, that is, one time slot. On the other hand, FIG. 2 (c)
In the conventional example shown in (1), the head position of the data frame must be delayed by the phase difference of the input data (in this example, three time slots).

〔The invention's effect〕

As described above, the phase matching circuit of the present invention adjusts the phase of this time slot by changing the time position of the time slot storing the head instruction information, and corrects the head instruction information in accordance with the change of the time position. By doing so, there is an effect that the delay of the output data output from the phase matching circuit can be reduced as compared with the related art.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart of input / output data in the embodiment and a conventional example, and FIG. 3 is a block diagram showing a conventional example. 2... Temporary storage circuit, 3... Head instruction circuit, 4... Head instruction information detection circuit, 5... Head instruction information correction circuit, 6.
… Start instruction information insertion circuit, D _IN …… Input data, D _OUT …
… Output data, D1 …… Data, D2 …… Start instruction information, D3
...... corrected head instruction information, G ... frame pulse (output instruction signal).

Claims (1)

(57) [Claims] An input data in which one frame is composed of head instruction information indicating a relative position to a head position of a frame and a data part, and an insertion position of the head instruction information in one frame is variable. A phase matching circuit for adjusting the phase of the data and outputting the input data by separating the input data into head instruction information and a data part, and outputting an output instruction signal in accordance with an instruction from a reading side. A leading instruction circuit for outputting, a temporary storage circuit for inputting and storing the data part from the leading instruction information detecting circuit and outputting this data part in accordance with the output instruction signal; and a leading input circuit from the leading instruction information detecting circuit. A head instruction information correction circuit for correcting and outputting the instruction information according to the output instruction signal; A head instruction information insertion circuit that inserts the head instruction information into the data portion output from the temporary storage circuit and outputs the data, and changes the position of the head instruction information and changes the content of the head instruction information A phase matching circuit characterized in that: