JPH02119161A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a separated substrate with high adhesive strength by mirror- finishing the main surface of a substrate, forming separating grooves, forming an insulating film on the surface and on the inner surface of the grooves, and then bonding the grooves and a supporting base to each other so that the space therebetween is made vacuum. CONSTITUTION:A first main surface of a semiconductor substrate 10 consisting of an n-type Si monocrystal is mirror-finished and separating grooves 11 are formed therein by etching. Next, an insulating film 12 consisting of an oxide film is formed on the first main surface and on the inner surface of the grooves 11 and a supporting base 13 is bonded thereon. Then, the substrate 10 is ground and polished from a second main surface side thereof to form groove segments to the neighborhood of the grooves 11. Further, the polished surface of the substrate 10 is oxidized to form an oxide film 14 connected to the film 12 on the inner surface of the grooves 11 so that a plurality of separated island-like regions are formed. Therefore, the substrate surface, with high degree flatness, can be joined to the supporting base, and the space formed by the separating grooves and the supporting base is made vacuum, so that a separated substrate with high adhesive strength and high reliability can be obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a dielectric isolation substrate for semiconductor devices, and in particular, to a semiconductor device using a dielectric isolation substrate with small curvature and high reliability, and a method for manufacturing the same. Regarding.

[Prior Art] As a prior art related to a method of manufacturing a dielectric isolation substrate, for example, Japanese Patent Application Laid-Open No. 81-292934.

A technique described in Japanese Patent Application Laid-Open No. 62-24641 is known. This conventional technique involves forming an isolation groove in a Si semiconductor substrate that will become an active region, and after forming an oxide film, filling the isolation groove with polycrystalline Si or the like, flattening its surface, and bonding it to a support. This method involves polishing the semiconductor substrate from the back side and separating it into a plurality of islands.

[Problems to be Solved by the Invention] The above-mentioned conventional technology cannot improve the manufacturing yield (voids) in adhering the semiconductor substrate filled with polycrystalline Si or the like in one isolation groove to the support base, and There is a problem in that the substrate is curved (warped) due to subsequent processing on the substrate, such as heat treatment such as oxidation, diffusion, and annealing.

An object of the present invention is to solve the problems of the prior art, improve the adhesion yield of harmful birds, and ensure the reliability of adhesion in adhesion between a semiconductor substrate in which a separation groove is formed and a support base.
Another object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can reduce the curvature (warpage) of a semiconductor substrate, particularly the curvature and variation thereof that occur during post-process heat treatment.

A further object of the present invention is to provide a method for manufacturing a semiconductor device that can simplify the manufacturing process and reduce the cost of the semiconductor device.

[Means for Solving the Problems] The present invention provides mirror polishing of the surface of a Si semiconductor substrate, forming a separation groove from the surface, forming an insulating film on the surface and the inner surface of the separation groove, and then forming one groove within the separation groove. If the separation groove is not filled with a heat-resistant material such as polycrystalline Si, or the separation groove is filled with a heat-resistant material such as polycrystalline Si to 80% or less of the groove depth, the separation groove and the support stand are Just as space becomes a vacuum,
This is achieved by bonding the Si semiconductor substrate and the support.

[Function] In order to bond the semiconductor substrate, especially the part that becomes the island forming the active region, and the support base without voids and with high reliability, the surfaces of both must have flatness equivalent to a mirror surface, and It is necessary that there are no steps, undulations, foreign objects, etc. Polycrystalline Si filled in the separation grooves has different orientations and crystal grain sizes, making it difficult to achieve a flat, mirror-finished surface, resulting in waviness on the semiconductor surface.

Creates a step. For this reason, in the prior art, the bonding yield was reduced. In the present invention, the separation trench is not filled with anything, but only a part of it is filled with polycrystalline Si, so that the adhesion between the semiconductor substrate and the support is as follows.
Since the surface layers to be bonded are not polycrystalline but single crystal or non-oriented amorphous, and are made of the same material, the adhesive strength can be improved.

In addition, by heat-treating the adhesion between the Si semiconductor substrate and the support base in an oxygen atmosphere, the oxygen gas within the one-separation groove is
It is consumed by forming a silicon oxide film (film thickness of about several nm), and the space formed between the separation groove and the surface of the support becomes a vacuum. Therefore, the adhesion between the Si semiconductor substrate and the support base is poor.

It becomes strong and has high reliability.

In addition, even when high-temperature heat treatment such as diffusion is performed in the process of forming various semiconductor devices in the parts that will become islands in the post-process, the stress distribution within the groove does not change and the semiconductor substrate does not bend (warp). fluctuations can be prevented.

Furthermore, by filling only the bottom of the isolation trench with a heat-resistant material such as polycrystalline Si, when cutting the semiconductor substrate into grooves and forming islands that will become active regions, it is possible to increase margins in the accuracy of controlling the thickness of the trenches. It is possible to make it larger. In other words, polishing and etching to create grooves may vary within the semiconductor substrate, resulting in
This means that it is acceptable for the particles to reach the separation groove.

As a result of an experimental investigation of the relationship between the curved height of the substrate of the semiconductor device according to the present invention, its variation, and the filling rate of polycrystalline Si filled in the separation grooves on the adhesive strength, the following was found.

In other words, when the filling rate of the heat-resistant material such as polycrystalline Si in the separation groove (thickness of the polycrystalline Si, which is the heat-resistant filling material by cross-sectional observation/depth of the separation groove) exceeds 80%, the curvature of the substrate increases. , and its fluctuation also increases. Further, when the above-mentioned filling rate is 50% or less, the variation in adhesive strength becomes small.

These are thought to be caused by the fact that as the filling rate increases, the growth and volumetric shrinkage of polycrystalline Si crystal grains due to heat treatment in the post-process increases, and the stress inside the 1-separation groove increases. It will be done.

[Example] Hereinafter, an example of a semiconductor device and a method for manufacturing the same according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram illustrating a manufacturing method according to a first embodiment of the present invention. In FIG. 1, 10 is a semiconductor substrate, 11
12 is an isolation trench, 12 is an insulating film, 13 is a support base, and 14 is an oxide film.

(1) First, a semiconductor substrate 10 is prepared. This semiconductor substrate 10 is an n-type Si single crystal, manufactured by the CZ method, has a resistivity of 20 to 30 Ωcm, a plane orientation of [111 mm, a diameter of 4″φ, and a thickness of 400 μm, with one isolation groove 11 formed therein. The first main surface on the opposite side has a super mirror finish [
Figure 1(a)].

(2) Forming isolation grooves 11 from the first main surface of semiconductor substrate 10. This separation groove 11 is formed using a mixed solution of hydrofluoric acid, nitric acid, and acetic acid (
70%HNO, :49%HF:100%CH,C00H
(7) Using volume ratio 5:3:3), depth 35μ
- Form by etching [Fig. 1(b)].

(3) An insulating film 12 made of an oxide film is formed on the first main surface of the semiconductor substrate 10 and the inner surface of the isolation trench 11 .

This insulating film 12 is formed by heating at 1200° C. for 5 hours in water vapor. At this time, the thickness of the oxide film formed is 2.0 μm [Fig. 1(c)
].

(4) The support base 13 is adhered to the first main surface side of the semiconductor substrate 1o. The support base 13 is made of the same material as the semiconductor substrate 1°.
They are of the same quality, and the surface to be bonded to the semiconductor substrate 10 has a super mirror finish.

The semiconductor substrate 10 and the support base 13 are bonded by bringing them into contact in an oxygen atmosphere and heat-treated at 1200° C. for 2 hours in an oxygen stream to form an oxidized bond at the interface between the two. Oxygen in the space formed by the separation groove 11 and the support base 13 is consumed by reacting with Si on the inner surface of the separation groove 11 through the support base or the oxide film 12 to generate an oxide film. becomes a vacuum [Fig. 1(d)].

(5) Grind and polish the semiconductor substrate 10 from the second main surface side to form grooves up to the vicinity of the separation grooves. This grinding and polishing is performed by first grinding to approximately 350 μm using a #400 grinder, and then performing mechanochemical polishing using a polishing liquid in which fine silica powder as an abrasive is suspended in an alkaline solvent. The thickness of the semiconductor substrate 10 after polishing is 37 to 38 μm, and the thickness up to the separation groove is 2 to 38 μm.
It is 3 μm [Fig. 1(e)].

(6) The polished surface of the semiconductor substrate 10 is oxidized to form an oxide film 14, which is connected to the insulating film 12 on the inner surface of the isolation groove 11, thereby separating the semiconductor substrate 10 into a plurality of island-like regions. The polished surface was oxidized in steam at 1200°C for 9 hours.3.
A SiO2 film with a thickness of 1 μm was formed [Fig.
f)].

In the first embodiment of the present invention, a dielectric isolation substrate is formed by the above-described steps, and the adhesive strength between the single crystal island and the support base of the semiconductor device manufactured by this embodiment is as follows: It is strong and stable at 140-145 kg/aJ. In addition, the bending height of the semiconductor device is 10 to 20 μm (41φ,
The active area side is convex) and small, and the subsequent process is also inconvenient. Note that the oxidation of the polished surface as shown in FIG. 1(f) does not need to be performed on the entire surface, and may be performed only on the portion where the separation groove is present.

FIG. 2 is a diagram illustrating the manufacturing method according to the second embodiment of the present invention, and FIG. 3 is a diagram illustrating the relationship between the amount of polycrystalline Si filled in the separation groove, substrate curvature, and bonding strength. It is.

In FIG. 2, 20 is a semiconductor substrate, 21 is an isolation trench, 2
2 is an insulating film (Sin2).

23 is an insulating film (Si3N4), and 24 is polycrystalline Si.

25 is a support base, and 26 is an oxide film.

(1) First, a semiconductor substrate 20 is prepared. This semiconductor substrate 20 is an n-type Si single crystal and was manufactured by the FZ method. It has a resistivity of 50 to 60Ω, a surface orientation of [100], a diameter of 41φ, and a thickness of 400 μm, and the first main surface on the side where the separation groove 21 is formed is super mirror finished [Figure 2 (a) ].

(2) Forming a separation groove 21 from the first main surface of the semiconductor substrate 2o. This separation groove 11 was formed by anisotropic etching in a mixed solution of 47% KOH aqueous solution and isoprobil alcohol (85°C) using a thermal oxide film Sin as a mask, and the groove depth was set to 60 μm. . Thereafter, after removing the oxide film of the mask, antimony is diffused to form an n+ diffusion layer (not shown) on the first main surface and the inner surface of the isolation trench 21 [FIG. 2(b)].

(3) The semiconductor substrate 20 is thermally oxidized to form an insulating film 22 made of a silicon oxide film on the first main surface and the inner surface of the isolation trench 21. The formation of this insulating film 22 is as follows.

This is carried out in the same manner as described with reference to FIG. 1(C) in the first embodiment. The thickness of the insulating film 22 is 2.0 μm [second
Figure (c)].

(4) An insulating film 23 made of Si3N4 is further deposited on the substrate 20 on which the oxide film 22 has been formed as described above.

This Si3N4 film is formed to be used as a stopper for selective etching in FIG. 2(f), which will be described later.
The film was formed by a low pressure CVD method using 5iH2Cut2 and NH as raw materials at a substrate temperature of 770°C, a pressure of 0.8 mbar, and a reaction time of 28 minutes to a film thickness of 1000±50 [Fig. (d)].

(5) A polycrystalline silicon film 24 is deposited on the first main surface of the substrate 20 on the side where the isolation trench 21 is formed, on which the insulating film 23 made of Si and N4 films is formed as described above, and the polycrystalline silicon film 24 is deposited in the isolation trench 21.
Fill it. The polycrystalline silicon film 24 is made of SiH, CR2
By atmospheric pressure CVD method using as a raw material, the substrate temperature was 11
It is formed at 50° C. to a thickness of 50 μm on the first main surface. At this time, the inside of the one-separation groove 21 has a film thickness of 70 to
At the same time, a polycrystalline silicon film with a thickness of 85 μm was deposited.

The insulating film 23 made of the Si3N4 film is densified [FIG. 2(e)].

(6) Next, the polycrystalline silicon film 24 deposited on the first main surface as described above is removed, leaving polycrystalline silicon only inside the isolation trench 21. Etching for removing the polycrystalline silicon film 24 was performed in the first embodiment by cooling the five films to 1° C. using the same hydrofluoric acid/oxidant mixture as explained in FIG. 1(b). This was done without stirring. At this time, Si3N
The insulating film 24 made of four films acts as an etching stopper and can keep the first main surface of the semiconductor substrate 20 flat [FIG. 2(f)].

(7) Attach the support base 25 to the first main surface side of the semiconductor substrate 20. The method of adhesion is the same as that described in FIG. 1(d) in the first implementation [FIG. 2(g)].

(8) Grind and polish the semiconductor substrate 20 from the second main surface side to make it into a thin piece. Grinding and polishing for thinning
In the first embodiment, a method similar to that described in FIG. 1(e) is used. However, in the second embodiment of the present invention, it is possible to perform both polishing up to the vicinity of the separation groove 21 and polishing to a position crossing the top of the separation groove 21, thereby increasing the allowable range of the amount of polishing. Since it can be made widely, the amount of polishing can be easily controlled and the manufacturing yield can be improved [FIG. 2(h)].

(9) Oxidize the polished surface of the semiconductor substrate 20 to complete a dielectric insulation isolation substrate. The oxidation of the polished surface is carried out in the same manner as described in FIG. 1(f) in the first embodiment [FIG. 2(i)].

A second embodiment of the invention according to the steps described above.

As explained in FIG. 2(h), the amount of polishing from the second main surface of the semiconductor substrate 20 for single-crystal island separation can be easily controlled; Controlling the amount of polycrystalline silicon filled in the isolation trenches 21 is important for the strength and curvature of the entire substrate.

Figure 3 shows the filling rate of polycrystalline silicon filled in the isolation trench (the ratio of the maximum isolation trench depth to the maximum filling thickness on the cross-sectionally polished surface), the curved height of the semiconductor substrate, and the relationship between the semiconductor substrate and the support base. This shows the relationship with adhesive strength, and this will be explained below.

The sample with a high filling rate was manufactured by grinding the polycrystalline silicon film and then etching it as shown in FIG. 2(f).

As is clear from Figure 3, the adhesive strength is determined by the filling rate of 80
% or less, a value of 140 to 160 kg/aJ can be obtained, and a semiconductor device with sufficient strength can be obtained. However, when the filling rate exceeds 80%, it rapidly decreases and becomes 100%.
If the filling rate is 100%, the surface of the polycrystalline Si filled in the isolation trench and the first main surface of the semiconductor substrate will be flattened and finished on the same plane. This is because it is difficult to do so, resulting in uneven adhesion.

In addition, the bending height of the semiconductor substrate is as small as 100 μm or less when the filling rate is 80% or less, and the pattern accuracy in the subsequent photolithography alignment process is ±0.
It is easy to set the thickness to about 2 μm. In particular, the filling rate is 50
% or less, the height of the curvature can be made 50 μm, and the variation can be made small, making it possible to perform patterning with higher precision in subsequent steps. but,
When the filling rate exceeds 80%, the height of the curvature increases rapidly, and its variation also increases, making it impossible to guarantee patterning accuracy in subsequent steps.

Therefore, it is desirable that the filling rate of polycrystalline Si into the isolation groove be 80% or less.

FIG. 4 is a diagram illustrating a manufacturing method according to a third embodiment of the present invention. In FIG. 4, 30 is a semiconductor substrate, 31
3 is a separation groove, 32 is an insulating film, 34 is a heat-resistant material, 35 is a support base, and 36 is an oxide film.

(1) Similar to FIGS. 2(a) to 2(c) in the second embodiment of the present invention, a separation trench 31 is formed in a semiconductor substrate 30, and an insulation film such as SiO is formed on the surface of the isolation trench 31. A film 32 is formed [FIG. 4(a)].

(2) Next, the insulating film at the bottom of the isolation trench is selectively removed by photolithography, and the single crystal Si inside the semiconductor substrate 30 is removed.
[Figure 4(b)].

(3) Using the CVD method using SiHCQ as a raw material, selective deposition is performed by adding 0.5% to 1% HCfi into the atmosphere, and the single crystal Si in the exposed semiconductor substrate is used as a seed to The crystal 5i34 is estimated to have a thickness of 30 μm [FIG. 4(c)].

(4) Next, after bonding the semiconductor substrate 30 to the support base 35, the semiconductor substrate 30 is ground and polished from its second main surface until it reaches the insulating film of the separation groove 31, and the polished surface is oxidized. Then, an oxide film 36 is formed, and the oxide film 36 is connected to the insulating film 32 made of an oxide film on the inner surface of the isolation groove 31, thereby separating the semiconductor substrate 30 into island shapes [FIG. 4(d)].

The third embodiment of the present invention as described above can also provide the same effects as the first and second embodiments of the present invention.

In addition, in the third embodiment of the present invention described above, FIG.
The selective deposition described in e) can be similarly performed by using a photo-CVD method in which only the separation groove 31 is irradiated with excitation light.

FIG. 5 is a diagram illustrating a manufacturing method according to a fourth embodiment of the present invention. In FIG. 5, 4o is a semiconductor substrate, 41
42 is a separation groove, 42 is an insulating film, 44 is a heat-resistant material, 45 is a support base, and 47 is a resist film.

(1) Similarly to FIGS. 1(a) to 1(C) in the first embodiment of the present invention, an nFR 41 is formed on the semiconductor substrate 40, and an i1! Membrane 4
2 [Fig. 5(a)].

(2) A heat-resistant material 44 made of a polycrystalline silicon film is formed on the first main surface of the semiconductor substrate 40 on which the isolation trench 41 is formed [FIG. 5(b)].

(3) A resist film 47 is applied on the heat-resistant material 44, and the separation groove portion is also shaped into a substantially flat shape [FIG. 5(C)].

(4) By dry etching, the resist film 47 applied above. Separation groove 4 of heat-resistant material 44 made of polycrystalline silicon film
1, and etch back until the insulating film 42 is exposed [FIG. 5(d)].

(5) After removing the resist film 47 remaining in the isolation groove 41, the semiconductor substrate 40 and the support base 45 are bonded, and the isolation groove 41 is
The semiconductor substrate 40 is ground and polished until it reaches 1, completing the dielectric isolation substrate [FIG. 5(e)].

FIG. 6 is a diagram illustrating a manufacturing method according to a fifth embodiment of the present invention. In FIG. 6, 50 is a semiconductor substrate, 51
5 is a separation groove, 52 is an insulating film, 54 is a heat-resistant material, and 58 is a resist film.

(1) Similar to FIGS. 2(a) to 2(C) in the second embodiment of the present invention, a separation trench 51 is formed in a semiconductor substrate 50, and an insulating film 52 made of a 5in2 film is formed on the surface of the isolation trench 51. After the formation, a resist film 58 is applied to the first main surface of the semiconductor substrate 50 except for one molecule 1il 151 [FIG. 6(a)].

(2) Next, a heat-resistant material 5 is formed using an amorphous Si film in the separation groove 51 and on the first main surface of the semiconductor substrate 50 by a vapor deposition method.
4 is estimated [Figure 6(b)].

(3) Next, the heat-resistant material 54 made of the amorphous Si film on the surface of the semiconductor substrate is removed by a lift-off method in which the resist film 58 is decomposed thermally or chemically [FIG. 6(c)] .

(4) Then 1 FIG. 2 in the second embodiment of the present invention (
g) to complete the dielectric isolation substrate by bonding the support base in the same manner as in FIG. 2(i) [not shown].

The fourth and fifth embodiments of the present invention described above also produce effects similar to those of the other embodiments.

[Effects of the Invention] As explained above, according to the present invention, a highly flat substrate surface can be bonded to the support base, and the space formed by the separation groove and the support base is a vacuum. , it is possible to provide a dielectric separation substrate for a semiconductor device with high adhesive strength and reliability between the substrate and the support, and the dielectric separation substrate is substantially composed of a substrate made of single crystal Si and the support Therefore, substrate curvature of the dielectric isolation substrate can be reduced. Further, according to the present invention, it is possible to provide a manufacturing method that can manufacture the dielectric isolation substrate as described above at low cost with fewer steps.

[Brief explanation of drawings]

1 and 2 are diagrams explaining the manufacturing method according to the first and second embodiments of the present invention, and FIG. 3 shows the amount of polycrystalline Si filled in the separation trench in the second embodiment. , diagrams explaining the relationship between substrate curvature and bonding strength, Figures 4, 5, and 6.
The figures are diagrams illustrating manufacturing methods according to third, fourth, and fifth embodiments of the present invention. 10. 20, 30, 40, 50-- Semiconductor substrate, 11. 21, 31, 41, 51... Separation groove,
12゜22.23, 32, 42, 52... Insulating film, 13゜25.35.45... Support stand, 14
, 26, 36... Oxide film, 24, 34, 44.
54. Old... Heat resistant material, 47.58... Resist. Fig. 1 3B2 Fig. 1O: Kison I book & loose 20: Si 23: J111 custom (Si3N4) s2 Fig. 4 Fig. 30: @Thermal material Figure 3 Filling rate (%) by supercrystalline Si soaked outside Figure 5 40: f-4 #4 main plate 44: M iron material 4I: Separation 45: Supporting iodine 42; Color & Ru 4 Otsu Resist

Claims (1)

[Claims] 1. A method for manufacturing a semiconductor device including a dielectric isolation substrate, including: (a) forming an isolation groove from a mirror-finished first main surface of the semiconductor substrate; (b) ) forming an insulating film on the first main surface of the semiconductor substrate and the inner surface of the separation groove; (c) adhering the first main surface of the semiconductor substrate to a support via the insulating film; (d) ) oxidizing at least the upper part of the isolation groove on the second main surface of the semiconductor substrate to remove the oxide film; A method for manufacturing a semiconductor device, comprising the steps of: separating a semiconductor substrate into island shapes by connecting them to an insulating film on the inner surface of a separation trench. 2. A method for manufacturing a semiconductor device including a dielectric isolation substrate, including: (a) forming an isolation groove from a mirror-finished first main surface of the semiconductor substrate; (b) forming an isolation groove from a first main surface of the semiconductor substrate; (c) burying a heat-resistant material in the separation groove; (d)
a step of adhering the first main surface of the semiconductor substrate to a support base via the insulating film; (e) a step of thinning the semiconductor substrate from the second main surface side at least until reaching the separation groove; A method for manufacturing a semiconductor device, characterized in that: 3. A method for manufacturing a semiconductor device including a dielectric isolation substrate, including: (a) forming an isolation groove from a mirror-finished first main surface of the semiconductor substrate; (b) forming an isolation groove from a mirror-finished first main surface of the semiconductor substrate; (c) burying a heat-resistant material in the separation groove; (d)
a step of adhering the first main surface of the semiconductor substrate to a support base via the insulating film; (e) a step of thinning the semiconductor substrate from the second main surface side to the vicinity of the separation groove; (f) A method for manufacturing a semiconductor device, comprising the steps of oxidizing the second main surface of the semiconductor substrate, connecting the oxide film to an insulating film on the inner surface of a separation trench, and separating the semiconductor substrate into island shapes. 4. The method of manufacturing a semiconductor device according to claim 2 or 3, wherein the heat-resistant material is buried in the isolation trench to within 80% of the depth of the isolation trench. 5. The embedding of the heat-resistant material into the isolation trench is performed by using the insulating film formed on the first main surface of the semiconductor substrate and the inner surface of the isolation trench as SiO_2 or a material containing SiO_2 as a main component; A Si_3N_4 film is formed, and the S
Claims 2 and 3 are characterized in that the method is performed by forming a polycrystalline Si film on the i_3N_4 film and then removing the polycrystalline Si film on the first main surface.
5. A method for manufacturing a semiconductor device according to item 4. 6. The heat-resistant material is buried in the separation trench by a lift-off method, and polycrystalline Si or amorphous S is buried only in the separation trench.
5. The method of manufacturing a semiconductor device according to claim 2, 3, or 4, wherein the manufacturing method is performed so that i remains. 7. The heat-resistant material is buried in the separation trench using polycrystalline S.
Claim 2, 3 or 4, characterized in that the method is carried out by selective deposition of i or amorphous Si.
A method for manufacturing a semiconductor device according to section 1. 8. The heat-resistant material is buried in the isolation trench using polycrystalline Si deposited on the entire surface of the semiconductor substrate where the isolation trench is formed.
The method of manufacturing a semiconductor device according to claim 2, 3 or 4, characterized in that the method is carried out by etching back amorphous Si. 9. The semiconductor substrate in which the separation groove is formed and the support are bonded by heating in an oxygen atmosphere, and the oxygen in the space formed by the separation groove and the support is bonded to the semiconductor substrate or the support. Claims 1 to 8 are characterized in that the space is fixed by oxidation of the base and the space is evacuated.
A method for manufacturing a semiconductor device according to item 1 of the items. 10. In a semiconductor device having a dielectric isolation structure including a plurality of insulated and isolated island regions by forming an isolation trench in a single crystal semiconductor substrate and a support base for supporting the island regions, a vacuum is provided inside the isolation trench. A semiconductor device characterized by having a space where