JPH02115961A - Microcomputer - Google Patents

Abstract

PURPOSE:To effectively use an address space by reducing the address space required for the addressing of targeted hardware by selecting one of plural targeted hardware with different process data length by a data length designation signal and a selection signal, and making access to it. CONSTITUTION:An instruction decoder 1 decodes an instruction INS, and the data length designation signal DL is set at a low level when the process data length held by the instruction INS is four bits, and the data length designation signal DL is set at a high level when it is eight bits. Selection control parts 3A and 3B, when the selection signal HS being inputted from an address decoder 2, check the level of the data length designation signal DL, respectively, and a control signal HC1 is outputted from the selection control part 3A when it is set at the low level, then, the targeted hardware 10A is accessed. Also, a control signal HC2 is outputted from the selection control part 3A when the data length designation signal DL is set at the high level, then, the targeted hardware 10B is accessed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer, and particularly to an addressable Mabutsu I10 type microcomputer that can process data of a plurality of data lengths.

[Conventional technology]

Conventionally, in this type of microcomputer, one target hardware with one processing data length is mapped to one address, or one target hardware with two processing data lengths is mapped to one address. The configuration was such that one piece of hardware was mapped, and it was necessary to use multiple addresses to map target hardware with long processing data lengths.

[Problem to be solved by the invention]

The conventional microcomputers mentioned above require at least one address for one target hardware, and are configured to map to multiple addresses especially for target hardware with long processing data length. This method has the disadvantage that the address space required for hardware addressing expands, making it impossible to utilize the address space effectively, and also that the amount of hardware required for addressing increases. Another drawback is that product design is restricted due to the lack of address space.

It is an object of the present invention to reduce the address space required for addressing target hardware so that the address space can be used effectively, thereby reducing the hardware required for addressing and easing constraints on product design. Our goal is to provide a microcomputer that can

[Means to solve the problem]

The microcomputer of the present invention includes an instruction decoder that decodes an instruction and outputs a data length designation signal that specifies the data length of data to be processed according to the processing data length of this instruction, and an instruction decoder that inputs an address signal and that outputs an address of the address signal. is a predetermined address mapping a plurality of target hardwares having different processing data lengths, an address decoder outputting a selection signal for selecting each of the target hardwares at this address, and the selection signal and data length designation. and a selection control section that selects and accesses one of the plurality of hardware in response to a signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

This embodiment decodes the instruction INS and decodes the instruction IN
An instruction decoder 1 outputs a data length designation signal DL that designates the data length of data to be processed according to the processing data length (for example, 4 bits, 8 bits) of S, and an address signal AD is input from an address bus 4. When the address of the address signal AD is an address that maps two target hardwares 10^, 10a with different processing data lengths (each processing data length = 4 bits, 8 bits), each target hardware 10A, 10a of this address, 1
An address decoder 2 that outputs a selection signal HS for selecting 0B, a selection signal HS and a data length designation signal DL.
The configuration includes selection control units 3A and 3B that select and access one of the target hardware 10A and 10B.

Next, the operation of this embodiment will be explained.

Instruction decoder 1 decodes instruction INS and converts this instruction I
When the processing data length of the NS is 4 bits, the data length designation signal DL is set to low level, and when it is 8 bits, the data length designation signal DL is set to high level.

When the selection control units 3A and 3B receive the selection signal H3 from the address decoder 2, the selection control units 3A and 3B each output a data length designation signal D.
The level of L is checked, and if the level is low, the selection control unit 3A outputs the control signal HC1, and the target hardware 10^
is accessed.

The target hardware IOA processes the 4 bit data via the data bussler.

Further, if the data designation signal DL is at a high level, the control signal HC2 is output from the selection control unit 3A, and the target hardware 1
0a is accessed.

FIG. 2 is a block diagram showing a second embodiment of the invention.

This embodiment is applied to the peripheral hardware 20 of the target hardware, which can process 1-bit and 8-bit data.

The operation of this embodiment is almost the same as that of the first embodiment, and the control signals HCI and HC2 control the peripheral hardware 20.
It is determined whether the processing operation is for a 1-bit data length or an 8-bit data length.

In this manner, by providing the selection control units 3A to 3p, only one address is required for addressing the target hardware, and this single address can control a plurality of target hardware.

〔Effect of the invention〕

As explained above, the present invention generates a data length designation signal that designates the data length of data to be processed according to the processing data length of the command by an instruction decoder, and outputs this data length designation signal and the target hardware from an address decoder. By providing a selection control unit that selects and accesses one of a plurality of target hardwares with different processing data lengths based on the selection signal of Because this single address can control multiple target hardware, the address space can be used effectively, thereby easing constraints on product design. This has the effect of reducing the amount of hardware required.

a, 20... Peripheral hardware.

Claims (1)

[Claims] An instruction decoder that decodes an instruction and outputs a data length designation signal that specifies the data length of the data to be processed according to the processing data length of this instruction, and an instruction decoder that inputs an address signal and has multiple addresses with different processing data lengths. an address decoder that outputs a selection signal for selecting each of the target hardware at this address when the address is a predetermined address mapped to the target hardware;
A microcomputer comprising: a selection control unit that selects and accesses one of the plurality of hardware based on the selection signal and the data length designation signal.