JPH04359334A - Microcomputer - Google Patents

Abstract

PURPOSE:To access data, which is mis-aligned across the word boundary on a memory, in one bus cycle. CONSTITUTION:A CPU 25 outputs start address 'Y' of data. An address increment signal generating block 26 generates address increment signals 24a, 24b, and 24c to memory blocks 23a, 23b, and 23c by lower bits AD30 and AD31 of the address and byte control signals 22a, 22b, 22c, and 22d. In the memory block 23a, the one-byte area designated by a value Y/4 of upper 30 bits of the start address of normal data is accessed, and the one-byte area designated by a value Y/4+1 is accessed by input of the address increment signal 24a. Thus, a mis-aligned data storage area can be accessed in one bus cycle.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention uses n bytes (n is a natural number)
Assign one address to each data storage area of Kn
The present invention relates to a microcomputer that can simultaneously access data of bytes (K is an integer of 1 or more).

0002

2. Description of the Related Art FIG. 5 is a schematic diagram showing the structure of a conventional memory. A row decoder 2 to which an upper address is input is connected to a word line 4, and then connected to the memory cell array 1 via the word line 4. Column decoder 3 to which the lower address is input is connected to bit selection line 8 and via bit selection line 8 to bit selection section 7 . A data input/output line 9 is connected to the bit selection section 7 . In the memory cell array 1, word lines 4 and bit lines 5 are arranged to intersect, and memory cells 6, 6, . . . are arranged corresponding to each intersection.
is placed. Each memory cell 6, 6, . . . is connected to a word line 4 and a bit line 5 which intersect with each other at corresponding positions.

Next, the operation of this memory will be explained using positive logic for convenience. In order to access memory, an address is given to the memory. When the upper address among the addresses is given to the row decoder 2, the row decoder 2 decodes the upper address and selects one of the word lines 4 as "
Set to "H" level. A memory cell is accessed via a bit line 5 when a word line 4 connected thereto goes to an "H" level. Among the addresses, lower addresses are input to the column decoder 3.

The column decoder 3 decodes the lower address and sets one of the bit selection lines 8 to the "H" level. In the bit selection unit 7, since the bit selection lines 8 and the bit lines 5 correspond one to one, one of the bit lines 5 corresponds to one of the bit selection lines 8 that has become "H" level. Select and connect to data input/output line 9. For example, when the word line 4c and the bit line 8c are both at the "H" level, the memory cell 6c is accessed via the bit line 5c and the data input/output line 9. That is, one memory cell is accessed in response to one address.

FIG. 6 is a conceptual diagram showing part of a memory map of a conventional 32-bit CPU. The addresses of the data storage areas 40, 41...47, each of which is 1 byte, are:
In that order, they are Y, Y+1, . . . Y+7. The bits of the data bus are sequentially D0, D1, . . . D31 from the most significant bit MSB to the least significant bit LSB. Data storage areas 40 and 44 have bits D0 to D7,
The data storage areas 41 and 45 are bits D8 to D15, and the data storage areas 42 and 46 are bits D16 to D2.
3, data storage areas 43 and 47 are bit D24.
~D31, respectively.

Next, a memory access operation by a conventional 32-bit CPU will be explained with reference to FIG. CPU is 1
Assign one 32-bit address to a byte of data,
Assume that data can be input and output up to 4 bytes at a time. When the CPU accesses memory, it specifies the data location in 4-byte units using the upper 30 bits of a 32-bit address, and also uses the byte control signal to
Specifies whether or not each 1-byte data in the 4-byte data is to be accessed.

[0007] Hereinafter, "Y" will be a multiple of 4. For example 3
When accessing 2-byte data in the data storage area 42 of 2-bit address "Y+2" and the data storage area 43 of "Y+3", the 32-bit address " Data storage areas 40, 41 from “Y” to “Y+3”
, 42, and 43 are designated, and the lower two bytes on the data bus are designated by the byte control signal, and the two bytes of data in the data storage areas 42 and 43 are accessed.

By the way, 32-bit addresses "Y" to "
There are cases where data of 4 bytes or less is stored across two consecutive 4-byte data storage areas specified by the upper 30 bits of ``Y+3'' and ``Y+4'' to ``Y+7'', with the lower 2 bits rounded down. be. The boundary between two data storage areas for 4-byte data is called a word boundary, and the data stored as described above is called misaligned data that straddles the word boundary.

For example, data storage areas 42, 43, 44,
When accessing misaligned 4-byte data that straddles word boundaries stored in 45, the 32-bit address "Y+2" of the first byte 42 is accessed in the first bus cycle.
The data storage area 4 is controlled by a byte control signal that specifies the upper 30 bits of the data bus and the lower 2 bytes of the data bus.
The upper two bytes of the 4-byte data of numbers 2 and 43 are accessed, and the data storage area 44 of 32 is accessed in the second bus cycle.
The lower 2 bytes of the 4-byte data in the data storage areas 44 and 45 are accessed by a byte control signal specifying the upper 30 bits of the bit address "Y+4" and the upper 2 bytes on the data bus.

FIG. 7 is a schematic diagram showing part of the configuration of a conventional 32-bit microcomputer. 32 bit CP
3 via the 30-bit address bus 17a.
2-bit address bus 16, and 32
32-bit data bus 1 via bit data bus 20
9 is connected. The CPU 14 connects the memory blocks 15a, 15b, 15c, 15d via byte control signal lines 22a, 22b, 22c, 22d separately.
is connected to.

The 32-bit address bus 16 connects memory blocks 15a, 15b, 15c,
15d is connected. 32 bit data bus 19
are 8-bit data buses 21a, 21b, 21c, 21d
through the memory blocks 15a, 15b, 15 separately.
c, 15d.

Next, the operation of this 32-bit microcomputer will be explained with reference to FIGS. 5, 6, and 7. Each memory block 15a, 15b, 15c, 15d is composed of the memories shown in FIG. 5, and is connected to byte control signal lines 22a, 22b, 22c, 22d.
through memory blocks 15a, 15b, 15c, 15
When a byte control signal is given to d, the address buses 18a, 18b, 18c, and 18 to which they are connected
An address is received via d, and a 1-byte data storage area corresponding to the received address becomes accessible.

Hereinafter, the addresses on the memory map shown in FIG. 6 will be simply referred to as addresses, and the memory blocks 15a and 15b will be
, 15c, 15d will be described as addresses used within each block as intra-block addresses. CPU 14
The 4-byte data storage area 40, 41, 42, 43 specified by the address "Y" with the lower 2 bits truncated.
Among them, the memory block 15a is the data storage area 40
, the memory block 15b has the data storage area 41,
The memory block 15c stores the data storage area 42, and the memory block 15d stores the data storage area 43 at address "Y/4" within each block.

[0014] The CPU 14 has addresses "Y+2" and "
When accessing the memories in the data storage areas 42 and 43 of ``Y+3'', the upper 3 of the 32-bit address ``Y+2''
The 0 bit "Y/4" is given to the upper 30 bits of the address bus 16 via the address bus 17a, and byte control signals 22c and 22d are output. As a result, the byte control signal 22c is applied to the memory block 15c, and the byte control signal 22d is applied to the memory block 15d.

The memory block 15c receives the upper 30 bits of the address bus 16 via the address bus 18c.
Y/4” and 1 of the block address “Y/4”
Access by the CPU 14 to the byte data storage area 42 is enabled via bits D16 to D23 on the data bus 21c and data buses 19 and 20. Also,
The memory block 15d takes in the upper 30 bits "Y/4" of the address bus 16 via the address bus 18d, and controls access by the CPU 14 to the 1-byte data storage area 43 at address "Y/4" in the block via the data bus 21d. , via bits D24-D31 on data bus 19 and 32-bit data bus 20.

The 1-byte data storage area corresponding to the intra-block address "Y/4" of the memory block 15c is C.
The 1-byte data storage area 42 at the address "Y+2" of the PU 14 is the 1-byte data storage area 42 corresponding to the address "Y/4" in the block of the memory block 15d. Since this is the data storage area 43, the CPU 14 ended up accessing the data storage areas 42 and 43 at addresses "Y+2" and "Y+3".

[0017] The CPU 14 uses addresses "Y+2" to "Y
+5'' data storage area 42, 43, 44, 45. When accessing a misaligned 4-byte data storage area that straddles word boundaries, 32 bytes are accessed in the first bus cycle.
Upper 30 bits “Y/4” of bit address “Y+2”
is applied to the upper 30 bits of the address bus 16 via the address bus 17a, and the byte control signals 22c and 22d are outputted to control the memory block 15.
The 1-byte data storage area 42 at the intra-block address "Y/4" of the memory block 15d and the 1-byte data storage area 43 at the intra-block address "Y/4" of the memory block 15d are accessed.

Furthermore, the CPU 14 starts a second bus cycle and transfers the upper 30 bits of the 32-bit address "Y+4".
The bit "(Y/4)+1" is given to the upper 30 bits of the address bus 16 via the address bus 17a, and the byte control signals 22a and 22b are output to set the intra-block address "(Y/4)" of the memory block 15a. )+1" 1-byte data storage area 44 and the block address "(Y/4
)+1" 1-byte data storage area 45 is accessed.

[0019]

[Problems to be Solved by the Invention] As mentioned above, in conventional microcomputers, when the CPU accesses a misaligned data storage area that straddles word boundaries in memory, it is necessary to activate the bus cycle twice. , there is a problem that the program execution speed is slow. SUMMARY OF THE INVENTION In view of this problem, it is an object of the present invention to provide a microcomputer that allows a CPU to access a misaligned data storage area that straddles word boundaries in one bus cycle.

[0020]

[Means for Solving the Problems] A microcomputer according to a first aspect of the invention includes means for incrementing an address issued by a CPU, and accessing a data storage area of the address and a data storage area of the incremented address in one bus cycle. and means to do so. A microcomputer according to a second aspect of the invention includes means for simultaneously outputting all address bits of the first byte of a data storage area to be accessed, and means for emitting a signal specifying a valid byte on a data bus.

A microcomputer according to a third aspect of the invention includes means for simultaneously outputting all address bits of the first byte of a data storage area to be accessed, means for outputting a byte control signal indicating whether or not the data is misaligned, and a byte control signal. means for generating an address increment signal based on the signal and the address lower bits of the first byte, and selectively applying it to a plurality of memory blocks divided by the address lower bits; Of the data storage area,
Among the data storage area of the memory block to which the address increment signal is not applied and the data storage area of the memory block to which the address increment signal is applied, among the multiple data storage areas specified by the address obtained by adding 1 to the upper bits of the address. and a means for accessing the information.

The microcomputer of the fourth invention includes means for simultaneously outputting all address bits to specify the first byte of the data storage area to be accessed, and a misaligned data access signal for instructing access to the misaligned data storage area. means for generating an address increment signal based on the misaligned data access signal and the address lower bits of the first byte, and means for selectively applying the address increment signal to a plurality of memory blocks divided by the address lower bits; Among the multiple data storage areas specified by the upper bits of the address,
Among the data storage area of the memory block to which the address increment signal is not applied and the data storage area of the memory block to which the address increment signal is applied, among the multiple data storage areas specified by the address obtained by adding 1 to the upper bits of the address. and a means for accessing the information.

[0023]

[Operation] The microcomputer of the first invention has a CPU
The data storage area of the address issued by the address and the data storage area of the address that is incremented by that address are accessed in one bus cycle. The microcomputer of the second invention designates the first byte by simultaneously outputting the address of the first byte of the data storage area to be accessed to the address bus. Given the valid bytes on the data bus,
Starting from the first byte, the data storage area of the specified valid bytes is accessed in one bus cycle.

The microcomputer of the third invention generates an address increment signal based on a byte control signal indicating whether or not data is misaligned and the lower address bit of the first byte of the data storage area to be accessed. An address increment signal is selectively applied to a plurality of memory blocks divided by address lower bits. If multiple data storage areas are specified using the upper bits of the address, one of the specified multiple data storage areas will be
1 in the data storage area and upper address bits of memory blocks to which the address increment signal is not applied.
Among the plurality of data storage areas specified by the address incremented by , the data storage area of the memory block to which the address increment signal is applied is accessed in one bus cycle.

[0025] The microcomputer according to the fourth invention includes:
If the data is misaligned, the CPU outputs a misaligned data access signal. An address increment signal is generated based on this misaligned data access signal and the lower address bit of the first byte of the data storage area to be accessed. An address increment signal is selectively applied to a plurality of memory blocks divided by address lower bits. If multiple data storage areas are specified using the upper bits of the address, specify the data storage area of the memory block to which the address increment signal is not given among the specified multiple data storage areas, and the address obtained by adding 1 to the upper bits of the address. Among the plurality of data storage areas, the data storage area of the memory block to which the address increment signal is applied is accessed in one bus cycle. This allows any microcomputer to access misaligned data that straddles word boundaries in one bus cycle.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained in detail below with reference to drawings showing embodiments thereof. FIG. 1 is a schematic diagram showing the configuration of a memory of a microcomputer according to the present invention. The row decoder 2 to which the upper address is input is connected to the word line 4, and the data output side of the shifter 10a is connected to the data input side of the shifter 10a via the word line 4 to the memory cell array 1 via the word line 4. Connected.

Column decoder 3 to which the lower address is input is connected to bit selection line 8, and via bit selection line 8 to the data input side of shifter 10b. The shifter 10b is connected to the bit selection line 8, and the bit selection line 8
It is connected to the bit selection section 7 via. Bit selection section 7
is connected to the memory cell array 1 via the bit line 5. A data input/output line 9 is connected to the bit selection section 7.

The address increment signal line 12 is connected to the shift signal terminal 11b of the shifter 10b and the AND circuit 1.
It is connected to one input terminal of 3. The other input terminal of the AND circuit 13 is connected to the bit selection line 8a corresponding to the minimum value of the column address among the bit selection lines 8 connecting the shifter 10b to the bit selection section 7, and is connected to the output terminal of the AND circuit 13. is the shift signal terminal 11 of the shifter 10a
connected to a.

In the memory cell array 1, word lines 4 and bit lines 5 are arranged to cross each other, and memory cells 6, 6, . . . are arranged corresponding to each intersection. Each memory cell 6, 6, . . . is connected to a word line 4 and a bit line 5 at corresponding intersection positions.

Next, the operation of this memory cell array 1 will be explained. Shifters 10a and 10b are shift signal terminals 11a
, 11b are at "L" level, the shifters 10a, 11b are at "L" level.
The word line 4 and bit selection line 8 on the input side of 10b are connected to the corresponding word line 4 and bit selection line 8 on the output side. On the other hand, the shift signal terminals 11a and 11b are "H"
'' level, the word line 4 and bit selection line 8 on the input side of the shifters 10a and 10b are shifted by one line in the direction in which the corresponding upper and lower addresses increase, and the word line 4 on the output side is shifted. , are connected to the bit selection line 8.

The word line 4b corresponding to the maximum value of the upper address and the bit selection line 8b corresponding to the maximum value of the lower address are connected to the word line 4a corresponding to the minimum value of the upper address or the minimum value of the lower address, respectively. is shifted to the bit selection line 8a corresponding to the bit selection line 8a. Therefore, when the address increment signal line 12 is at the "L" level, it is similar to the case where the conventional memory cell array shown in FIG. 5 is accessed.

However, when the address increment signal line 12 is at the "H" level, the shift signal terminal 11b of the shifter 10b is at the "H" level, so that the shifter 10b performs the above-described shift operation. When the address increment signal line 12 is at "H" level, the shifter 10b
When the bit selection line 8a corresponding to the minimum value of the lower address becomes "L" level due to the shift operation, the shifter 1
Since the shift signal terminal 11a of 0a is at the "L" level, the shifter 10a does not perform a shift operation.

Address increment signal line 12 is set to “H”.
” level, the shift operation of the shifter 10b causes the bit selection line 8a corresponding to the minimum value of the lower address to go to “H” level.
When the signal reaches the "H" level, the shift signal terminal 11a of the shifter 10a becomes "H" level, so that the shifter 10a performs a shifting operation. Therefore, when the address increment signal line 12 is at the "H" level, the memory cell 6 corresponding to the address "X+1" is accessed in response to the input address "X".

Next, a memory access operation of, for example, a 32-bit CPU that accesses the memory cell array 1 shown in FIG. 1 will be explained. The memory map of this 32-bit CPU is similar to that shown in FIG. 6, and will be explained in conjunction with FIG. Address “Y” with lower 2 bits truncated
” data storage areas 40, 41, 42,
The access operation of the data storage area located within 43, which does not cross word boundaries, is exactly the same as that of conventional microcomputers.

However, when performing memory access to a misaligned data storage area that straddles a word boundary, the first byte of the data storage area is specified using all 32 bits of the address, and the byte control signal is used to specify the first byte of the data storage area. If you specify , memory access is completed in one bus cycle.

For example, data storage areas 42, 43, 44
, 45, the 32-bit address "Y+2" specifies the first byte 42 of the data storage area and all 4 bytes on the data bus are accessed using the byte control signal. Specifying that the byte is valid, data storage areas 42, 43,
44, 45 accesses are completed.

FIG. 2 shows the memory shown in FIG. 1 and the 32-bit C
1 is a block diagram of main parts of a microcomputer showing an embodiment of the present invention using a PU. 32 bit CPU 2
5 is connected to a 32-bit address bus 16 via a 32-bit address bus 17, and to a 32-bit data bus 19 via a 32-bit data bus 20.

The CPU 25 is connected to the address increment signal generation block 26 through byte control signal lines 22a, 22b, 22c, and 22d, respectively.
Also, byte control signal lines 22a, 22b, 22c
, 22d respectively, and memory blocks 23a, 23b, 23c, 15 each having an m×1 byte word configuration (m is a natural number).
connected to d. 32 bit address bus 16 is connected to 30 bit address buses 18a, 18b, 18c, 18
d separately through memory blocks 23a, 23b, 2
3c and 15d.

The memory block 23a is connected to the data bus 21
a to bits D0 to D7 on data bus 19, memory block 23b to bits D8 to D15 on data bus 19 via data bus 21b, and memory block 23c to bits D16 to D23 on data bus 19 via data bus 21c. , memory block 15d
are connected to bits D24 to D31 on the data bus 19 by a data bus 21d, respectively. When the address buses 16 and 17 are designated as address bits AD0, AD1, .

The address increment signal generation block 26 connects address increment signal lines 24a, 24b,
24c respectively to the memory blocks 23a and 23b.
, 23c. memory block 23a,
The address increment signals given to the memory blocks 23b, 23c are
It is given as a signal that increments the address of the memory that makes up the memory. FIG. 3 is a truth table showing the functions of the address increment signal generation block 26 shown in FIG. 2, and "x" in the figure represents an undefined value.

Next, a 32-bit CPU configured as described above
The operation of a microcomputer using this will be explained with reference to FIG. 6, which shows a conceptual diagram of a memory map. When accessing a data storage area that does not cross word boundaries, the CPU
Byte control signals 22a, 22b,
22c, 22d and address lower bits AD30 and A
In combination with D31, the address increment signal generation block 26 does not output address increment signals 24a, 24b, 24c based on the truth table shown in FIG.
Address increment signal 12 for all memories that make up
(see FIG. 1) goes to "L" level. As a result, Figure 7
The memory access operation is exactly the same as that of the conventional microcomputer shown in .

However, when the CPU 25 accesses misaligned 4-byte data that straddles word boundaries in the data storage areas 42, 43, 44, and 45, the 32-bit address "Y+2" is sent to the address bus 17 via the address bus 17. 16, and outputs byte control signals 22a, 22b, 22c, and 22d. In this way, memory blocks 23a, 23b, 23c, 15
Byte control signals 22a, 22b, 22c,
22d, the address buses 18a, 18
32-bit address “Y” via b, 18c, 18d
The upper 30 bits ``Y/4'' of ``+2'' are taken in and used as addresses within each memory block.

Also, since the CPU 25 outputs the byte control signals 22a, 22b, 22c, 22d, the byte control signals 22a, 22b, 22c, 2
2d are all “1” and the 32-bit address is “Y
+2", the address lower bit AD30 is "
1”, and AD31 becomes “0”. Therefore, the address increment signal generation block 26 outputs the address increment signals 24a and 24b as shown in the truth table of FIG.
Do not output c.

Since the address increment signal 24a is output from the address increment signal generation block 26, the address increment signal 12 of each memory constituting the memory block 23a becomes "H" level, and the fetched address "Y/ 4", the memory cell corresponding to the address "(Y/4)+1" in the memory block becomes accessible.

As a result, the memory block 23a can access the 1-byte data storage area 44 at address "Y+4". Also, address increment signal 2
4b is the address increment signal generation block 26
Therefore, the memory block 23b operates in the same way as the memory block 23a, and the memory block 23b operates in the same way as the memory block 23a. Access to the byte data storage area 45 becomes possible.

Therefore, the memory block 23b can access the 1-byte data storage area 45 at address "Y+5" within the memory block. Since the address increment signal generation block 26 does not output the address increment signal 24c, the memory block 23c
Address increment signal 12 of the memory that constitutes
becomes the "L" level, and the memory cell corresponding to the fetched address "Y/4" in the memory block becomes accessible.

As a result, the memory block 23c can access the 1-byte data storage area 42 at address "Y+2" within the memory block. memory block 1
Since 5d is constituted by a conventional memory, it is possible to access the 1-byte data storage area 43 corresponding to the loaded address "Y/4" in the memory block. Therefore, the memory block 15d allows access to the 1-byte data storage area 43 at address "Y+3" within the memory block.

In the end, the CPU 25 accesses the misaligned 4-byte data storage area that straddles word boundaries in the data storage areas 42, 43, 44, and 45 in one bus cycle.

FIG. 4 is a block diagram of main parts showing another embodiment of the microcomputer according to the present invention. In the microcomputer shown in FIG. 2, the address lower bit AD
30 and AD31 and byte control signals 22a, 2
2b, 22c, 22d, address increment signals 24a, 24b, 24c are output based on the address increment signals 24a, 24b, 24c, but when a misaligned data storage area that straddles a word boundary is accessed by issuing a misaligned data access signal from the CPU. is configured to generate a misaligned data access signal and output an address increment signal using a simple logic circuit using the generated misaligned data access signal and lower address bits.

The CPU 27 is configured to issue a misaligned data access signal 28, and this misaligned data access signal 28 is given to the memory block 23a as an address increment signal 24a.
In addition, one input terminal of the AND circuit 29 and three input terminals of the AND circuit 29
A first input terminal of circuit 30 is provided. The other input terminal of the AND circuit 29 and the second input terminal of the 3-input AND circuit 30
Address lower bit AD30 is applied to the input terminal.

The third input terminal of the three-input AND circuit 30 is supplied with the address lower bit AD31. AN
The output of the D circuit 29 is the address increment signal 24.
b to the memory block 23b, and the output of the 3-input AND circuit 30 is fed to the memory block 23c as an address increment signal 24c. The 32-bit CPU 27 is connected to the 32-bit address bus 16 via a 32-bit address bus 17 and to the 32-bit data bus 19 via a 32-bit data bus 20.

Address bus 16 is connected to memory blocks 23a, 23b, 23c, and 15d via 30-bit address buses 18a, 18b, 18c, and 18d, respectively. The memory block 23a is connected to the data bus 21
a to bits D0 to D7 on data bus 19, memory block 23b to bits D8 to D15 on data bus 19 via data bus 21b, and memory block 23c to bits D8 to D15 on data bus 19 via data bus 21c.
Upper bits D16 to D23 contain memory block 15d.
are connected to bits D24 to D31 on the data bus 19 by a data bus 21d, respectively.

Next, the memory access operation of the microcomputer configured as described above will be explained with reference to FIG. When accessing a data storage area that does not cross word boundaries, the CPU 27 sends a misaligned data access signal 2.
8 is not output, the misaligned data access signal 28 is at "L" level, and the address increment signal 24 is
a, 24b, 24c are memory blocks 23a, 23b,
23c. Therefore, memory block 2
The address increment signals 12 (see FIG. 1) of all the memories constituting 3a, 23b, and 23c become "L" level. Therefore, the memory access operation is similar to that of the conventional microcomputer shown in FIG.

However, when the CPU 27 accesses a misaligned data storage area that straddles a word boundary, the misaligned data access signal 28 is output, and the misaligned data access signal 28 becomes "H" level. Therefore, address increment signal 24
a becomes "H" level regardless of address lower bits AD30 and AD31.

[0055] Then, address lower bit AD30 is "
0” and address lower bit AD31 is “1”, address increment signals 24b and 24
Both c become "0". Also, address lower bit AD30 is “1” and address lower bit AD31 is “0”.
'', the address increment signal 24b becomes "1" and the address increment signal 24c becomes "0".

Furthermore, the lower address bit AD30 is “1”
and when address lower bit AD31 is "1", address increment signals 24b and 24c
Both become "1". That is, the address increment signals 24a and 24b shown in the truth table shown in FIG.
, 24c are generated, address increment signals 24a, 24b, 24c are output.

Similar to the memory access operation of the microcomputer shown in FIG. 2, misaligned data storage areas that straddle word boundaries can be accessed in one bus cycle.

In this embodiment, one address bus is allocated to each 1-byte data storage area, and the CPU can access 4-byte data simultaneously via a 4-byte wide data bus. The possible number of bytes is not limited to the number of bytes in the embodiment as long as it is 2 or more bytes.

Furthermore, although the operation has been explained using positive logic, it goes without saying that negative logic may also be used. Further, in this embodiment, one address is assigned to one data storage area, but one address may be assigned to two data storage areas.

[0060]

[Effects of the Invention] As detailed above, according to the present invention,
Misaligned data storage areas that cross word boundaries are
Since it can be accessed in one bus cycle, the number of memory accesses does not increase even when data is misaligned, and it has the excellent effect of providing a microcomputer that can execute programs at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a main part configuration of a memory of a microcomputer according to a first invention and a second invention.

FIG. 2 is a block diagram showing the main part configuration of a microcomputer according to a third invention.

FIG. 3 is a truth table showing the functions of an address increment signal generation block.

FIG. 4 is a block diagram showing the main part configuration of a microcomputer according to a fourth invention.

FIG. 5 is a block diagram showing the configuration of main parts of a memory of a conventional microcomputer.

FIG. 6 is a conceptual diagram of a memory map of the CPU.

FIG. 7 is a block diagram showing the main part configuration of a conventional microcomputer.

[Explanation of symbols]

1 Memory cell array 2 Row decoder 3 Column decoder 4 Word line 5 Bit line 6 Memory cells 10a, 10b Shifter 13 AND circuit 15d Memory block 23a, 23b, 23c Memory block 25
CPU 26 Address increment signal generation block 27
CPU 29, 30 AND circuits 40 to 47 data storage area

Claims (4)

[Claims] Claim 1: One address is assigned to each n-byte (n is a natural number) data storage area of the memory, and two
In a microcomputer in which n-byte data can be accessed by a CPU, a means for incrementing an address issued by the CPU, and a data storage area of the address and a data storage area of the incremented address are accessed in one bus cycle. A microcomputer characterized by comprising means for. 2. One address is assigned to each data storage area of n bytes (n is a natural number) of the memory, and misaligned data of Kn bytes (K is an integer of 2 or more) or more that straddles word boundaries is transferred to the CPU. A microcomputer that can be accessed in one bus cycle by means of a means for simultaneously outputting all address bits of the first byte of a data storage area to be accessed to an address bus, and a means for simultaneously outputting all address bits of the first byte of a data storage area to be accessed, and means for emitting a signal specifying the effective byte, and is configured to specify the first byte and the number of effective bytes, and access the data storage area of the specified number of effective bytes starting with the first byte. A microcomputer characterized by: 3. One address is assigned to each data storage area of n bytes (n is a natural number) of the memory, and misaligned data of Kn bytes (K is an integer of 2 or more) or more that cross word boundaries is transferred to the CPU. A microcomputer that can be accessed in one bus cycle by means of a means for simultaneously outputting all address bits of the first byte of a data storage area to be accessed, and a byte control signal indicating whether or not the data is misaligned. means for generating an address increment signal based on the byte control signal and the lower address bits of the first byte, and means for selectively applying the address increment signal to a plurality of memory blocks divided by the lower address bits; and the address of the first byte. Among the multiple data storage areas specified by the upper bits, the data storage area of a memory block to which an address increment signal is not given, and among the multiple data storage areas specified by the address obtained by adding 1 to the upper bits of the address. , means for accessing a data storage area of a memory block to which an address increment signal is applied. 4. One address is assigned to each n-byte (n is a natural number) data storage area of the memory, and misaligned Kn-byte (K is an integer of 2 or more) data that straddles word boundaries is stored by the CPU. A microcomputer that can be accessed in one bus cycle, and includes means for simultaneously outputting all address bits to specify the first byte of the data storage area to be accessed, and commands to access misaligned data storage areas. means for generating a misaligned data access signal, and generating an address increment signal based on the misaligned data access signal and the address lower bits of the first byte, and selectively accessing a plurality of memory blocks divided by the address lower bits; and a data storage area of a memory block to which an address increment signal is not given among the plurality of data storage areas specified by the address upper bits of the first byte, and an address specified by adding 1 to the address upper bits. 1. A microcomputer comprising means for accessing a data storage area of a memory block to which an address increment signal is applied, among a plurality of data storage areas provided in the memory block.