JPS63245757A - Direct memory access controller - Google Patents

Abstract

PURPOSE:To easily expand addresses at the time of DMA transfer by providing the titled device with a data detector capable of recognizing that an address outputted from a DMA controller reaches an expected value. CONSTITUTION:The DMA controller LSI 11 can correspond to addresses A0-A15. The lower 8 bits A0-A7 of the addresses are outputted from the DMA controller 11 through a bus 12 and the upper 8 bits A8-A15 are outputted through a bus 13. The outputs of the buses 12, 13 are partially branched and inputted to an all-'1' detector 14, and all signals on the bus 13 are turned to all-'1', the detector 14 generates an output 15. The output 15 informs that all the data on the bus 12 and all the data on the bus 13 obtained when an address strobe signal 16 is validated are turned to '1'.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a direct memory access controller (hereinafter referred to as a DMA controller), and particularly to its address extension method.

[Conventional technology]

Conventionally, DMA control LSIs used in micro combinator systems have only had the ability to perform DMA transfer in a 16-bit address space. - In recent years, the amount of data processed by microcomputers has increased, and they often handle data of more than 64 bytes.
An increasing number of microcomputer systems are using four 16M byte spaces specified by byte space or 24 bits.

A DMA with a 16-bit address space is used in such a micro combinator system with an address space of 17 bits or more.
When using a DMA control LSI'i which only has the ability to perform transfers, a circuit is required to extend the address of this LfSI. This DMA controller/I/L
The operation of a microcomputer system with sI address extension will be explained with reference to FIG.

FIG. 4 is a block diagram of a microcombiator system with an address width of 20 bits using a conventional LSI for DMA control. 401 is a microprocessor, 402 is a memory, 403 is an I/(J, and 404 is an LSI for DMA control. , 405 indicates a 4-bit latch, and 406 indicates an 8-bit latch. Also, 411 indicates an address bus AO to A9,
412 is data bus DO~D7.4131d control bus (memory read, memory write, ■10 read.

414 is a hold response signal, 4
15 is a hold request signal, 416 is a DMA request signal, 4
17 is a DMA address enable signal, 418 is an address strobe signal, and 419 is a DMA response signal.

As an example, the operation when DMA transfer is performed from l10403 to the memory 402 to which addresses 30000H to 33FFFH are allocated will be described.

The pre-shield microprocessor sends the 4-bit latch 405 the upper 4 bits of the transfer start address, 3H, D,
The lower 16 bits 00-00H and the number of transfers (33FiI"FH-'3'00'OOH=3) are sent to the MA controller.
Set FFFH-)i. As shown in Figure 6, D
The MA cycle is activated by a DMA request 416 from the l10403 to the DMA controller 404. D
MA controller 404 sends l10403 DMA request 416'! When it receives r, it outputs a hold request 415 to the microprocessor 401 to obtain the right to use the bus. When the hold response 414 is output from the microprocessor 401, the Konbutsu controller 404 sets the DMA address enable 417 and the LAMA address strobe 41.
8. The lower 8 bits of the DMA transfer start address are output to the lower 8 bits of the address bus (00), and the middle 8 bits OOH'i are output to the data bus. 8-bit latch 406
Then, the middle eight bits OOH of the transfer start address from the data bus 412 are latched by the address strobe 418. The output of this 8-bit latch 406 is the middle 8 bits A7 to A15 of the address bus 411, and since the 4-bit latch 405 is connected to the upper A16 to A19, the output of the valley latch is set to the address by the DMA address enable 417. Output on the bus and the address bus is 30000
Indicates address H.

Rewrite is output, and the data read from Ilo is written to address 30000H of the memory.

One DMA cycle is completed by the above series of operations. If DMA request 416 is active at the completion of a DMA cycle, the next DMA cycle continues. 2
In subsequent DMA cycles, the DMA address strobe 418 to the 8-bit latch 406 is not output and the previous value is maintained unless a carry occurs from the lower 8 bits of the address to the middle 8 bits of the address. The number of transfers is 3FFFH
The DMA transfer is completed when the DMA address reaches the address limit of DM using a conventional DMA controller
When the value of the upper 4 bits of the A transfer address is different from 3FFOOH to 40OFFH, it is necessary to change the data written to the 4-bit latch 405 by the microprocessor 401 during the iDMA transfer. Therefore, in this case, the DMA transfer is divided into two times, each with its own DMA transfer.
MicroProcera v401 4 bit latch 4 before time
It is necessary to set the values of 3H and 4H in 05, which has the disadvantage that DMA control becomes complicated.

[Problem that the invention seeks to solve]

As mentioned above, when a DMA controller using a conventional DMA control LSI extends the entire address, a latch is provided to store the address data of the address extension part, and the preset data of this latch and the f , the DMA address was the address that SH could access and the money. Therefore, it is necessary to rewrite the data in this latch to set an extended address every time a DMA transfer is performed across the extended range, which has the disadvantage of complicating DMA control.

[Means for solving problems]

In the direct memory access controller of the present invention,
The present invention is characterized in that it is equipped with a data detector which can input a DMA address value, detect that the address value has reached a preset state, and output this state as a signal.

〔Example〕

1 and 2 show an embodiment of the present invention, FIG. 1 shows an address extension method using a conventional DMA control LSI, and FIG. 2 shows an iDMA control LSI using this method. This is an example in which it is incorporated into the inside of.

(1) First, the case shown in FIG. 1 will be explained. 11 is a conventional DMA controller LSI with address A.

It can handle up to A1s. 12 is a bus for the lower 8 bits of the address AO to A7, 13 is the bus for the upper 8 bits of the address 88 to
Bus for A15, 14 is the first loop detector, 15 is the output signal of 14, which informs the data on path 12 and the address strobe signal of 16 that the data on bus 13, which has become valid, is all 1. It's a signal. Incidentally, the value set in the data detector may originally be any value, but in order to simplify the explanation, all l detection is assumed here.

The case where this expansion method is used in a microcomputer system in which the DMA controller has a total address width of 20 bits will be described with reference to FIG.

In this figure, 301 is a microprocessor, 302 is a memory, 303 is Ilo, and 304 is a DMA controller using an address extension signal according to the present invention, and the same as in FIG. 1 applies to these positions. 305 is a 4-bit counter, 3
06 represents 8-bit latch gold. Also, 311 is an address bus AO to AI9, 312 is a data bus), 314
is a hold response, and 315 is a hold request.

316 is DMA request, 317 is DMA address enable, 318 is DMA address strobe, 319 is D
The MA response, 320, is the output of the all-one data detector (hereinafter referred to as carry) and is the signal line 15 in FIG. It is assumed that each of the signals 314°, 315, and 317 also includes the backlash controller LSIII in FIG.

Further, 12, 13, and 16 in FIG. 1 are respectively inscribed with 311, 312, and 318 in FIG. 3, respectively.

With the above configuration, the memory 302 of 30000 to 33FFFH
The operation when performing j5 DMA transfer from Ilo 303 to Ilo 303 is similar to that of the microcomputer system using the conventional DMA controller described above, except that the upper 4 bits of the address are loaded into a 4-bit counter instead of into a 4-bit latch.

Next, a case where the DMA transfer address is 3FFOO to 40OFFH will be explained. As in the case of DMA transfer to the memory 3000 to 33FFH described above, the microprocessor transfers the upper 4 bits 3H of the transfer start address to the 4-bit counter 305 in advance.

Lower 16 bits) FF in LS111 in DMA controller
OOH and number of transfers 40OFF-3FFOOH:IF
Set FH. As in the case of microcomputer systems using conventional DMA controllers, D
The MA cycle is activated and DMA transfer is performed. DM
When the lower 16 bits of the A transfer address are all 1, such as 3FFFFH, a carry is output from the data detector 14 in FIG. This is communicated to the 4-bit counter 305 via signal 320.

That DMA? When the cycle is completed and all addresses of the DMA controller 11 are OK for the next DMA cycle, the output 15° 320 of the data detector becomes inactive. 4-bit counter 305 at the trailing edge of this carry
Complete the count up. As a result, in the next DMA cycle, the output of the 4-bit counter changes from 3H to 4H, the DMA address changes to 40000H, and DMA transfer continues up to address 40OFFH. This is shown in FIG.

(2) Figure 2 shows the data detector f: DMA mentioned in (1).
This is an example in which it is incorporated into a controller LSI. Here, 21 is an address counter, 22 and 23 are buffers, 24 is a data 10=detector, and 25 is necessary inside the DMA controller LSI. Also, 2a is the output of the address counter, and the lower 8 bits of the address AO to A72b are the output of the address counter, and the upper 8 bits of the address are 88 to AI5, 2c.
is address output AO~A7, 2d is data output DO~D
7°2e represents the all l detection output.

The transfer method when using this embodiment is the same as in the case (1) above. The lower 8 bits of the address of 2C are the first
The upper 8 bits of address 12 and 2d in the figure are B2 in Figure 1.
The output of the detector at e corresponds to 15 in FIG.

〔Effect of the invention〕

As explained above, the present invention is equipped with a data detector that can recognize when the address output from the conventional Otori controller has reached the expected value, thereby easily changing the address during DMA transfer. Expansion will be possible.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of the present invention in which the data detector is an LS
The block diagram in the case where it is outside I, Figure 2 is also DM
A block diagram inside the A controller LSI,
FIG. 3 is a block diagram of a microcomputer system with a 20-bit address using a DMA controller according to the present invention, FIG. 4 is a block diagram of a microcomputer system with a 20-bit address using a conventional DMA controller, and FIG. Timing chart in Figure 3, No. 6
The diagram is based on the timing chart in Figure 4. 11...DMA controller LSI, 1'2.
...Address lower 8 bits AO to A7.13...
...address top 8 bits 88~A15.14...
...Data detector, 15...Data detection signal, 16...Address strobe 1 word, 21
...address counter, 22...buffer, 23...buffer, 24...f
- Evening detection! , 25...DMA control L
SI, 2a...Address lower 8 bits AO to A
7.2b...Address top 8 pictograms A8-A1
5.2C...2a output, 2d...2
b output, 2e...data detection signal, 301.
...Microprocessor, 302...Memory, 303...Ilo, 304...
DMA controller, 305...4-bit counter, 306...8-bit latch, 311...
...Address bus AO~A19.312...
・Data bus DO~D7. 313...Control bus, 314...Hold response, 315...
...Hold request, 316...DMA request, 317...DMA address enable, 3
18...DMA address strobe, 319.
...DMA response, 320...Data detection signal (carry), 401...Microprocessor, 402...Memory, 403...
■10.404...DMA controller, 40
5...4 bit latch%406...8
Pitstratch, 411...Address AO~A1
9.412...Data bus Do-D7.413
...Controller no. 414...Hold response, 415...
Hold request, 416...DMA request, 417
...DMA address enable, 418...
...DMA Adpath Robe, 419...D
MA response.

Claims (1)

[Claims] In a direct memory access controller using an LSI for direct memory access control, the value of a counter that outputs the data transfer address of the LSI is input, and when the value reaches a preset value, a detection signal is output. A direct memory access controller characterized in that it is equipped with a data detector.