JPH02113643A - Transmission line code error monitoring system - Google Patents

Abstract

PURPOSE:To obviate a descrambling circuit in a repeater by synchronizing the resetting period of an M system generating circuit to an error monitoring section period and further, selecting the resetting period so that the M system generating circuit can be reset at the even number of times in one error monitoring section. CONSTITUTION:After an information signal is inputted from an input terminal 1 and parity-counted by a parity counting circuit 2, the exclusive OR is obtained in a pseudo random signal generated by an M system generating circuit 3 and an exclusive OR circuit 5 and scrambling is applied. Thereafter, the parity bit is added by a parity bit adding circuit 6 and outputted from an output terminal 7. By the resetting pulse generated periodically by a resetting timing generating circuit 4, the M system generating circuit 3 is reset for (m) bits; the parity counting circuit is reset for 2m bits and the parity counting is executed for 2m bits. Thus, in the repeater, when the transmission line code error monitoring is performed, a descrambling circuit is made unnecessary.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a transmission path code transmission system used in PCM communication, and more specifically, to a system for monitoring code errors in a PCM transmission path.

(Prior Art) In digital transmission, scrambling is generally applied on the transmitting side to suppress jitter occurring in the transmission path.

In a system that uses parity to monitor code errors on a transmission path, it is desirable to perform parity counting before scrambling in order to make the monitoring interval as long as possible. In such a case, if the repeater performs code error monitoring, the error monitoring must be performed after descrambling.

(Problems to be Solved by the Invention) Therefore, the conventional transmission line code error monitoring system requires a descrambling circuit in the repeater, which has the disadvantage of increasing the circuit scale.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks, and to provide a transmission line code error monitoring system that does not require a descrambling circuit in a repeater.

(Means for Solving the Problems) In order to achieve the above object, the transmission path code error monitoring method according to the present invention is such that when transmitting a digital signal using a transmission path, the transmitting side divides information bits into a fixed number of bits. A monitoring bit is added to these information bits and sent to the transmission path, and the receiving side compares the received information bits with the monitoring bit to detect code errors on the transmission path.
In a transmission line code error monitoring system using a parity bit method, on the transmitting side, after performing parity counting, a scramble value is added, a parity bit is added after the scramble value is applied, and the M-sequence generation circuit of the scramble circuit is reset. Synchronize the cycle with the error monitoring interval cycle, and further select the reset cycle so that the M-sequence generation circuit is reset an even number of times during the error 9 monitoring interval, and descramble the received signal at the repeater. The parity count of the information bits is performed without any errors, and the count results are compared with the monitoring bits to monitor errors.

(Example) Hereinafter, the present invention will be explained in more detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a transmission line code error monitoring system according to the present invention.

The information signal is inputted from an input terminal 1, subjected to parity counting by a parity counting circuit 2, and then exclusive-ORed with a pseudo-random signal generated by an M-sequence generation circuit 3 in an exclusive-OR circuit 5. , scrambled. Thereafter, a parity bit is added to the parity bit adding circuit 6 and outputted from the output terminal 7.

In addition, the parity counting circuit 2 receives reset pulses periodically generated by the reset timing generation circuit 4.
Then, the M-sequence generation circuit 3 is reset, and parity counting and scrambling are periodically reset.

FIG. 2 is a diagram showing the reset timing of the M-sequence generation circuit and the parity counting circuit in this embodiment.

The M-sequence generation circuit 3 is reset every m bits. Further, the parity counting circuit is reset every 2m bits, and parity counting is performed every 2m bits.

The parity counting circuit reset timing is synchronized with the M-sequence generation circuit reset timing, and occurs at the same time once every two M-series generation circuit reset timings. In other words, the parity counting period is 2m bits, the scramble reset period is m bits, and the scramble is reset twice during one parity counting period.

Here, consider the change in parity before and after scrambling. It can be seen from the nature of scrambling that the M-sequence generation circuit output and the information signal are exclusively ORed, that when the M-sequence generation circuit output is "1", the information signal is inverted and the parity changes.

“1” during one scrambling period of the M-sequence generation circuit output.
'' is n, then in one parity counting section, there are two scrambling periods in the section, so the number of "1"s in the output of the M-sequence generation circuit is 2n. In other words, 1
The number of information bits that are inverted during the parity counting interval is 20, that is, an even number of bits are inverted. This indicates that no change in parity occurs before and after scrambling.

From the above, if you just want to monitor transmission line code errors, count the parity of the information bits without descrambling.
It turns out that it is sufficient to check the parity bit.

Therefore, when error monitoring is performed in a repeater, a descrambling circuit is not required, and transmission line code error monitoring becomes possible by counting the parity of the input information signal and comparing it with the parity bit.

In this embodiment, the number of scramble resets in one parity counting period is set to two, but the same effect can be obtained if the number of scramble resets is an even number.

(Effects of the Invention) As explained above, according to the present invention, a descramble circuit is not required when monitoring transmission line code errors in a repeater, and the device can be made smaller and lower in price. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the transmission line code error monitoring system according to the present invention, and FIG. 2 is a timing chart showing the M-sequence generation circuit reset timing and the parity counting circuit reset timing of the embodiment. 1... Signal input terminal 2... Parity counting circuit 3
... M sequence generation circuit 4 ... Reset timing generation circuit 5 ... Exclusive OR circuit 6 ... Parity pit addition circuit 7 ... Signal output terminal

Claims (1)

[Claims] When transmitting a digital signal using a transmission path, the transmitting side divides the information bits into a fixed number of bits, adds monitoring bits to these information bits, and sends them out to the transmission path.
In a transmission path code error monitoring method using a parity bit method, the receiving side compares the received information bits with the monitoring bits to detect code errors in the transmission path, and the transmitting side performs scrambling after performing parity counting. Apply
After the scrambling, a parity bit is added, and the reset synchronization of the M-sequence generation circuit of the scrambling circuit is synchronized with the error monitoring period period, and the M-sequence generation circuit is activated an even number of times during one error monitoring period. The feature is that the reset period is selected so that the signal is reset, the repeater performs parity counting of the information bits without descrambling the received signal, and the counting result is compared with the monitoring bit to perform error monitoring. Transmission path code error monitoring method.