JPS60254857A - Error generating circuit - Google Patents

Abstract

PURPOSE:To prevent a decrease in the random property of an error by inserting the error into an input digital signal according to the correlation output of the output of scrambling and a PN pattern generator. CONSTITUTION:An (n)th-degree PN pattern generator 24 generates (n) phases of PN patterns with a period of 2<n>-1 with an input clock and supplies them to a correlation detector 25. Further, an (m)th-degree scrambler 27 scrambles an input signal to generate and supply (m) phases of scramble patterns to the correlation detector 25. The correlation detector 25 detects the correlation between the (n) phases of PN patterns and (m) phases of scramble patterns and sends its output to an error inserting circuit 26. The error inserting circuit 26 inverts the polarity of the input signal from a terminal 21 and outputs it only when the correlation output exists to insert the error, and passes the input signal as it is when off.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a random error generation circuit that inserts errors into digital signals.

(Background Art) Conventionally, a circuit with a function of generating random errors in such a field is as shown in FIG. 2, n7! It is composed of an AP N pattern generator 14, an AND gate 15, and an error insertion circuit 16. A random pattern with a mark rate of 1/22 generated by ANDing the outputs of the k phase among the n-phase PN patterns each having a mark rate of 1/2 from the AP N-bang generator 14 in the AND gate 15. The error insertion circuit operates to generate random errors with an error rate of 172 in the input signal using the error insertion circuit. However, the error generating circuit with this configuration has a drawback that the randomness of errors decreases in a region where the error rate is low.

(Problem of the Invention) An object of the present invention is to solve the above-mentioned problems of the prior art and to realize a circuit that generates random errors with high randomness even in a region with a low error rate. is an error generation circuit that inserts random errors into an input digital signal and outputs it, which includes a scrambler that scrambles the input signal, a PN stamp generator that generates a PN pattern, and a link between the output of the scrambler and the PN pattern generator. The error generating circuit includes a correlation means for taking a correlation with an output, and an error insertion circuit for inserting an error into an input digital signal according to the correlation output obtained from the correlation means.

(Structure and operation of the invention) FIG. 1 is a circuit diagram showing an embodiment of the invention, in which 24 is an n-th PN pattern generator, 27 is an m-th scrambler, and 25 is a circuit diagram showing an embodiment of the invention.
26 is a correlation detector, 26 is an error insertion circuit, 21 is an input terminal for an input signal, 22 is an input terminal for a clock, and 23 is an output terminal for an output signal. The input terminal 21 is connected to the correlation detector 25 and the error insertion circuit 26, and the clock input terminal 22 is connected to the m-th scrambler 27 and the n-th PN pattern generator 24, and the clock input terminal 22 is connected to the m-th scrambler 27 and the n-th PN pattern generator 24. The signal and the n-phase signal outputted from the n-stage PN bang generator 24 are connected to a correlation detector 25, and the correlation output signal outputted from the correlation detector 25 is connected to an error insertion circuit 26. The output signal outputted from 26 is connected to the output terminal 23.

The n-th order PN bang generator 24 generates 2-1 by the input clock.
A PN pattern having a period of n phases is generated and this is fed to a correlation detector. In addition, the m-th scrambler 27 scrambles the input signal and generates an m-phase scramble button.
This is given to the correlation detector 25. The values of m and n may be equal. The correlation detector 25 takes the cross-correlation between the n-phase PN button sent from the PN pattern generator and the m-phase scramble button sent from the m-phase scrambler, and sends the correlation output to the error insertion circuit 26. Output.

The error insertion circuit inserts an error by inverting the polarity of the input signal sent from the input terminal 21 and outputting it only when the correlation output sent from the correlation detector 25 rises, and the correlation output rises. When not, a random error corresponding to the correlation detection function of the correlation detector 25 is inserted into the input signal as in 6 or more in which the input signal is passed through as is, and is output to the output terminal 23. Since the scramble pattern obtained by scrambling the input signal and the PN pattern generated by the PN pattern generator are generally uncorrelated, the correlation detector 2
If the cross-correlation between the two is taken in step 5, a random bump on the time axis can be obtained from the output.

For example, the correlation detector may detect each phase of the scramble pattern and P
Match each phase of the N pattern with the same number (or complementary number)
The phases of are taken in pairs, and when all pairs match, a correlation output is generated.

(Effects of the Invention) As described above, the present invention provides a scrambler and a scramble pattern for scrambling input signals, and can be used for error evaluation tests of various digital communication devices.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional error generating circuit. 21; Input signal, 22; Input clock, 23; Output signal, 24; PN bang generator, 25; Correlation detector, 2
6; error insertion circuit, 27; scrambler. Patent applicant: Oki Electric Industry Co., Ltd. Patent application agent: Megumi Yamamoto

Claims (4)

[Claims] (1) In an error generation circuit that inserts random errors into an input digital signal and outputs it, there is a scrambler that scrambles the input signal, a PNN vine generator that generates a PN pattern, and the output of the scrambler and the PNN meta generator. What is claimed is: 1. An error generation circuit comprising: a correlation means for taking a correlation with an output of the error generating circuit; and an error insertion circuit for inserting an error into an input digital signal according to a correlation output obtained from the output of the correlation means. (2) The PNN meta-generator creates a PN pattern using a generating polynomial other than the generating polynomial of the scrambler.
2. The error generating circuit according to claim 1, wherein the error generating circuit is a NN meta-generator. (3) The correlation means connects each phase of the scramble pattern to P
The first aspect of the present invention is characterized in that it is configured to match each phase of the N patterns by pairing phases with the same number, and to generate a correlation output when all the pairs match. Error generating circuit described in section. (4) The correlation means connects each phase of the scramble pattern to P
The first aspect of the present invention is characterized in that it is configured to match each phase of the N pattern by pairing phases of complementary numbers, and to generate a correlation output when all the pairs match. Error generating circuit described in section.