JP2676836B2 - Transmission line code error monitoring system - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a transmission line code transmission system used for PCM communication, and more particularly to a code error monitoring system in a PCM transmission line.

(Prior Art) In digital transmission, it is general that scramble is applied on the transmission side in order to suppress the jitter generated in the transmission path.

Then, in the method of monitoring the code error in the transmission line by using the parity, it is desirable to perform the parity counting before scrambling from the viewpoint of keeping the monitoring section as long as possible. In this case, when the code error is monitored by the repeater, the error monitoring must be performed after descrambling.

(Problems to be Solved by the Invention) Therefore, the conventional transmission line code error monitoring system has a drawback in that the descramble circuit is required in the repeater, which increases the circuit scale.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks and to provide a transmission line code error monitoring system in which a descrambling circuit is unnecessary in a repeater.

(Means for Solving the Problem) In order to achieve the above object, the transmission line code error monitoring method according to the present invention uses a transmission line to transmit a digital signal, and the transmitting side transmits a constant number of information bits. Separated by, a monitoring bit is added to these information bits and sent to the transmission line, and the receiving side compares the received information bit with the monitoring bit to detect a code error in the transmission line. In the path code error monitoring method, the transmitting side performs a parity count, then scrambles, adds a parity bit after the scrambling, and monitors the reset cycle of the M-sequence generating circuit of the scramble circuit for the error monitoring. The reset cycle is selected so that the M-sequence generating circuit is reset even number of times during one error monitoring interval in synchronization with the interval cycle. On the other hand, the repeater counts the parity of the information bit without descramble the received signal and compares the count result with the monitoring bit to perform error monitoring.

Hereinafter, the present invention will be described in more detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a transmission line code error monitoring system according to the present invention.

The information signal is input from the input terminal 1 and subjected to parity counting by the parity counting circuit 2 and then subjected to exclusive OR in the exclusive OR circuit 5 and the pseudo random signal generated by the M-sequence generation circuit 3. It can be scrambled. After that, the parity bit is added by the parity bit adding circuit 6 and output from the output terminal 7. Further, the reset pulse generated periodically by the reset timing generating circuit 4 resets the parity counting circuit 2 and the M-sequence generating circuit 3, and periodically resets the parity counting and scrambling.

FIG. 2 is a diagram showing the reset timing of the M-sequence generation circuit and the parity counting circuit in this embodiment.

The M-sequence generation circuit 3 is reset every m bits. The parity counting circuit is reset every 2 m bits, and the parity counting is performed every 2 m bits.

The parity counting circuit reset timing is synchronized with the M-sequence generating circuit reset timing, and is simultaneously generated once every two M-sequence generating circuit reset timings. In other words, the parity counting period is 2 m bits and the scrambling reset period is m bits, and scrambling is reset twice in one parity counting period.

Now consider the change in parity before and after scrambling. It can be seen from the scramble characteristic that the output of the M-sequence generator circuit is exclusively ORed with the information signal, the information signal is inverted when the output of the M-sequence generator circuit is "1" and the parity changes.

Assuming that the number of “1” s in one scramble cycle of the output of the M sequence generation circuit is n, in one parity counting section,
Since there are two scramble cycles in the section, the number of "1" s in the output of the M-sequence generation circuit is 2n. That is,
The number of information bits inverted in one parity counting section is 2n, that is, an even number of bits are inverted. This means that there is no change in parity before and after scrambling.

From the above, it is understood that if only the transmission path code error is monitored, the parity bit of the information bit may be counted without performing the descramble and the parity bit may be compared with the parity bit.

Therefore, when performing error monitoring in a repeater,
The descramble circuit is not necessary, and the transmission line code error can be monitored by counting the parity of the input information signal and comparing it with the parity bit.

In this embodiment, the number of scramble resets in one parity counting section is set to two, but the same effect can be obtained if it is an even number.

(Effects of the Invention) As described above, according to the present invention, the descramble circuit is not needed when the transmission line code error is monitored in the repeater, and the size and cost of the device can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a transmission line code error monitoring system according to the present invention, and FIG. 2 is a timing chart showing an M sequence generation circuit reset timing and a parity counting circuit reset timing of the embodiment. 1 ... Signal input terminal 2 ... Parity counting circuit 3 ... M sequence generation circuit 4 ... Reset timing generation circuit 5 ... Exclusive OR circuit 6 ... Parity bit addition circuit 7 ... Signal output terminal

Claims (1)

(57) [Claims] 1. When transmitting a digital signal using a transmission line, the transmitting side divides the information bits by a certain number of bits, adds a monitoring bit to these information bits, and sends them to the transmission line. On the receiving side, the received information bit and the monitoring bit are compared to detect a code error in the transmission line.In the transmission line code error monitoring system of the parity bit system, the transmission side performs parity counting and then scrambling. After the scrambling, parity is added, and the reset synchronization of the M-sequence generating circuit of the scramble circuit is synchronized with the error monitoring period cycle, and the M-sequence generating circuit is reset even number of times during one error monitoring period. The reset cycle is selected so that the repeater repeats the information bit pattern without descrambling the received signal. Performs Tay count, and compares the count result and the monitoring bit channel coding error monitoring system and performing error monitoring.