JPS6058740A - Self-synchronism type scrambler - Google Patents

Abstract

PURPOSE:To prevent pulse generation stop of a PN generator for scrambling even if an input pulse signal is a state of consecutive same code by feeding back an output of a shift register to a prescribed shift register unit when all outputs of the said shift register are logical ''1'' or at the state of ''1''. CONSTITUTION:An output of a shift register unit 2-5 of the final stage of a feedback type shift register (PN generator) 10 is fed back to an input terminal 4 via the 1st adder 3 and through the 2nd adder 5. Through the constitution above, a video signal subject to PCM coding inputted to an input terminal 6 is inputted to the 3rd adder 5, scrambled by an M series generated from the PN generator 10 and outputted from an output terminal 7. In the process of the scramble, when all outputs of terminals Q of the shift register units 2-1-2-5 of the PN generator 10 are logical ''0'', the outputs of all terminals Q are logical ''1''. The logical ''1'' signal resets the shift register unit 2-1 via an AND gate 9 to bring the Q output to the logical ''1''. Thus, it is prevented that the PN generator 10 is stopped with all ''0''.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a self-synchronous scrambler in which all contents of shift registers of a linear register circuit are 101 or 111.
The present invention relates to a self-synchronized scrambler that prevents the scrambler from stopping generating pulses, which occurs when there is no change in the state of an input pulse signal.

(b) Prior Art and Problems In a PCM transmission system, it is known that scrambling a transmission code string is effective for retaining timing information and suppressing relay system jitter. There are two types of circuit scramblers that perform this scrambling 4: a reset type scrambler and a self-synchronous type scrambler. In principle, both formats are M-sequence eM (Maximal Period
d 5equence (abbreviation for maximum periodic sequence, a type of pseudo-random code sequence) and the original pulse sequence e to be transmitted
, one exclusive OR (OR) operation is performed between them.

The reset type scrambler performs a linear feedback type shift register (hereinafter referred to as feedback type shift register) at a determined timing to obtain the original input pulse signal.It is necessary to perform frame synchronization in transmission and reception that takes this timing, so the circuit The scale becomes larger.

Next, one embodiment of a conventional self-synchronous scrambler will be described with reference to the drawings. FIG. 1 shows an example of the configuration of a conventional self-synchronous scrambler. In the figure, 1 is a feedback shift register, 2-1 to 2-5 are shift register units, 3 is a first adder, 4 is an input terminal, 5 is a second adder, 6 is an input terminal, and 7 is an output Indicates terminal.

FIG. 2 shows a conventional video signal and its scrambled signal. In the figure, the horizontal axis shows time and the vertical axis shows level.

In FIG. 2, (a) is an analog video signal.

(a)-1 is a horizontal synchronization signal, (a)-2 is a video signal,
(b) is a PCM encoded analog video signal (a), (b) -1 in the figure is a horizontal synchronization signal section, (C) is an enlarged waveform of (b) 1, -4, In the figure, TH indicates the threshold range.

In FIG. 1, shift registers 2-1 to 2-5 and a first
Feedback shift register 1 (hereinafter referred to as P) consisting of an adder and p
The input pulse signal inputted from the input terminal 6 is inputted via the second adder 5 to the input terminal 4 of the N generator.
An exclusive OR operation is performed between the sequence eM and the input pulse train to scramble the input pulse signal and send it out the output terminal 7. In this case, if the same code string continues in the human pulse signal, the PN generator stops generating pulses.

The above self-synchronous type does not require synchronization and has a simple multi-circuit configuration, but since the state of the PN generator changes depending on the state of the input pulse signal, all 111 PN generators may be used depending on the state of the input pulse signal. 3- It may stop at full wOa.

In addition, signals that have the same level for a certain period, such as the horizontal and vertical synchronizing signals of the video signal shown in Figure 2 (IL), can be
If the video signal is encoded as a CM and transmitted, and then scrambled and transmitted using a self-synchronized scrambler, the same code continues in the horizontal synchronization signal section shown in Figure 2 (b)-1, so this section The PN generator pulse stops at
However, the scrambled horizontal synchronizing signal as shown in FIG. 2(e) is differentiated by the capacitance component of the DC-blocking transmission line. , the input pulse signal as shown in FIG. 2(d)-1 has a differential waveform of the envelope.This waveform generates an error code, and the error in the scrambled input pulse signal falls within the threshold range TH. There are many periods where bursts occur.

As a result, errors are superimposed on the TV screen, causing defects such as screen flickering. It is an object of the present invention to provide a self-synchronized scrambler in which a scrambling PN generator does not stop generating pulses even when codes are continuous.

(d) Structure of the Invention In order to achieve the above-mentioned object, the present invention provides a self-synchronous scrambling system in which an adder is fed back to the input, and the input pulse signal is output to the transmission line via the second adder. , all outputs of the shift register are 10
1 or 111, by feeding back the output of the shift register to a predetermined shift register unit.
The present invention is characterized in that means for writing 111 or 101 into the shift register is provided.

(2) In the above, all outputs of the shift register are M
It is characterized by writing several bits of 111 or 101 into the shift register when in the o2ma or 11m state.

(e) Embodiment of the Invention An embodiment of the self-synchronous scrambler of the present invention will be described below with reference to the drawings. FIG. 3 shows a configuration diagram of an embodiment of the self-synchronous scrambler of the present invention.

In FIG. 3, the same numbers and symbols as in FIG. 1 indicate the same members.

In Figure 3, 8 and 9 are AND gates, 1
0 is input to the feedback type shift register (hereinafter PN oscillation protection register unit 2-1). It is fed back to the PN generator input terminal 4, and the outputs of the Q terminals of each shift register unit 2-1 to 2-5 are AND ( The output from the Q terminal of each shift register unit 2-1 to 2-5 is inputted to the R (reset) terminal of the shift register unit 2-1 via an AND gate 8, and the output from the Q terminal of each shift register unit 2-1 to 2-5 is input to the shift register via an AND gate 9. It is input to the S (set) terminal of unit 2-1.

In the circuit configuration as described above, the PCM encoded video signal as shown in FIG. 2(b) input to the input terminal 6 is input to the second adder 5, and is converted into The scrambled video signal is outputted from the output terminal 7 into a video signal band as shown in FIG.

In the above scrambling process, the synchronizing signal (b)-1
At the timing of , the Q output of each shift register unit 2-1 to 2-5 of the PN generator 10 is set to 101, and the Q output of 7-1 is set to 101, and the PN generator 10 is stopped at all 111 as described above. prevent.

FIG. 5 shows a block diagram of another embodiment of the present invention.

The figure shows the output of the AND gate 8 of the embodiment of FIG. 3 being transferred to a plurality of shift register units 2-1, 2-2.
2-4, and the output of the AND gate 9 is fed back to the S (set) terminal of the shift register unit.
Even if the N generator 110 inputs are all 111 or all 101, the outputs of AND gates 8 and 9 will
A corresponding predetermined shift register unit is set or reset to prevent the PN generator 11 from being stopped.

8- I can do it.

[Brief explanation of drawings]

',',+:l"Figure 1 shows the conventional self-synchronized Hekura-Kura, Figure 2@3 shows the embodiment of the present invention, Figure 4 shows the scramble signal of the present invention, and Figure 5 shows the present invention. In the figure, 1 is a PN generator, 2-1 to 2-5 are shift register units, 3 is an edict 1 adder, 4.6 is an input terminal, 5 is a second adder, 7 is the output terminal, 8.9 is AND (AND)
10.11 shows the PN generator.

Claims (2)

[Claims] (1) The output of the linear register circuit consisting of a shift register consisting of a plurality of shift register units and a first adder is fed back to the input via the first adder, the second adder, and the input pulse signal is In self-synchronous scrambling, which is output to the transmission line via the second adder, when all the outputs of the shift register are in the state of 101 or 11'', the output of the shift register is sent to a predetermined shift register unit. 11 to the shift register by feeding back
A self-synchronizing scrambler characterized in that it is provided with means for writing 1 or 101. (2) In the above, all outputs of the shift register are 80
2. The self-synchronous scrambler according to claim 1, wherein when the state is 1 or 111, several bits of IIM or 101 are written to the shift register.