JPH0211351U - - Google Patents
Info
- Publication number
- JPH0211351U JPH0211351U JP1988089697U JP8969788U JPH0211351U JP H0211351 U JPH0211351 U JP H0211351U JP 1988089697 U JP1988089697 U JP 1988089697U JP 8969788 U JP8969788 U JP 8969788U JP H0211351 U JPH0211351 U JP H0211351U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- semiconductor device
- resin
- space
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 11
- 230000017525 heat dissipation Effects 0.000 claims 1
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 238000007789 sealing Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Description
第１図は本考案の樹脂封止型半導体装置の樹脂
封止を透視した平面図、第２図は第１図のＡ−Ａ
断面図、第３図は従来の樹脂封止型半導体装置の
樹脂封止を透視した平面図、第４図は第３図Ｂ−
Ｂ断面図である。
１……半導体素子、２……外部接続用電極、３
……ボンデイングワイヤ、４……インナーリード
、５……リードフレーム、６……放熱板、７……
封止樹脂。
FIG. 1 is a plan view of the resin-sealed semiconductor device of the present invention seen through the resin sealing, and FIG. 2 is the A-A of FIG. 1.
A sectional view, FIG. 3 is a plan view of a conventional resin-sealed semiconductor device as seen through the resin molding, and FIG. 4 is a diagram of FIG. 3B-
It is a sectional view of B. 1...Semiconductor element, 2...External connection electrode, 3
... bonding wire, 4 ... inner lead, 5 ... lead frame, 6 ... heat sink, 7 ...
Sealing resin.
Claims (1)
載する中央部分に空所を設け、前記空所に半導体
素子が配置され、この半導体素子の外部接続用電
極とインナーリードとの間をボンデイングワイヤ
で接続して、前記半導体素子を前記リードフレー
ムに保持する樹脂封止型半導体装置に於いて、前
記半導体素子裏面に固着される放熱板を備えるこ
とを特徴とする樹脂封止型半導体装置。 A space is provided in the central part of a lead frame for a semiconductor device on which a semiconductor element is mounted, the semiconductor element is placed in the space, and an external connection electrode of this semiconductor element and an inner lead are connected with a bonding wire. . A resin-sealed semiconductor device in which the semiconductor element is held on the lead frame, the resin-sealed semiconductor device comprising a heat dissipation plate fixed to the back surface of the semiconductor element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988089697U JPH0211351U (en) | 1988-07-05 | 1988-07-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988089697U JPH0211351U (en) | 1988-07-05 | 1988-07-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0211351U true JPH0211351U (en) | 1990-01-24 |
Family
ID=31314242
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988089697U Pending JPH0211351U (en) | 1988-07-05 | 1988-07-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0211351U (en) |
-
1988
- 1988-07-05 JP JP1988089697U patent/JPH0211351U/ja active Pending