JPH02105426A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a gallium arsenide Schottky barrier junction gate type field-effect transistor whose parasitic resistance is extremely low and whose manufacturing process can be simplified by a method wherein a source electrode and a gate electrode are formed close to a gate electrode in a self-aligned manner and are made to be ohmic electrodes. CONSTITUTION:A high-melting-point silicide layer 2 forming a Schottky junction to an n-type GaAs active layer 5 is formed on a semiinsulating GaAs substrate 1 where the active layer 5 has been formed; ions of Si<+> are implanted; conductive regions 6a, 6b are formed. After that, this assembly is covered with a silicon nitride film; after a heat treatment, the silicon nitride film is removed. Then, a silicon oxide film is formed; after that, an anisotropic etching operation is executed; a silicon oxide side wall 8 is formed at the silicide layer 2. Then, n-type GaAs layers 17a, 17b whose carrier concentration is 1.0X10<19>cm<-3> or higher are epitaxially grown selectively only on the n-type GaAs active layers 6a, 6b. Then, an aluminum metal layer is grown only on the GaAs epitaxial layers 17a, 17b; an ohmic source electrode 13 and an ohmic drain electrode 14 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a potassium diode shot 1 to key barrier junction gate type field effect transistor.

[Prior art] Gallium arsenide Schottky junction gate field effect transistor (hereinafter referred to as GaAs, MES and E-r)
GaAs integrated circuits using GaAs as a basic element can operate at higher speeds than silicon integrated circuits, and are currently being actively developed. In particular, when a normally-off type GaAs MESFET is used as a driving element,
It also has the advantage of requiring less power consumption, which is advantageous for large-scale integrated circuits. Normally-off type GaAs
In order to improve the performance of MESFET, it is important to suppress the influence of the surface depletion layer between the drain electrode and the source and drain electrodes, and to reduce the source resistance and the train resistance.

As a conventional method for manufacturing GaAs MESFETs, for example, there is a method disclosed in Japanese Patent Application No. 123775/1983, in which the manufacturing steps are shown in FIGS. 2(a) to 2([).

In this method, first, as shown in FIG. 2(a), a semi-insulating (3aAs) substrate 1 with a carrier temperature
As shown in FIG. 2(b), a
forming a Schottky junction with the r) type GaAS operating layer 5;
- A layer 2 of high melting point metal silylide (for example, tungsten silicide) is formed.

Next, as shown in FIG. 2(C), ions of Sl are implanted using the wrinkled side layer 2 of high melting point metal as a mask, covered with a silicon nitride film, heat treated and activated, and then the silicon nitride film is removed. Then, conductive regions 6a and 6b with carriers slightly higher than the n-type GaAS operating layer 5 are formed.This conductive region 6a.

The reason why the carrier concentration of 6b is not made too high is to suppress the short channel P channel effect.

Next, as shown in FIG. 2(d), after forming a silicon oxide film, the silicon oxide film is anisotropically etched by reactive ion etching, and silicon oxide is etched only on the side surfaces of the silicide layer 2 of high melting point metal. The side wall 8 is formed by leaving the film behind.

Next, as shown in FIG. 2(e), high concentration r) type GaAS layers 7a and 7b are selectively epitaxially grown only on the ``) type GaAS operating layers 5a and 5b using, for example, MOCVD.

Next, as shown in Fig. 2 [f], ohmic conductivity (
AuGe/N is formed by vacuum-depositing a gold-germanium alloy and nickel (hereinafter referred to as AuGe/N1) as a dual-purpose metal film, followed by patterning and heat treatment.
The source electrode 3 and the drain electrode (~4) of ohmic electrodes are formed on the S layers 7a and 7b by alloying the high concentration n-type Ga.

[Problem to be Solved by the Invention 1] However, in the above conventional method, AuGe/Ni
It requires multiple steps such as vacuum evaporation on the other side, patterning, and heat treatment. Since this method requires a mask margin during patterning, a large distance is left between the source and train electrodes and the gate electrode, which increases the extraneous resistance between them.If the extraneous resistance is large, the FET The characteristics deteriorate, and the variations in characteristics due to variations in spacing and variations in resistance to striking become more noticeable.

Therefore, in the conventional method described above, in order to reduce this extraneous resistance and to keep the contact resistance sufficiently low after alloying by heat treatment, high concentration n-type G is used in the source and drain regions.
An aAs epitaxial layer is provided.

However, for heat treatment of vapor-deposited metal provided thereon, for example, 5. Even if a high concentration layer of OX 1018 cm-3 or more is used, the growth layer must be at least 2000 to 3000 Å thick, and the thicker the growth, the longer the growth time and the worse the throughput. In addition, if it is necessary to provide a multilayer structure on the FET in a later process, for example, a T
When forming a ΔU type electrode, a thick growth layer becomes an obstacle.

It is an object of the present invention to provide a gallium oxide semiconductor with extremely low parasitic resistance and to simplify the manufacturing process of source and drain electrodes.
~Rancista's'! The objective is to provide an A-building method.

[Means for Solving the Problems] The present invention provides an n
A step of providing a Schottky barrier junction gate made of a refractory metal or a refractory metal compound at a predetermined location on the surface of the gallium arsenide active layer, and forming a side wall portion made of an insulator on the side surface of the Schottky barrier junction gate. process and
1 only on the exposed n-type gallium arsenide working layer.
A step of selectively epitaxially growing a high concentration n-type gallium arsenide layer of x 1019 cm-3 or more, and a step of selectively growing an aluminum metal layer or an aluminum metal compound layer only on the high concentration ")" type epitaxial layer. A method for manufacturing a semiconductor device, comprising:

[Function] The method for manufacturing a gallium arsenide Schottky barrier junction gate field effect transistor according to the present invention selectively grows an aluminum metal layer or an aluminum metal compound layer only on a high concentration n-type gallium arsenide epitaxial diagram, and and a train electrode are formed in self-alignment close to the gate electrode. Therefore, the parasitic resistance between the two becomes extremely low.

Further, by setting the carrier temperature of the high-opening [)-type gallium arsenide epitaxial layer to l x 1019 cm' or more, the aluminum metal layer or the aluminum metal compound layer becomes a non-alloy ohmic electrode. Therefore, the manufacturing process is simplified, and the thickness of the highly doped n-type epitaxial layer is sufficient to be several hundred angstroms or less, and the throughput is improved.

[Example] Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) to 1([) are schematic cross-sectional views of a semiconductor device showing an embodiment of the present invention in the order of steps.

First, as shown in FIG. 1(a), a carrier temperature of 1 x 1017 cm-3, for example, is placed on a semi-insulating GaAS substrate 1.
As shown in FIG. 1(b), on a substrate on which an n-type GaAS operation layer 5 with a thickness of 0.1 mm is formed, a layer with a thickness of, for example, Sa 50
A layer 2 of a refractory metal silylite (for example, tungsten silicide) of 0.00000000000 is formed.

Next, as shown in FIG. 1(C), using the high-melting point metal silicide layer 2 as a mask, ions of 81 were implanted into the n1 GaAs operating layer 5 at an initial energy of 50 keV and 6.0 x 1012 cm-2. Conductive regions 5a and 6b having a slightly higher concentration of Q and R are formed. After that, it was covered with a silicon nitride film and heat treated at 800°C for 115 minutes.
Conductive region 6a, which is an ion-implanted layer.

6b is activated and the silicon nitride film is removed and covered. The reason why the conductive regions tt6a and tt6b are not made to have a very high chirelia degree is to suppress the short channel effect.

Next, as shown in FIG. 1(d), for example, the thickness is 3500 mm.
After forming the silicon oxide film, the silicon oxide film 8 is etched anisotropically using CF4 residue or active ion etching, leaving the silicon oxide film only on the sides of the high-melting point metal 91941~layer 2, and forming the sidewall 8. form.

Next, as shown in FIG. 1(e), only on the n-type GaAS operating layers 6a and 6b, for example, carrier air
1019cm-3, thickness 200A high concentration “) type Ga△
5ll17a and 17b are selectively grown epitaxially. As a method for forming this epitaxial growth layer, for example, an MOCVD method using trimethylpotassium (TMG), arsine (ASH3), and hydrogen selenide (H2Se) as raw materials can be used.

Next, as shown in FIG. 1(f), a high concentration ") type GaA
An aluminum metal layer with a thickness of 500 nm is selectively grown only on the S epitaxial layers 1i 17a and 17b to form an ohmic source electrode 13 and drain electrode 14. As a method for forming this ohmic electrode layer, for example, triisobutylaluminium (-[IBA) or diethylaluminum chloride (DE/'l Cj
) can be used as a raw material scrap.

In the above embodiment, the MOCVD method was used as a method for forming the high orange n-type GaAS layer, but selective epitaxial growth and high concentration 1-bing of 1.0×1019 cm−3 or more were also used. Any possible method may be used, such as hydride vapor phase growth.

Furthermore, if atomic layer epitaxial growth is applied, thin films can be grown uniformly and with good reproducibility, resulting in high reliability.

Further, the high melting point metal layer 2 and the high concentration n-type layer 17a.

Although silicon oxide is used as a material for providing a space between 17b and the ohmic electrodes 13 and 14, any insulating material that can form side walls may be used, for example, silicon nitride may be used.

Further, although tungsten is used as the high melting point metal, other high melting point metals or compounds thereof may also be used.

[Effects of the Invention] As explained above, according to the present invention, the source and drain electrodes can be formed in the vicinity of the gate electrode in a self-aligned manner. Or, since the aluminum metal compound layer is non-alloyed and becomes an ohmic electrode, the process can be simplified. A method for manufacturing a wall junction type L-type field effect transistor is improved.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view of a semiconductor device showing an embodiment of the present invention in the order of steps, and FIG. be. 1... Semi-insulating GaAs substrate 2... High melting point total bending silicon 1-noid layer 3... Source electrode 4... Train electrode 5... GaAS operating layer 6a, 5b... Conductive region 7a, 7b, 17a, 17b -...1
3... Source Aβ electrode 14... Drain Af! electrode

Claims (1)

[Claims] (1) A step of providing a Schottky barrier junction gate made of a refractory metal or a refractory metal compound at a predetermined location on the surface of an n-type gallium arsenide operating layer provided on a semi-insulating gallium arsenide substrate, and the Schottky barrier A step of forming a side wall portion made of an insulator on the side surface of the junction gate, and a step of forming a side wall portion made of an insulator on the side surface of the junction gate, and forming a 1×10
A process of selectively epitaxially growing a high concentration n-type gallium arsenide layer of ^1^9cm^-^3 or more, and selectively growing an aluminum metal layer or an aluminum metal compound layer only on the high concentration n-type epitaxial layer. A method of manufacturing a semiconductor device, comprising the steps of: