JPH0193174A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the width of a junction and attain an increase in the effective photovoltaic region by a method wherein a first electrode is connected to an adjoining second electrode by a scribe section provided by removing a linear section from an amorphous semiconductor layer by using a high energy beam. CONSTITUTION:On an insulating substrate 14, first electrodes 18 are formed, each composed of a main section 10 and an extension 17. Then an amorphous semiconductor layer 20 is attached to them. A high energy beam is thrown upon an extension 17 for a partial removal of the semiconductor layer 20 for the formation of a scribe section 22. Second electrodes 26 are then formed on them, to be electrically connected by the scribe section 22 in the extension 17 overlapping an extension 25. Finally, a protecting film 28 is provided for the completion of a semiconductor device 10 of this design. With a scribe section being formed through application of a narrow high-energy beam, the area that electrodes require for their connection is quite small and other regions may be used for power generation. This design greatly enlarges the area to serve as an effective photovoltaic region.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to integration technology.

[Conventional technology]

In order to obtain the necessary voltage in a semiconductor device such as a solar cell, a plurality of power generation regions are connected in series on an insulating substrate, in which a first electrode, an amorphous semiconductor layer, and a second electrode facing the first electrode are laminated. It is organized by being integrated into. In such a semiconductor device, when the performance of the semiconductor is the same, in order to increase the output efficiency, that is, the output per unit area, it is necessary to increase the effective power generation area, in other words, to decrease the integrated area. Conventionally, the following two methods have been put into practical use as methods for manufacturing semiconductor devices by reducing the integrated area.

One method is to form a plurality of first electrodes 2 on an insulating substrate l, and then to cover the first electrodes 2, as shown in FIGS. 20(a) and 20(b). A semiconductor layer 3 is formed. Next, the amorphous semiconductor layer 3 is removed in stripes using a laser beam to expose the first electrode 2, and then the second electrode 4 is removed from the amorphous semiconductor layer 3.
By cutting the second electrode 4 with a laser beam, the first electrode 4 in a certain power generation area
A semiconductor device 5 is manufactured in which the electrode 2 of the first electrode 2 and the second electrode 4 of the adjacent power generation region are connected in series.

Another method is to form a plurality of first electrodes 2 having extensions 6 on an insulating substrate 1, and then cover the extensions 6 with a mask, as shown in FIGS. 21(a) and 21(b). An amorphous semiconductor Jl! is coated on the first electrode 2 excluding the extension portion 6.
! 3 is formed. Next, a second electrode 4 having an extension part 7 is formed on the amorphous semiconductor layer 3 so as to face the first electrode 2, and is adjacent to the first electrode 2 in a certain power generation fiJl region. A semiconductor device 8 is manufactured in which the second electrode 4 of the power generation region is connected in series by the respective extensions 6.7.

Note that the reference numeral 9 in the figure is a protective film.

(Problems to be Solved by the Invention) The first method shown in FIG. 20 uses a laser beam to cut the amorphous semiconductor N3 and the second electrode 4 into strips, so the laser processing takes time. Not only is this necessary, but there is also the problem of significant thermal effects, such as deterioration of the amorphous semiconductor due to the heat of the laser beam. Moreover, the power generation area is concentrated at the first electrode 2. Since the positions of the amorphous semiconductor layer 3 and the second electrode 4 are slightly shifted from each other, the width of the integrated portion becomes wide, resulting in a problem that the area of the integrated portion becomes large.

In addition, in the second method shown in FIG. 21, when depositing the amorphous semiconductor 11113 on the first electrode 2, the extension part 6 of the first electrode 2, which becomes the integrated part, is covered with a mask. Since the mask is to be exposed, a certain width is required to attach the mask to the end of the substrate 1 including the extension portion 6, and there is a limit to the reduction in the area of the integrated portion. Furthermore, due to the presence of the mask, there were problems such as poor deposition of the amorphous semiconductor and generation of pores in the layer near the boundary between the first electrode 2 and the mask.

[Means for solving problems]

The present invention has been made to solve these problems, and the gist of the method for manufacturing a semiconductor device according to the present invention is to form a plurality of first electrodes on an insulating substrate and to After depositing the amorphous semiconductor on the plurality of first electrodes, a portion of the amorphous semiconductor layer formed on one of the adjacent first electrodes is exposed to a high-energy beam. , and then from the part where the amorphous semiconductor layer was removed, a second electrode is applied over the amorphous semiconductor layer deposited on the other first electrode.
The reason is that a plurality of electrodes are formed.

[For production]

According to the present invention, a plurality of power generation regions constituted by the first electrode, the amorphous semiconductor layer, and the second electrode are formed on the insulating substrate, and the first electrode of a certain power generation region among the power generation regions is formed on the insulating substrate. The second electrodes of adjacent power generation regions are electrically connected at a portion where the amorphous semiconductor layer is removed by the high-energy beam, and the plurality of power generation regions are integrated in series.

〔Example〕

Next, embodiments of the present invention will be described in detail based on the drawings. In addition, each part of the drawing is shown enlarged as appropriate for explanation.

FIG. 1 is a front view showing an embodiment of a semiconductor device manufactured by the method of the present invention.
0 is a large one in which four power generation areas 12 are integrated. This semiconductor device 10 is manufactured as follows.

In FIG. 2, reference numeral 14 denotes an insulating substrate, and on the insulating substrate 14, a first electrode 18 having an electrode main body portion 16 and extension portions 17 extending on both sides thereof is formed by photolithography. by the law or screen printing method, etc.
A plurality of them are formed in a predetermined pattern.

Here, the insulating substrate 14 includes any substrate that is generally used in semiconductor devices such as solar cells, such as glass, polymer film, ceramics, or metal foil with an electrically insulating coating formed thereon.

Further, the first electrode 18 is made of, for example, ITO, 5nOz+
Transparent electrodes such as ITO/Snow, etc. , stainless steel, Mo.

It includes metal electrodes such as Pt+Au, Ag+Nt+Cu, and alloys thereof, and any other electrodes that are generally used in semiconductor devices such as solar cells.If the insulating substrate 14 is a transparent substrate such as glass, the first A transparent electrode such as 5nO1 is used as the electrode 18.

As shown in FIGS. 3(a) and 3(b), an amorphous semiconductor N20 is formed on the insulating substrate 14 on which the first electrode 18 is formed, except for the current extraction portion 19 of the first electrode 18. be coated. The amorphous semiconductor layer 20 is made of, for example, an amorphous semiconductor such as amorphous silicon a-5i + hydrogen hydrogen more amorphous silicon a, Si:IL water hydrogenated 7 rulphous silicon carbide a3iC:II, amorphous silicon nitride, pin type + 9
It is deposited in n-type, Mis-type, heterojunction type, homojunction type, Schottky barrier type, or a combination of these types, and can be deposited using ion blating method, vacuum evaporation method, plasma CvUI method, sputtering method, etc. It is formed by

The first electrode 18, on which the amorphous semiconductor M20 is deposited in this way, emits a high-energy beam onto its extended portion 17 almost parallel to the direction in which the power generation regions 12 are integrated, as shown in FIG. 3(a). The amorphous semiconductor layer 20 is removed in a linear manner by irradiating the same.

High energy beams are e.g. YAG laser, Cot
A beam capable of concentrating high energy is used, such as a laser beam such as a laser, an electron beam, or an ion beam.

The scribe portion 22 of the extension portion 17 where the amorphous semi-molar body layer 20 is removed in a linear manner with a high energy beam is the fourth
Although it may reach the insulating substrate 14 as shown in FIG. 4(a), it is sufficient that at least the extension portion 17 of the first electrode 18 is exposed as shown in FIG. 4(b).

Next, Figures 1 and 5 (a), (b), (c)
As shown in FIG. 2, a second electrode 26 having an electrode body portion 24 and extension portions 25 extending to both ends thereof is formed in a predetermined pattern on the amorphous semiconductor Ji 20 by a vapor deposition method, a photolithography method, or the like. The electrode body part 24 of the second electrode 26 is disposed to face the electrode body part 16 of the first electrode 18, and the extension part 25 of the second electrode 26 is connected to the adjacent electrode 18. It is arranged so as to straddle the extension part I7 extending from the both extension parts 17.25.
As shown in FIGS. 5(a) and 5(b), they are electrically connected at the scribe portion 22 where the amorphous semiconductor N20 is removed by a high-energy beam. Therefore, the electrode body portion 16/amorphous semiconductor layer 20 of the first electrode 18
/The power generation Mk/i 12 constituted by the electrode body 24 of the second electrode 26 is integrated by the extension 17.25. Here, the second electrode 26 is the first electrode 18
However, if the insulating substrate 14 is a transparent substrate such as glass and the first electrode 18 is a transparent electrode such as Snug, the second electrode 26 is a metal electrode such as AI. used.

As shown in FIG. 5(a), the second electrode 26 is further coated with a protective film 2 to manufacture the semiconductor device 1O.

According to this implementation method, the extension part that becomes the aggregate 111 part can be formed without using a mask or the like, so problems such as poor deposition or pores do not occur at the end of the amorphous semiconductor layer, and the extension part Since the width of the part is sufficient as long as the amorphous semiconductor layer can be removed by a high-energy beam, it is possible to significantly reduce the area of the integrated part. More specifically, the width of the scribe portion is approximately 0.02 to 0.3
Since it is about am, the width of the accumulation part can be made 0.5 m+s or less. In conventional manufacturing methods, the area ratio of the effective power generation area to the area of the semiconductor device, that is, the area ratio of the effective power generation area, was only 60 to 80%, but according to the method of the present invention, the area ratio is 80% or more. become.

Although one embodiment of the present invention has been described above in detail, the method of the present invention is not limited to the above-mentioned embodiment.

For example, as shown in FIG. 6, in the scribe portion 22 where the amorphous semiconductor layer 20 on the extension portion 17 of the first electrode 18 is removed in lines with a high-energy beam,
A metal 30 made of a good electrical conductor may be deposited on the scribe portion 22 where the extension portion 25 of the second electrode 26 is not provided, or a material different from that of the second electrode 26 may be used for the metal 30. It is also possible to form it integrally with the second electrode 26. According to this example, the scribing section 22
The connection resistance between the first electrode 18 and the second electrode 26 can be reduced.

Further, as shown in FIGS. 7 to 8, Cr, Ni, Ti
After depositing a thin film 32 made of a good electrical conductor such as by vapor deposition method, etc., the amorphous semiconductor 11 is deposited in the same manner as described above.
The step of depositing the ff120, the step of removing the amorphous semiconductor layer 20 using a high-energy beam, and the step of forming the second electrode 26 may be performed. In this way, the current generated in the power generation region 12 not only flows through the first electrode 18 and is directly led out to the extension part 17 which is the accumulation part, but also flows from the first electrode 18 to the electrically good conductor. According to this example, the output loss that occurs when the generated current flows through the first electrode 18 made of SnO, etc., which has a high resistance, is It can be reduced by directing the current to the thin film 32, and is effective when applied to solar power generation devices and other semiconductor devices that generate large currents.

As described above, in the embodiment of the method of the present invention, the extension parts 17.25 forming the accumulation part were provided at both ends of the power generation area 12.
It may be provided only at one end, and can be selected depending on the amount of power generated by the semiconductor device.

In addition, as shown in FIGS. 9 and 10, the method of the present invention includes connecting the extension portion 34 of the first electrode 18 to the adjacent first electrode 1.
The scribe portion 22 is formed so that it does not extend toward the 8th side, and is formed by a high-energy beam on the extended portion 34 of the scribe portion 22.
It is also possible to form the extension 36 of the second electrode 26 such that the first electrode 18 and the second electrode 26 are electrically connected at.

Further, as shown in FIG. 11, the first electrode 38 is not provided with an extension part, and a second
The extension portion 25 of the electrode 26 may be connected to span the first electrode 38.

Furthermore, as shown in FIGS. 12 to 13, the extension part 42 of the first electrode 40 is arranged in the notch part 44 of the other adjacent first electrode 40, so that the amorphous semiconductor can be removed by the high-energy beam. After forming the scribe portion 22 of the layer 20 on the extension portion 42 in a direction perpendicular to the stacking direction, a second electrode 46 having no extension portion is disposed opposite to the first 11 poles 40, and the scribe portion 22 is formed on the extension portion 42 in a direction perpendicular to the stacking direction. The first electrode 40 and the second electrode 46 may be connected at 22.

Conversely, as shown in FIGS. 14 and 15, the electrode 48 is placed at an appropriate location on the first electrode 48 without an extension.
A high-energy beam is applied from the top of the amorphous semiconductor layer 20 deposited thereon to form a scribe portion 22 in a direction perpendicular to the integration direction, and then the extension portion 5 of the second electrode 50 is formed.
2 is disposed on the scribe portion 22 so as to straddle the side of the adjacent first electrode 48, and the first electrode 48 and the second electrode 50 are electrically connected at the scribe portion 22. It is also possible.

In any of the above examples, the area of the integrated portion of the power generation region can be further reduced.

The embodiments of the method of the present invention have been described above in detail based on the drawings, but it is also possible to provide a thin film made of a good electrical conductor at an appropriate location on the first electrode or the second electrode, etc. The method can be implemented with various modifications, improvements, and modifications based on the knowledge of those skilled in the art without departing from the spirit thereof.

Example 1 The solar cell shown in FIG. 16 was manufactured by the method shown in FIGS. 1 to 5.

External dimensions 35+++mX 15m+w as an insulating board,
A transparent substrate 54 made of glass with a thickness of 1.1 mm is used, and a layer with a thickness of 200 to 500 mm is used as a first electrode on the transparent substrate 54.
Transparent electrodes 56 made of SnO were formed at four separate locations. The transparent electrode 56 was formed by photolithography into a pattern consisting of an electrode main body portion serving as a photosensitive area and an extension portion that does not contribute to power generation.

Next, an amorphous silicon semiconductor with a thickness of 5,000 to 7,000 people is placed on the transparent electrode 56. 5B was applied. The amorphous silicon semiconductor layer 58 is composed of a pin junction formed inside thereof in parallel with the layer surface, and specifically, first a P-type amorphous silicon semiconductor layer/i-type amorphous silicon half-octane layer/ N-type amorphous silicon semiconductor layers were laminated in order by a known method.

Thereafter, the amorphous silicon semiconductor N58 on the extension of the transparent electrode 56 was removed in stripes parallel to the direction of integration using a YAG laser. The YAG laser used has a wavelength of 1.06
The conditions were μm, output 6W, and pulse frequency 25kllz. Further, the width of the scribe portion 60 from which the amorphous silicon semiconductor 1'55B was removed using the YAG laser was approximately 50 μm.

Next, aluminum AI was deposited as a second electrode (62) in a predetermined pattern on the amorphous silicon semiconductor layer 58 under a pressure of 5 x 10-'' Torr.The thickness was about 2,000. When inspecting the scribe portion 60, it has a cross section shown in FIG. 5(a) or (b),
A of the transparent electrode 56 of a certain power generation area and the adjacent power generation area!
It was connected to the electrode 62 through a scribe portion 60 . Furthermore, when the resistance value of the connection point was measured, it was less than 1Ω/C11, which was a value that caused no problem in practical use.

In this example, for comparison, the distance between the outer periphery of the effective power generation area and the substrate was set to 1 ma+, and the distance between adjacent power generation areas was set to 0.5 mm. Further, the width of the stacking portion can be formed to be 0.5 mm or less according to the method of the present invention, but in this example, it was formed to be la+n.

The area ratio of the effective power generation area of the amorphous silicon solar cell thus obtained was 78%. Further, the output of this solar cell was investigated under FL1001uxO. The results are shown in FIG. 17, with the horizontal axis representing the output voltage and the vertical axis representing the output current.

Comparative Example 1 A solar cell having the structure shown in FIG. 20 was manufactured under the same conditions as in Example 1, and the area ratio of the effective power generation area and output of the obtained solar cell were examined under the same conditions.

However, the distance between the outer periphery of the effective power generation area and the substrate is ll+1f.
fi, but the width of the accumulation part was l+uw as a result of implementing the conventional method.

As a result, the area ratio of the effective power generation area was 74.3%. Moreover, the output was as shown by a single dot in FIG. 17. Comparative Example 2 A solar cell having the structure shown in FIG. 21 was manufactured under the same conditions as in Example 1, and the area ratio of the effective power generation area and output of the obtained solar cell were examined under the same conditions.

However, the distance between the outer periphery of the effective power generation area and the substrate was set to 1 mm, and the distance between adjacent power generation areas was set to 0.5 mm.

In addition, the width of the accumulation part was 211 mm as a result of implementing the conventional method.
It was I11.

As a result, the area ratio of the effective power generation area was 72%. Moreover, the output was as shown by the two-dot chain line in FIG.

Embodiment 2 As shown in FIG. 18, a solar cell has a structure in which a thin film 64 made of chromium Cr having a width of 0.2 mm is deposited on the peripheral edge adjacent to other transparent electrodes 56, including the extended portion of the transparent electrode 56. A battery was manufactured under the same conditions as in Example 1 above.

The output of the solar cells obtained is measured using a solar simulator AM (
Air Mass) 1 (100 mW/cm"). The results are shown in FIG. 19, with the horizontal axis representing the output voltage and the vertical axis representing the output current.

Comparative Example 3 Using the same solar cell as in Comparative Example 1 described above, its output was examined under the same conditions as in Example 2.

The results are shown in FIG. 19 by a dashed line.

[Effects of the Invention] The method of the present invention has a scribe portion in which a part of the amorphous semiconductor layer is removed in lines using a high-energy beam, and a first electrode in a certain power generation region and a second electrode in an adjacent power generation region are connected to each other. Because of the connection, the width of the connection part, that is, the accumulation part, can be reduced, thereby making it possible to reduce the area of the accumulation part, or in other words, to increase the effective power generation area. Moreover, since a mask is not used when forming the amorphous semiconductor layer, not only is it possible to further reduce the area of the integrated area, but also problems such as poor deposition of the amorphous semiconductor and the formation of pores due to the influence of the mask etc. can occur. Never. Furthermore, the scribe portion is formed by an extension extending from either or both of the first electrode of a certain power generation region or the second electrode of an adjacent power generation region, and the extension does not contribute to power generation. The present invention has excellent effects, such as the fact that there is no need to consider the effects of deterioration of the amorphous semiconductor layer due to energy beam irradiation.

[Brief explanation of the drawing]

FIG. 1 is a front view showing an example of a semiconductor device manufactured by the method of the present invention. 2 to 5 are diagrams for explaining the main points of the manufacturing process of the semiconductor device shown in FIG. 1, and FIG. 2 is a front view showing a state in which a first electrode is formed on an insulating substrate; FIG. 3(a) is a front view showing the state in which the scribe portion is formed in the amorphous semiconductor layer, FIG. 3(b) is a cross-sectional view showing the state in which the amorphous semiconductor layer is formed, and FIG.
5(a) and 5(b) are cross-sectional views showing the scribe portion, respectively, FIG. 5(a) is a cross-sectional view of the semiconductor device shown in FIG. 1,
Figures (b) and (c) are sectional views of the stacking section, respectively. 6 to 15 are diagrams for explaining other embodiments of the method of the present invention, FIG. 6 is a front view showing another embodiment, and FIGS. 7 to 8 are diagrams showing still another embodiment. FIG. 7 is a front view showing a state in which a first electrode is formed on an insulating substrate, and FIG. 8 is a front view of the obtained semiconductor device. FIGS. 9 and 10 are diagrams showing still another embodiment, with FIG. 9 being a partial front view showing one step, and FIG. 10 being a partial front view of the obtained semiconductor device. FIG. 11 is a front view showing still another embodiment, FIGS. 12 to 13 and FIGS. 14 to 15 are views showing still other embodiments, and FIG. 12 shows one step. 13 is a partial front view of the obtained semiconductor device, FIG. 14 is a partial front view showing one step, and FIG. 15 is a partial front view of the obtained semiconductor device. FIG. 16 is a front view of the semiconductor device used in Example 1-, and FIG. 17 is a diagram showing the output of the semiconductor device in FLloolux. FIG. 18 is a front view of the semiconductor device used in Example 2, and FIG. 19 is a diagram showing the output of the semiconductor device in a solar simulator A M 1 of 100 mW/am. It is a figure which shows an example of an apparatus, the same figure (a) is a front view, and the same figure (b) is a side view.
The figures are diagrams showing another example of a conventional semiconductor device, in which figure (a) is a front view and figure (b) is a cross-sectional view. 10i semiconductor device 12; power generation area 14.54;
Insulating substrate ' 17.34, 42i extension (first electrode) IEI, 3B
, 40.48.5G, first electrode 20.58; amorphous semiconductor layer 22, . 60. Scribe portion 25.36, 52; extension portion (second electrode) 26.46,
50,62i Second electrode 30; Metal 32; Thin film Fig. 2 Fig. 3 (b)] 4 43 (a) (b) Fig. 5 (b) (c) Fig. 6 Fig. 7 Fig. 9 Figure 12 Figure 15 Figure 16 Figure 18! Figure 7 (V) Figure 19 (V)

Claims (3)

[Claims] (1) A method for manufacturing a semiconductor device in which a plurality of power generation regions each including a first electrode, an amorphous semiconductor layer, and a second electrode facing the first electrode are stacked on an insulating substrate, comprising: After forming a plurality of first electrodes on an insulating substrate and depositing an amorphous semiconductor on the plurality of first electrodes, on one of the adjacent first electrodes. A part of the amorphous semiconductor layer formed on the first electrode is removed using a high-energy beam, and then the amorphous semiconductor layer deposited on the other first electrode is straddled from the part where the amorphous semiconductor layer was removed. 1. A method of manufacturing a semiconductor device, characterized in that a plurality of second electrodes are formed using a plurality of second electrodes. (2) The first electrode or the second electrode has an extension portion extending to the other first electrode side or the second electrode side adjacent to either one or both, and the extension portion has a high energy Claim 1, characterized in that the amorphous semiconductor layer is removed by a beam to connect the first electrode of any power generation region to the second electrode of an adjacent power generation region. A method for manufacturing a semiconductor device. (3) After forming the first electrode, at least the peripheral edge of the first electrode on the side where a portion of the amorphous semiconductor layer is removed by the high-energy beam and adjacent to another first electrode; 3. The method of manufacturing a semiconductor device according to claim 1, wherein a thin film made of a good electrical conductor is applied to the portion of the semiconductor device.