JPS62232175A - Manufacture of photovoltaic device - Google Patents

Manufacture of photovoltaic device

Info

Publication number
JPS62232175A
JPS62232175A JP61075263A JP7526386A JPS62232175A JP S62232175 A JPS62232175 A JP S62232175A JP 61075263 A JP61075263 A JP 61075263A JP 7526386 A JP7526386 A JP 7526386A JP S62232175 A JPS62232175 A JP S62232175A
Authority
JP
Japan
Prior art keywords
electrodes
semiconductor layer
amorphous semiconductor
connection
power generation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61075263A
Other languages
Japanese (ja)
Other versions
JPH07105510B2 (en
Inventor
Noritoshi Yamaguchi
文紀 山口
Kenji Tomita
賢時 冨田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP61075263A priority Critical patent/JPH07105510B2/en
Priority to US07/032,164 priority patent/US4773943A/en
Publication of JPS62232175A publication Critical patent/JPS62232175A/en
Publication of JPH07105510B2 publication Critical patent/JPH07105510B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

Abstract

PURPOSE:To stabilize the quality of a film and to improve the quality of appearance, by forming a connecting hole part, which penetrates an amorphous semiconductor layer by the projection of laser light along the aligning direction of a plurality of first electrodes, and electrically connecting second electrodes to the neighboring first electrodes through the connecting hole part when a plurality of the second electrodes are formed on the amorphous semiconductor layer. CONSTITUTION:On a substrate 1, first electrodes 2a-2c and extended parts 21a-21c for connection are simultaneously formed. An amorphous semiconductor layer 3 is deposited so as to cover the electrodes and the extended parts completely. A connecting hole part 5, which is formed by the projection of laser light, penetrates the amorphous semiconductor layer 3. A plurality of second electrodes 4a-4c corresponding to the first electrodes 2a-2c are formed on the amorphous semiconductor layer 3. Extended parts 4la-41c for connection are electrically connected to the extended parts 21a-21b of the first electrodes for connection.

Description

【発明の詳細な説明】 〔産業上の利用分野] 本発明は太陽電池や光センサー等の非晶質半導体層を有
する光起電力装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a photovoltaic device having an amorphous semiconductor layer, such as a solar cell or a photo sensor.

〔従来の技術〕[Conventional technology]

従来の光起電力装置の平面図を第3図(g)に示す。 A plan view of a conventional photovoltaic device is shown in FIG. 3(g).

絶縁基板1上に複数個の第1電極2g〜21が形成され
ている。該複数個の第1電極2g〜21上に連続的に連
なる非晶質半導体層3が被着され、さらに第1電極2g
〜21に対応し、非晶質半導体N3上に複数個の第2電
極4g〜41が形成される。
A plurality of first electrodes 2g to 21 are formed on the insulating substrate 1. A continuous amorphous semiconductor layer 3 is deposited on the plurality of first electrodes 2g to 21, and further the first electrode 2g
21, a plurality of second electrodes 4g to 41 are formed on the amorphous semiconductor N3.

これにより絶縁基板l上に複数個の発電区域g〜iが形
成される。
As a result, a plurality of power generation areas g to i are formed on the insulating substrate l.

第1電極2g〜21を形成する際、マスク操作又はエツ
チング処理により、非晶質半導体層3外に延びる第1電
極の接続用延長部21g〜21iが形成される。また、
第2電極4g〜41を形成する際、マスクの操作により
、非晶質半導体層3外に延び、かつ隣接する発電区域g
−hの第1電極の接続用延長部21g〜21hと重畳接
続する第2電極の接続用延長部41h〜41iが形成さ
れる。なお、発電区域gの第2電極の接続用延長部41
gはそのまま非晶質半導体層3外に形成され、また発電
区域iの第1電穫の接続用延長部21i上にリード線取
り出し用出力端子部61が形成される。
When forming the first electrodes 2g to 21, connection extensions 21g to 21i of the first electrodes extending outside the amorphous semiconductor layer 3 are formed by mask operation or etching. Also,
When forming the second electrodes 4g to 41, by operating a mask, a power generation area g extending outside the amorphous semiconductor layer 3 and adjacent to the
-h second electrode connection extensions 41h to 41i are formed to overlap and connect with the first electrode connection extensions 21g to 21h. In addition, the extension part 41 for connecting the second electrode of the power generation area g
g is formed as it is outside the amorphous semiconductor layer 3, and an output terminal portion 61 for taking out a lead wire is formed on the connection extension portion 21i of the first electric power generation area i.

かくして、第1電掻の接続用延長部21g〜21hと第
2電極の接続用延長部41h〜41i とが発電区域g
”iを直列的関係になるべく夫々電気的接続が行われ、
出力は発電区域gの第2電極の接続用延長部41gとリ
ード線取り出し用出力端子部61との間で得られる。(
特公昭58−21827号公報)次に上述の光起電力装
置の製造方法を第3図(a)〜(g)の各工程における
平面図に基づいて説明する。
Thus, the connection extensions 21g to 21h of the first electrode and the connection extensions 41h to 41i of the second electrode are in the power generation area g.
``i is electrically connected to each other so as to be in a series relationship,
Output is obtained between the connection extension part 41g of the second electrode in the power generation area g and the output terminal part 61 for taking out the lead wire. (
(Japanese Patent Publication No. 58-21827) Next, a method for manufacturing the above-mentioned photovoltaic device will be explained based on plan views of each step in FIGS. 3(a) to 3(g).

絶縁基板1を洗浄、乾燥しく第3図(a) ) 、該基
板1上に第1電極形成用マスク22を覆設する(第3図
(b))。 マスク22の形状は、該発電区域g−iの
第1電Fi2g〜21及びその接続用延長部21g〜2
1iが形成される窓を有する。
The insulating substrate 1 is cleaned and dried (FIG. 3(a)), and a first electrode forming mask 22 is placed over the substrate 1 (FIG. 3(b)). The shape of the mask 22 is such that the first electricity Fi2g~21 of the power generation area g-i and its connection extension part 21g~2
1i has a window formed therein.

マスク22を介して、スプレー法、プラズマCVD法ス
パッタリング法を用いて、第1電掻2g〜21及びその
接続用延長部21g〜21i となる透明導電膜例えば
SnO□、 In、03等が被着される。 その後、該
マスク22を外す。これにより基板l上に夫々配列され
た第1電極2g〜21及びその接続用延長部21g〜2
1iが形成される(第3図(C))。
Through the mask 22, a transparent conductive film such as SnO□, In, 03, etc., which will become the first electric scrapers 2g to 21 and their connection extensions 21g to 21i, is deposited using a spray method, a plasma CVD method, or a sputtering method. be done. Thereafter, the mask 22 is removed. As a result, the first electrodes 2g to 21 and their connection extensions 21g to 2 arranged on the substrate l, respectively.
1i is formed (FIG. 3(C)).

次に非晶質半導体層形成用マスク32を基板1に装着す
る(第3図(d))。ここで形成用マスク32は該第1
1を極2g〜21に連続的に連なり、かつその接続用延
長部21g〜21iが隠蔽される形状の窓を有す。
Next, a mask 32 for forming an amorphous semiconductor layer is attached to the substrate 1 (FIG. 3(d)). Here, the forming mask 32
1 is continuously connected to the poles 2g to 21, and the connecting extensions 21g to 21i are hidden.

プラズマCVD装置に投入し、グロー放電分解で非晶質
半導体層3が被着される。非晶質半導体層3はP−1−
N接合が施されており、例えばPJliはシラン(Si
H4)、水素(Hり、 ジボラ ン(BIH,)の混合
ガスが、1層はシラン、水素の混合ガスが、NNiはシ
ラン+Ht+フォスフイン(Plh)の混合ガスが、ガ
ス圧1.2Torrで13.56MIIzの高周波電圧
が印加されることにより該マスク32を介して被着され
る。
It is put into a plasma CVD apparatus, and an amorphous semiconductor layer 3 is deposited by glow discharge decomposition. The amorphous semiconductor layer 3 is P-1-
For example, PJli is made of silane (Si
H4), hydrogen (H), diborane (BIH), one layer is a mixture of silane and hydrogen, NNi is a mixture of silane + Ht + phosphine (Plh), and the gas pressure is 1.2 Torr. The film is deposited through the mask 32 by applying a high frequency voltage of .56 MIIz.

該マスク32を外し、第1電極2g〜21上に連続的に
連なる非晶質半導体層3が形成される(第3図(e))
The mask 32 is removed, and a continuous amorphous semiconductor layer 3 is formed on the first electrodes 2g to 21 (FIG. 3(e)).
.

さらに、非晶質半導体層3上に第2電極4g〜41及び
その接続用延長部41g〜411、出力様端子61が形
成される様に所定形状の窓を有する第2電極形成用マス
ク42が装着される(第3図(f) ) 。
Further, a second electrode forming mask 42 having a window of a predetermined shape is provided on the amorphous semiconductor layer 3 so that the second electrodes 4g to 41, their connection extensions 41g to 411, and an output terminal 61 are formed. (Fig. 3(f)).

この状態でスパッタ法、抵抗加熱法、電子ビーム法を用
いて第2電14g〜41及びその接続用延長部41g〜
41i 、出力用端子部61となる金属膜が被着される
。使用される金属は、アルミニウム(AI)、ニッケル
(Ni)、クロム(Cr)、チタン(Ti)等であり、
0.4〜1μmの膜厚で被着される。
In this state, the second electrodes 14g to 41 and their connecting extension parts 41g to
41i, a metal film that will become the output terminal portion 61 is deposited. The metals used are aluminum (AI), nickel (Ni), chromium (Cr), titanium (Ti), etc.
It is deposited in a film thickness of 0.4 to 1 μm.

そして該マスク42を外し、所定形状の第2電極4g〜
41及びその接続用延長部41g〜41i 、出力用端
子61が形成される。(第3図(g))。
Then, the mask 42 is removed, and the second electrode 4g having a predetermined shape is
41, its connection extensions 41g to 41i, and an output terminal 61 are formed. (Figure 3(g)).

〔従来技術の問題点〕[Problems with conventional technology]

しかしながら、従来の光起電力装置は基板lの全表面積
の15〜20χは発電に全く寄与しない接続部であり、
基板lの面積に対する有効受光面積(非晶質半導体層3
被着部分G)は、極めて低下してしまう。
However, in conventional photovoltaic devices, 15 to 20χ of the total surface area of the substrate l is a connection part that does not contribute to power generation at all.
Effective light-receiving area relative to the area of the substrate l (amorphous semiconductor layer 3
The deposited area G) is extremely degraded.

これは非晶質半導体層3が接続部分Cに被着しない様に
マスク32が装着されるが、該非晶質半導体T43がマ
スク32と基板1との間隙に入り込む可能性があるため
、第1電掻の延長部21g〜21hと第2電極の延長部
41h〜41の重畳部分を大面積化し、接続の信頼性を
向上させていることに起因する。
This is because the mask 32 is attached so that the amorphous semiconductor layer 3 does not adhere to the connection portion C, but the amorphous semiconductor T43 may enter the gap between the mask 32 and the substrate 1. This is due to the fact that the overlapping portions of the electric scraper extensions 21g to 21h and the second electrode extensions 41h to 41 are enlarged to improve the reliability of the connection.

また、前記マスク32により、グロー放電によるプラズ
マの干渉が発生し、非晶質半導体層3の膜質を不安定に
し出力特性を低下させ、外観を悪くするという問題があ
った。
Further, the mask 32 causes plasma interference due to glow discharge, which causes the film quality of the amorphous semiconductor layer 3 to become unstable, resulting in a decrease in output characteristics and a poor appearance.

〔本発明の目的〕[Object of the present invention]

本発明は上述の問題点に鑑み、案出されたものであたり
、その目的は、基板に対する有効受光面積が増大し、か
つ、非晶質半導体層の膜質を向上させ、高い出力特性が
得られる光起電力装置の製造方法を提供することにある
The present invention was devised in view of the above-mentioned problems, and its purpose is to increase the effective light-receiving area with respect to the substrate, improve the film quality of the amorphous semiconductor layer, and obtain high output characteristics. An object of the present invention is to provide a method for manufacturing a photovoltaic device.

〔目的を達成するための具体的手段〕[Specific means to achieve the purpose]

本発明が上述の目的を達成するために行った具体的手段
は、非晶質半導体層と、該非晶質半導体層を挟む第1.
第2電極とからなる複数個の発電区域を有し、該発電区
域を絶縁基板上に配列形成した光起電力装置の製造方法
において、該絶縁基板上に複数個の第1電極を形成し、
該複数個の第1電極を覆うように非晶質半導体層を被着
した後、該非晶質半導体層を貫通する接続用開口部を第
1電極の配列方向に沿った直線上に配置されるように形
成し、次いで各発電区域の起電力が直列に出力されるよ
うに非晶質半導体層上に複数個の第2電掻を形成し、隣
接する発電区域の第1電掻を該接続用開口部を通じて電
気的に接続したことである。
The specific means taken by the present invention to achieve the above object includes an amorphous semiconductor layer and a first layer sandwiching the amorphous semiconductor layer.
In a method for manufacturing a photovoltaic device having a plurality of power generation areas consisting of a second electrode and an array of the power generation areas formed on an insulating substrate, a plurality of first electrodes are formed on the insulating substrate,
After depositing an amorphous semiconductor layer to cover the plurality of first electrodes, connection openings penetrating the amorphous semiconductor layer are arranged on a straight line along the arrangement direction of the first electrodes. Then, a plurality of second electric wires are formed on the amorphous semiconductor layer so that the electromotive force of each power generation area is output in series, and the first electric wires of adjacent power generation areas are connected. electrical connection through the opening.

〔実施例〕〔Example〕

以下、本発明の光起電力装置の製造方法を図面に基づい
て説明する。
Hereinafter, a method for manufacturing a photovoltaic device according to the present invention will be explained based on the drawings.

第1図(g)は本発明の光起電力装置の製造方法によっ
て製造された光起電力装置の平面図である。
FIG. 1(g) is a plan view of a photovoltaic device manufactured by the method for manufacturing a photovoltaic device of the present invention.

基板1上に第1電極28〜2cを配列形成されている。First electrodes 28 to 2c are arranged and formed on the substrate 1.

この時、各電極28〜2cには各発電区域a−cの側縁
部に延長する接続用延長部21a〜21cが同時に形成
される。
At this time, connecting extension parts 21a to 21c extending to the side edges of each power generation area a to c are simultaneously formed on each of the electrodes 28 to 2c.

非晶質半導体層3が前記第1電f42a〜2c及びその
接続用延長部21a〜21cを完全に覆うように被着さ
れている。
The amorphous semiconductor layer 3 is deposited to completely cover the first electrodes f42a-2c and their connection extensions 21a-21c.

5は基板1に配列した第1電掘の接続用延長部21a〜
21c上の非晶質半導体層3の一部に発電区域a−cの
配列方向に沿ってレーザー照射により形成した接続用開
口部である。接続用開口部5によって非晶質半導体層3
は貫通し、第1電極28〜2cの接続用延長部21a〜
21c及び基板1が露出する。
5 is the connection extension part 21a of the first electrical excavation arranged on the board 1.
This is a connection opening formed in a part of the amorphous semiconductor layer 3 on 21c by laser irradiation along the arrangement direction of power generation areas a-c. The amorphous semiconductor layer 3 is formed by the connection opening 5.
extends through the connection extension portions 21a to 21a of the first electrodes 28 to 2c.
21c and the substrate 1 are exposed.

接続用開口部5の巾はレーザーの出力で決定されるが、
最低20μmあれば充分である。また、接続用開口部5
はレーザー発振のQスイッチの周波数と基板lに対する
レーザー走査速度により、最低20μmの直径の小孔を
断続的に形成してもよいし、また単一の小孔を形成して
もよい。
The width of the connection opening 5 is determined by the output of the laser.
A minimum thickness of 20 μm is sufficient. In addition, the connection opening 5
Depending on the Q-switch frequency of the laser oscillation and the laser scanning speed with respect to the substrate 1, small holes with a diameter of at least 20 μm may be formed intermittently, or a single small hole may be formed.

さらに、非晶質半導体層3上に第1電m2a〜2Cに対
応する複数個の第2電極4a〜4cが形成される。
Furthermore, a plurality of second electrodes 4a to 4c corresponding to the first electrodes m2a to 2C are formed on the amorphous semiconductor layer 3.

これにより基板1上に複数個の発電区域a−Cが形成さ
れる。
As a result, a plurality of power generation areas a-C are formed on the substrate 1.

第2 ’14i4a〜4cを形成する際、同一発電区域
a〜Cの第1ri極2a〜2cのに接続せず、隣接する
発電区域a=b第1電極28〜2bにまで延長する接続
用延長部41b〜41cが形成され、該接続用延長部4
1b〜41cは接続用開口部5を通じて隣接する発電区
域a−bの第1電極の接続用延長部21a〜21bに電
気的接続される。
When forming the second 14i4a to 4c, the connection extension does not connect to the first ri poles 2a to 2c of the same power generation area a to C, but extends to the adjacent power generation area a=b first electrodes 28 to 2b. portions 41b to 41c are formed, and the connecting extension portion 4
1b to 41c are electrically connected to the connection extensions 21a to 21b of the first electrodes of the adjacent power generation areas a-b through the connection openings 5.

かくして、直列的に電気接続された各発電区域a’wc
を有する光起電力装置の出力は、発電区域aの第2電極
4aから延びた接続用延長部41aと発電区域Cの第1
電極2cの延出部21cが露出する該レーザー接続用開
口部5上に形成された出力端子部6cとの間から得られ
る。
Thus, each generating area a'wc electrically connected in series
The output of the photovoltaic device having a
It is obtained from between the output terminal portion 6c formed on the laser connection opening 5 where the extending portion 21c of the electrode 2c is exposed.

次に、本発明の光起電力装置の製造方法を第1図(a)
〜(g)の各工程における平面図に基づいて説明する。
Next, the method for manufacturing the photovoltaic device of the present invention is shown in FIG. 1(a).
Description will be made based on plan views of each step of -(g).

ガラス、セラミック、ステンレスの表面に絶縁処理した
基板1を洗浄、乾燥しく第1図(a))、該基板1に第
1電極形成用マスク22を覆設する(第1図(b))。
A substrate 1 whose surface is made of glass, ceramic, or stainless steel and has been subjected to insulation treatment is cleaned and dried (FIG. 1(a)), and a first electrode forming mask 22 is placed over the substrate 1 (FIG. 1(b)).

マスク22の形状は発電区域a−Cの第1電極2a〜2
C及びその接続用延長部21a〜21Cが形成される所
定形状の窓を有する。
The shape of the mask 22 corresponds to the first electrodes 2a to 2 in the power generation areas a-C.
C and its connection extensions 21a to 21C are formed therein.

この状態でスプレー法、プラズマCVD法、スパッタ法
等を用いて、第1電極2a〜2c及びその接続用延長部
21a〜21cとなる透明導電膜、例えば酸化錫(Sn
O□)等が被着される。この後、マスク22を外し、基
板1上に所定形状の第1電極2a〜2C及びその接続用
延長部21a〜21cが配列形成される(第1図(C)
)。
In this state, using a spray method, plasma CVD method, sputtering method, etc., a transparent conductive film, for example, tin oxide (Sn
O□) etc. are deposited. Thereafter, the mask 22 is removed, and the first electrodes 2a to 2C and their connecting extensions 21a to 21c are arranged and formed on the substrate 1 (see FIG. 1C).
).

この第1電極28〜2Cが被着した基板1をプラズマC
VD法装置に投入し、グロー放電分解により、該基板1
の全面に非晶質半導体層3を被着する(第1図(d))
Plasma C
The substrate 1 is placed in a VD method device and decomposed by glow discharge.
An amorphous semiconductor layer 3 is deposited on the entire surface (Fig. 1(d)).
.

非晶質半導体153はP−1−N接合が施されている非
晶質シリコンであり、P層の形成はシラン、水素及びP
型ドープ剤としてジボランを添加した混合ガスを用いて
、基板温度150〜200℃、ガス圧1.0〜1.3T
orrに保ち、13.56MIIzの高周波電圧印加す
る。IJIはシラン、水素を、N層はシラン、水素、N
型ドープ剤としてフォスフインを添加した混合ガスを用
いて夫々被着する。非晶質半導体層3の膜厚は0.5〜
1μmである。
The amorphous semiconductor 153 is amorphous silicon with a P-1-N junction, and the P layer is formed using silane, hydrogen, and P.
Using a mixed gas containing diborane as a mold doping agent, the substrate temperature is 150-200°C and the gas pressure is 1.0-1.3T.
orr and apply a high frequency voltage of 13.56 MIIz. IJI contains silane and hydrogen, and N layer contains silane, hydrogen and N.
Each is deposited using a gas mixture to which phosphine is added as a mold dopant. The thickness of the amorphous semiconductor layer 3 is 0.5~
It is 1 μm.

次に、基板1に配列した第1電極28〜2cの接続用延
長部21a〜21c上の非晶質半導体層3の一部に配列
方向に沿ってレーザー照射で直線上の接続用開口部5が
形成される(第1図(e))。この接続用開口部5は非
晶質半導体層3を貫通して、第1電極の接続用延長部2
1a〜21c及び基板1を露出する。具体的には接続用
開口部5はNd−YAGレーザー光を照射し形成する。
Next, a portion of the amorphous semiconductor layer 3 on the connection extensions 21a to 21c of the first electrodes 28 to 2c arranged on the substrate 1 is irradiated with a laser along the arrangement direction to form a straight connection opening 5. is formed (Fig. 1(e)). This connection opening 5 penetrates the amorphous semiconductor layer 3 and extends through the connection extension 2 of the first electrode.
1a to 21c and the substrate 1 are exposed. Specifically, the connection opening 5 is formed by irradiating Nd-YAG laser light.

例えばレーザー発振のロスインチの周波数を2KHz、
 q板lに対するレーザー走査速度を100mm/se
cとする。図では接続用開口部5は直線状の溝とし”ζ
示したが、ロスインチの周波数を低くしたり、基板lに
対するレーザー走査速度を増したりし、直径20〜20
0μIの小孔を断続的に形成することも可能である。 
さらに第1電極28〜2cにダメージを与えず所定の開
口中にするためレーザーの出力、ロスインチの周波数及
びレーザー走査速度を種々に設定することも可能である
For example, if the loss inch frequency of laser oscillation is 2KHz,
Laser scanning speed for q plate l is 100mm/se
Let it be c. In the figure, the connection opening 5 is a straight groove.
However, by lowering the loss inch frequency and increasing the laser scanning speed for the substrate l,
It is also possible to form small holes of 0 μI intermittently.
Furthermore, it is also possible to variously set the laser output, loss inch frequency, and laser scanning speed in order to form a predetermined opening without damaging the first electrodes 28 to 2c.

さらに非晶質半導体層3上に第2電極28〜2c及びそ
の接続用延長部21a〜21c 、出力用端子部6cが
形成される所定形状の窓を有する第2電極形成用マスク
42が装着される(第1図(f))。
Further, a second electrode forming mask 42 having a window of a predetermined shape in which the second electrodes 28 to 2c, their connecting extensions 21a to 21c, and an output terminal portion 6c are formed is mounted on the amorphous semiconductor layer 3. (Figure 1(f)).

この状態でスパッタ法、抵抗加熱法、電子ビーム法を用
いて第2TL極4a〜4c及びその接続用延長部41a
〜41c、出力用端子部6cとなる金属膜が被着される
。金属はアルミニウム、ニッケル、クロム、チタン等で
あり、その厚膜は0.4〜1μmである。
In this state, the second TL poles 4a to 4c and their connecting extension portions 41a are formed by sputtering, resistance heating, or electron beam.
41c, a metal film that will become the output terminal portion 6c is deposited. The metal is aluminum, nickel, chromium, titanium, etc., and the thickness thereof is 0.4 to 1 μm.

非晶質半導体N3の膜厚よりも金属膜の方が薄くても、
金属膜の被着の際、基板lを回転させれば、接続用開口
部5のエッヂ部分での接続不良は生じない。
Even if the metal film is thinner than the amorphous semiconductor N3,
If the substrate 1 is rotated during deposition of the metal film, connection failures at the edge portions of the connection openings 5 will not occur.

そして、該マスク42を外し、所定形状の第2電極48
〜4c及びその接続用延長部41a〜41c、出力用端
子部6cが形成され、前記接続用開口部5を介し、発電
区域aの第1″rf極の接続用延長部21aと発電区域
すの第2電極の接続用延長部41bとが、発電区域すの
第1電極の接続用延長部21bと発電区域Cの第2電極
の接続用延長部41cとが夫々電気的に接続され、発電
区域a−cが直列接続される。
Then, the mask 42 is removed, and the second electrode 48 having a predetermined shape is removed.
4c, their connection extensions 41a to 41c, and an output terminal part 6c are formed, and the connection extension 21a of the first RF pole of the power generation area a and the power generation area The second electrode connection extension 41b is electrically connected to the first electrode connection extension 21b of the power generation area C and the second electrode connection extension 41c of the power generation area C, respectively. a-c are connected in series.

本発明によれば、実質的に接続が行われる部分は20〜
200μmの開口巾を有する接続用開口部5であるため
、第1電極の接続用延長部21a〜2bと第21極の接
続用延長部41b〜41cの巾が該接続用開口部5より
もやや大きい寸法でよく、光起電力装置の接続部分が極
めて小面積となる。
According to the invention, the portion where the connection is substantially made is from 20 to
Since the connection opening 5 has an opening width of 200 μm, the widths of the first electrode connection extensions 21a to 2b and the 21st electrode connection extensions 41b to 41c are slightly wider than the connection opening 5. The dimensions can be large, and the connecting portion of the photovoltaic device has an extremely small area.

第2図(a) (b)は本発明の光起電力装置の製造方
法の他の実施例の主要工程を示す平面図である。
FIGS. 2(a) and 2(b) are plan views showing the main steps of another embodiment of the method for manufacturing a photovoltaic device of the present invention.

基板1上に矩形状の第1電極2d〜2fが配列されてい
る。第1電極2d〜2fは接続用延長部はなく、基板1
のほぼ全面に位置する様に形成される。この第1電極2
d〜2f上に連続的に連なって非晶質半導体層3が形成
されている。非晶質半導体層3には第1 TL極2d〜
2fの配列方向に断続的な直線状の接続用開口部5d〜
5fが形成される(第2図(a))。
Rectangular first electrodes 2d to 2f are arranged on the substrate 1. The first electrodes 2d to 2f do not have connection extensions and are connected to the substrate 1.
It is formed so that it is located almost on the entire surface of the area. This first electrode 2
An amorphous semiconductor layer 3 is formed continuously on d to 2f. The amorphous semiconductor layer 3 has a first TL pole 2d~
Intermittent linear connection openings 5d in the arrangement direction of 2f.
5f is formed (FIG. 2(a)).

好ましくは、接続用開口部5d〜5「は、限りがなく第
1電極2d〜2fの端部に形成し、有効受光面積を増大
させる。
Preferably, the connection openings 5d to 5'' are formed at the ends of the first electrodes 2d to 2f without limit to increase the effective light receiving area.

そして、第2電ff14d〜4f及び接続用延長部41
e〜41f、出力端子部6fが形成される(第2図(b
))、 具体的には上述の如く第2電極形成用マスクの
操作により所定形状で形成され、発電区域「の第2電極
4fの接続用延長部41fが接続用開口部5eを介して
発電区域eの第1電極2eに接続し、発電区J−1ie
の第2を極4eの接続用延長部41eが接続用開口部5
dを介して発電区域dの第111極2dに接続し、発電
区域f−dが直列的に電気接続されるようにする。
Then, the second electric cables ff14d to 4f and the connection extension part 41
e to 41f, and the output terminal portion 6f are formed (Fig. 2(b)
)) Specifically, as described above, the second electrode is formed into a predetermined shape by operating the mask for forming the second electrode, and the connection extension 41f of the second electrode 4f of the power generation area is connected to the power generation area through the connection opening 5e. connected to the first electrode 2e of power generation section J-1ie
The second connection extension 41e of the pole 4e connects to the connection opening 5.
d to the 111th pole 2d of the power generation zone d, so that the power generation zones f and d are electrically connected in series.

かくして、上述の光起電力装置の出力は発電区域dの第
2電極4dの接続用延長部41dと発電区域fの第1電
極2f上の接続用開口部5fを介して接続する出力端子
部6fとの間から得られる。
Thus, the output of the photovoltaic device described above is connected to the output terminal portion 6f through the connection extension 41d of the second electrode 4d of the power generation area d and the connection opening 5f on the first electrode 2f of the power generation area f. It can be obtained from between.

上述の光起電力装置の製造方法において、接続用開口部
を断続的に設けたため、同一発電区域における第1電極
と第2?i!極とが対向し合う発電寄与部分を極めて大
きくでき、同一寸法の基板で製造した従来装置に比べ短
絡電流値が極めて向上する。
In the method for manufacturing the photovoltaic device described above, since the connection openings are provided intermittently, the first electrode and the second electrode in the same power generation area are connected intermittently. i! The portion contributing to power generation where the poles face each other can be made extremely large, and the short-circuit current value is significantly improved compared to conventional devices manufactured using substrates of the same size.

尚、上述の実施例において、第1電極に透明導電膜を、
第2電極に金属膜を夫々用いたが、第1電極に金属膜を
、第2電極に透明導電膜を用いても構わない。また、各
第1、第2電極の形状にはマスク操作をしたが、レジス
ト膜とエツチング処理により所定形状の第1、第2電極
を形成してもよい。
In addition, in the above-mentioned embodiment, a transparent conductive film is provided on the first electrode,
Although a metal film is used for each of the second electrodes, a metal film may be used for the first electrode, and a transparent conductive film may be used for the second electrode. Further, although the shape of each of the first and second electrodes is determined by a mask operation, the first and second electrodes having a predetermined shape may be formed by a resist film and an etching process.

〔効果〕〔effect〕

以上、上述した様に本発明は、絶縁基板上に複数個の第
1電極を配列形成し、該複数個の第1電掻を完全に覆う
非晶質半導体層を被着し、該複数個の第1?ilt極の
配列方向に沿ってレーザー照射で非晶質半導体層を貫通
する接続用開口部を形成し、さらに非晶質半導体層上に
複数個の第2電極を形成する際、接続用開口部を介し、
隣接する第1電極と電気的接続を施す光起電力装置の製
造方法であって、非晶質半導体層がマスクなしで被着さ
れるため、該非晶質半導体層にマスクとプラズマとによ
って生じる干渉が全くなく、膜質が安定し且つ外観品質
上極めて優れた非晶質半導体層が得られ、また各発電区
域の直列接続が最低−木の接続用開口部で達成できる。
As described above, the present invention includes forming a plurality of first electrodes in an array on an insulating substrate, depositing an amorphous semiconductor layer that completely covers the plurality of first electrodes, and forming a plurality of first electrodes on an insulating substrate. The first? When forming a connection opening that penetrates the amorphous semiconductor layer by laser irradiation along the arrangement direction of the ilt electrodes, and further forming a plurality of second electrodes on the amorphous semiconductor layer, the connection opening Through
A method of manufacturing a photovoltaic device in which an electrical connection is made to an adjacent first electrode, wherein an amorphous semiconductor layer is deposited without a mask, so that interference caused by the mask and plasma on the amorphous semiconductor layer is avoided. An amorphous semiconductor layer with no oxidation, stable film quality, and extremely excellent appearance quality can be obtained, and series connection of each power generation area can be achieved with a minimum diameter of connection opening.

また20〜200μmの巾又は直径の接続用開口部で接
続が施され、第1及び又は第2電掻の接続用延長部の巾
も極小化できるため基板に対する有効受光面積が向上す
る。これより製造用基板から取れる光起電力装置の個数
が増加するため、1個当たりの使用原料ガス、金属等が
少なくて済み、単価が極めて安価となる。
Further, since the connection is made through the connection opening having a width or diameter of 20 to 200 μm, and the width of the connection extension of the first and/or second electric scratcher can be minimized, the effective light-receiving area with respect to the substrate is improved. This increases the number of photovoltaic devices that can be obtained from the manufacturing substrate, so less raw material gas, metal, etc. are used per device, and the unit price becomes extremely low.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)乃至第1図(g)は本発明の光起電力装置
の製造方法の各工程を示す平面図であり、特に第1図(
g)は本発明の光起電力装置の製造方法によって製造さ
れた光起電力装置の平面図である。 第2図(a) 、 (b)は本発明の本発明の光起電力
装置の製造方法の他の実施例の主要工程のみを示す平面
図であり、特に第2図(b)はその製造方法によって製
造された光起電力装置の平面図である。 第3図(a)乃至第3図軸)は従来の光起電力装置の製
造方法の各工程を示す平面図であり、特に第3図(g)
は従来の光起電力装置の製造方法によって製造された光
起電力装置の平面図である。 1 ・・・基板 2a〜21・・・第1電極 3 ・・・非晶質半導体層 4a〜41・・・第2電掻
1(a) to 1(g) are plan views showing each step of the method for manufacturing a photovoltaic device of the present invention, and in particular, FIG.
g) is a plan view of a photovoltaic device manufactured by the method for manufacturing a photovoltaic device of the present invention. FIGS. 2(a) and 2(b) are plan views showing only the main steps of another embodiment of the method for manufacturing a photovoltaic device according to the present invention, and in particular, FIG. FIG. 2 is a plan view of a photovoltaic device manufactured by the method. FIG. 3(a) to FIG. 3(g) are plan views showing each step of the conventional method for manufacturing a photovoltaic device, especially FIG. 3(g).
1 is a plan view of a photovoltaic device manufactured by a conventional method for manufacturing a photovoltaic device. 1...Substrates 2a to 21...First electrode 3...Amorphous semiconductor layers 4a to 41...Second electric scraping

Claims (1)

【特許請求の範囲】 非晶質半導体層と、該非晶質半導体層を挟む第1、第2
電極とからなる複数個の発電区域を有し、該発電区域を
絶縁基板上に配列形成した光起電力装置の製造方法にお
いて、 前記絶縁基板上に複数個の第1電極を形成し、該複数個
の第1電極を覆うように非晶質半導体層を被着した後、
該非晶質半導体層を貫通する接続用開口部を第1電極の
配列方向に沿った直線上に配置されるように形成し、次
いで各発電区域の起電力が直列に出力されるように非晶
質半導体層上に複数個の第2電極を形成し、隣接する発
電区域の第1電極を該接続用開口部を通じて電気的に接
続したことを特徴とする光起電力装置の製造方法。
[Claims] An amorphous semiconductor layer, a first and a second layer sandwiching the amorphous semiconductor layer.
A method for manufacturing a photovoltaic device having a plurality of power generation areas consisting of electrodes, and in which the power generation areas are arranged and formed on an insulating substrate, comprising: forming a plurality of first electrodes on the insulating substrate; After depositing an amorphous semiconductor layer to cover the first electrodes,
Connection openings penetrating the amorphous semiconductor layer are formed so as to be arranged on a straight line along the arrangement direction of the first electrodes, and then an amorphous semiconductor layer is formed so that the electromotive force of each power generation area is output in series. A method for manufacturing a photovoltaic device, characterized in that a plurality of second electrodes are formed on a semiconductor layer, and first electrodes of adjacent power generation areas are electrically connected through the connection opening.
JP61075263A 1986-03-31 1986-03-31 Photovoltaic device manufacturing method Expired - Lifetime JPH07105510B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP61075263A JPH07105510B2 (en) 1986-03-31 1986-03-31 Photovoltaic device manufacturing method
US07/032,164 US4773943A (en) 1986-03-31 1987-03-30 Photovoltaic device and a method of producing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61075263A JPH07105510B2 (en) 1986-03-31 1986-03-31 Photovoltaic device manufacturing method

Publications (2)

Publication Number Publication Date
JPS62232175A true JPS62232175A (en) 1987-10-12
JPH07105510B2 JPH07105510B2 (en) 1995-11-13

Family

ID=13571159

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61075263A Expired - Lifetime JPH07105510B2 (en) 1986-03-31 1986-03-31 Photovoltaic device manufacturing method

Country Status (1)

Country Link
JP (1) JPH07105510B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0193174A (en) * 1987-10-05 1989-04-12 Kanegafuchi Chem Ind Co Ltd Manufacture of semiconductor device
EP3767398A4 (en) * 2018-03-14 2021-12-01 Casio Computer Co., Ltd. Solar panel, display device, and watch

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55107276A (en) * 1979-02-09 1980-08-16 Sanyo Electric Co Ltd Photoelectromotive force device
JPS60117649A (en) * 1983-11-16 1985-06-25 ア−ルシ−エ− コ−ポレ−ション Photocell array
JPS6276786A (en) * 1985-09-30 1987-04-08 Sanyo Electric Co Ltd Manufacture of photovoltaic device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55107276A (en) * 1979-02-09 1980-08-16 Sanyo Electric Co Ltd Photoelectromotive force device
JPS60117649A (en) * 1983-11-16 1985-06-25 ア−ルシ−エ− コ−ポレ−ション Photocell array
JPS6276786A (en) * 1985-09-30 1987-04-08 Sanyo Electric Co Ltd Manufacture of photovoltaic device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0193174A (en) * 1987-10-05 1989-04-12 Kanegafuchi Chem Ind Co Ltd Manufacture of semiconductor device
EP3767398A4 (en) * 2018-03-14 2021-12-01 Casio Computer Co., Ltd. Solar panel, display device, and watch

Also Published As

Publication number Publication date
JPH07105510B2 (en) 1995-11-13

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