JPH0671095B2 - Photovoltaic device manufacturing method - Google Patents
Photovoltaic device manufacturing methodInfo
- Publication number
- JPH0671095B2 JPH0671095B2 JP60119335A JP11933585A JPH0671095B2 JP H0671095 B2 JPH0671095 B2 JP H0671095B2 JP 60119335 A JP60119335 A JP 60119335A JP 11933585 A JP11933585 A JP 11933585A JP H0671095 B2 JPH0671095 B2 JP H0671095B2
- Authority
- JP
- Japan
- Prior art keywords
- power generation
- electrodes
- electrode
- amorphous semiconductor
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000010248 power generation Methods 0.000 claims description 40
- 239000004065 semiconductor Substances 0.000 claims description 33
- 239000000758 substrate Substances 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 13
- 239000004020 conductor Substances 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 7
- 239000011800 void material Substances 0.000 claims description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 238000006243 chemical reaction Methods 0.000 description 6
- 239000012495 reaction gas Substances 0.000 description 5
- 229910003437 indium oxide Inorganic materials 0.000 description 4
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 4
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 239000011669 selenium Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 2
- 229910001887 tin oxide Inorganic materials 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 description 1
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000002223 garnet Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 229910052744 lithium Inorganic materials 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910052711 selenium Inorganic materials 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/042—PV modules or arrays of single PV cells
- H01L31/0445—PV modules or arrays of single PV cells including thin film solar cells, e.g. single thin film a-Si, CIS or CdTe solar cells
- H01L31/046—PV modules composed of a plurality of thin film solar cells deposited on the same substrate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Landscapes
- Life Sciences & Earth Sciences (AREA)
- Sustainable Development (AREA)
- Engineering & Computer Science (AREA)
- Sustainable Energy (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Photovoltaic Devices (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は非晶質半導体層を有し、基板の一主面に形成さ
れた複数の発電区域が配列方向に直列接続されて成る太
陽電池や光センサ等の光起電力装置の製造方法に関す
る。The present invention relates to a solar cell having an amorphous semiconductor layer, in which a plurality of power generation areas formed on one main surface of a substrate are connected in series in an array direction. And a method for manufacturing a photovoltaic device such as an optical sensor.
（従来の技術） 第２図は従来の各発電区域が直列接続する光起電力装置
の構造を示す断面図である。(Prior Art) FIG. 2 is a cross-sectional view showing a structure of a photovoltaic device in which conventional power generation areas are connected in series.
21は絶縁基板、22a,22bは該基板21上に被着形成した第
１電極、23a,23bは夫々第１電極22a,22b上に被着した非
晶質半導体層、24a,24bは夫々非晶質半導体層23a,23b上
に被着した第２電極である。Reference numeral 21 is an insulating substrate, 22a and 22b are first electrodes deposited on the substrate 21, 23a and 23b are amorphous semiconductor layers deposited on the first electrodes 22a and 22b, and 24a and 24b are non-conductive layers. This is the second electrode deposited on the crystalline semiconductor layers 23a and 23b.
上記の絶縁基板21は可視光線を透過するガラス基板又
は、セラミック基板などが用いられ、第１電極22a,22b
及び第２電極24a,24bは光が入射する側の電極は透光性
を有する酸化錫、酸化インジウム、などで構成され、他
方の電極はアルミニウム、クロム、ニッケルなどの金属
で構成されている。A glass substrate or a ceramic substrate that transmits visible light is used as the insulating substrate 21, and the first electrodes 22a and 22b are used.
The electrodes of the second electrodes 24a and 24b on the light incident side are made of translucent tin oxide, indium oxide, or the like, and the other electrodes are made of metal such as aluminum, chromium, or nickel.
上記非晶質半導体層23a,23bは光照射によって電子、正
孔を発生するもので、第１電極22a,22b側からＰ型層、
ｉ型（ノンドープ）層及びＮ型層の３層構造となってい
る非晶質シリコン層などが用いられる。The amorphous semiconductor layers 23a and 23b generate electrons and holes by light irradiation. The amorphous semiconductor layers 23a and 23b are P-type layers from the first electrodes 22a and 22b side,
An amorphous silicon layer having a three-layer structure of an i-type (non-doped) layer and an N-type layer is used.
上記の光起電力装置の製造方法としては、各発電区域の
形状に応じて所定の形状の孔を有する金属マスクが用い
られる。該マスクを絶縁基板21上に装着し、第１電極形
成装置で、第１電極22a,22bを基板21上に被着形成す
る。次に該マスクを第１電極22a,22bの配列方向に所定
の距離だけ移動させ、第１電極22a,22b上に装着する。
この後に、プラズマCVD装置等を用いて非晶質半導体層2
3a,23bを該第１電極22a,22b上に被着形成する。さらに
該マスクを上述と同一方向に所定の距離だけ移動させ、
非晶質半導体層23a,23b上に装着する。この後に第２電
極形成装置で、第２電極24a,24bを被着形成する。これ
により発電区域ａ′の第１電極22aが隣接する発電区域
ｂ′の第２電極24bに接続された光起電力装置が製造さ
れる。（特公昭48−26977号公報参照） また別の製造方法としては、基板21上に所定の形状をし
た第１電極22a,22b上に非晶質半導体層23a,23bを被着形
成し、非晶質半導体層23a,23bの不必要部分をマスクを
介してプラズマエッチング、逆スパッタリング又はレー
ザビーム照射等の手法で除去する。さらに該非晶質半導
体層23a,23b上に第２電極24a,24bを被着形成し、上述の
手法で、不必要部分の第２電極24a,24bを除去して上記
と同様に直列接続された光起電力装置が製造される。
（特開57−12568号公報参照） 上記の従来の光起電力装置において各発電区域ａ′,b′
に光が照射されると非晶質半導体層23a,23bに電子、正
孔が発生し、第１電極22a,22bと第２電極24a,24b間に電
位差が生じる。As a method for manufacturing the above photovoltaic device, a metal mask having a hole having a predetermined shape according to the shape of each power generation area is used. The mask is mounted on the insulating substrate 21, and the first electrodes 22a and 22b are formed on the substrate 21 by the first electrode forming apparatus. Next, the mask is moved by a predetermined distance in the arrangement direction of the first electrodes 22a, 22b and mounted on the first electrodes 22a, 22b.
After this, the amorphous semiconductor layer 2 is formed using a plasma CVD device or the like.
3a and 23b are deposited on the first electrodes 22a and 22b. Furthermore, by moving the mask in the same direction as the above by a predetermined distance,
It is mounted on the amorphous semiconductor layers 23a and 23b. After that, the second electrodes 24a and 24b are deposited by the second electrode forming apparatus. This produces a photovoltaic device in which the first electrode 22a of the power generation area a'is connected to the second electrode 24b of the adjacent power generation area b '. (See Japanese Patent Publication No. 48-26977) As another manufacturing method, the amorphous semiconductor layers 23a and 23b are formed by depositing on the substrate 21 on the first electrodes 22a and 22b having a predetermined shape. Unnecessary portions of the crystalline semiconductor layers 23a, 23b are removed through a mask by a method such as plasma etching, reverse sputtering, or laser beam irradiation. Further, the second electrodes 24a and 24b are formed by depositing on the amorphous semiconductor layers 23a and 23b, and the unnecessary portions of the second electrodes 24a and 24b are removed by the above-described method, and the second electrodes 24a and 24b are connected in series in the same manner as above. A photovoltaic device is manufactured.
(See Japanese Patent Application Laid-Open No. 57-12568) In each of the conventional photovoltaic devices described above, each power generation area a ', b'
When the amorphous semiconductor layers 23a and 23b are irradiated with light, electrons and holes are generated, and a potential difference is generated between the first electrodes 22a and 22b and the second electrodes 24a and 24b.
この時、発電区域ａ′の第１電極22aと発電区域ｂ′の
第２電極24bが電気的に接続された状態となり、各発電
区域ａ′,b′の起電圧は相加される。At this time, the first electrode 22a of the power generation area a'and the second electrode 24b of the power generation area b'are electrically connected, and the electromotive voltages of the power generation areas a'and b'are added.
（発明が解決しようとする問題点） しかし従来の直列接続された光起電力装置は、直列接続
を形成するために製造上、マスクを何回も移動させた
り、又は数種類のマスクを使用しなければならないため
にマスクの脱着作業時に各層を損傷させ、又誤操作によ
って接続不良を招くといった問題を生じる。また、接続
部分がせいぜい１μｍ程度の第１電極と第２電極とが重
畳しているだけであり、複数の発電区域を直列接続させ
た場合、光起電力装置の直列抵抗分が大きくなり、光電
変換による出力を充分引き出すことが困難であった。(Problems to be Solved by the Invention) However, in the conventional photovoltaic devices connected in series, the mask must be moved many times or several kinds of masks must be used in manufacturing in order to form the series connection. Therefore, there is a problem in that each layer is damaged when the mask is attached and detached, and a connection failure is caused by an erroneous operation. In addition, the first electrode and the second electrode, which have a connection portion of at most about 1 μm, overlap each other, and when a plurality of power generation areas are connected in series, the series resistance of the photovoltaic device increases, and It was difficult to obtain the output of the conversion sufficiently.
（本発明の目的） 本発明の目的は上述の欠点を一挙に解決するものであ
り、接続不良がなく複数の発電区域を直列接続しても良
好な特性の出力を得ることにある。(Object of the present invention) The object of the present invention is to solve the above-mentioned drawbacks all at once, and to provide an output with good characteristics even if a plurality of power generation areas are connected in series without a connection failure.
（問題を解決するための手段） 上述の目的を達成するために本発明は基板の一主面上に
複数の下部電極を被着形成する工程と、複数の下部電極
上に連続して非晶質半導体層及び上部電極層を被着する
工程と、隣接する下部電極間の一部において上部電極層
及び非晶質半導体層を除去し、下部電極及び基板が露出
する空隙部を設けることにより、基板上で下部電極、非
晶質半導体層及び上部電極からなる発電区域を複数個に
分割する工程と、該空隙部に導電性材料を充填し、互い
に隣接する発電区域の一方の発電区域の下部電極と他方
の発電区域の上部電極とを電気的に接続する工程と、隣
接する発電区域の一方の発電区域の下部電極と他方の発
電区域の上部電極との電気的接続を維持させつつ、隣接
する各発電区域の上部電極が実質的に電気的に接続しな
いように発電区域内で少なくとも上部電極に絶縁溝を形
成する工程からなる光起電力装置の製造方法である。(Means for Solving the Problems) In order to achieve the above-mentioned object, the present invention comprises a step of depositing a plurality of lower electrodes on one main surface of a substrate, and a continuous amorphous process on the plurality of lower electrodes. A step of depositing a high-quality semiconductor layer and an upper electrode layer, and removing the upper electrode layer and the amorphous semiconductor layer in a part between adjacent lower electrodes, and providing a void portion exposing the lower electrode and the substrate, A step of dividing a power generation area composed of a lower electrode, an amorphous semiconductor layer, and an upper electrode on a substrate into a plurality of parts, and filling the voids with a conductive material to form a lower part of one of the power generation areas adjacent to each other. A step of electrically connecting the electrode and the upper electrode of the other power generation area, and an electrical connection between the lower electrode of one power generation area of the adjacent power generation area and the upper electrode of the other power generation area while maintaining the electrical connection between them. The upper electrode of each power generation area is Is a method for manufacturing a photovoltaic device, which comprises a step of forming an insulating groove in at least an upper electrode in a power generation area so as not to be electrically connected.
（実施例） 以下、本発明の実施例を図面に基いて詳説する。(Example) Hereinafter, the Example of this invention is described in detail based on drawing.
本発明の複数の発電区域が直列接続されて成る光起電力
装置の製造方法を第１図（ａ）〜（ｆ）に基いて説明す
る。A method for manufacturing a photovoltaic device according to the present invention in which a plurality of power generation areas are connected in series will be described with reference to FIGS. 1 (a) to 1 (f).
第１図（ａ）において、ガラス等の絶縁基板１の一主面
上に所定の形状をした複数の第１電極2a,2bが被着形成
される。該第１電極2a,2bはインジウム錫をターゲット
にしてアルゴン圧5.0×10-2Torrの雰囲気中でスパッタ
リングを行い、基板１上に酸化インジウム・錫（ITO）
を析出させたものである。前記酸化インジウム・錫の他
に酸化錫，酸化インジウム等の透明導電膜を使用するこ
とができる。In FIG. 1 (a), a plurality of first electrodes 2a, 2b having a predetermined shape are adhered and formed on one main surface of an insulating substrate 1 such as glass. The first electrodes 2a and 2b are formed by sputtering indium tin oxide (ITO) on the substrate 1 by sputtering indium tin as a target in an atmosphere of argon pressure of 5.0 × 10 -2 Torr.
Is deposited. In addition to the above-mentioned indium oxide / tin, a transparent conductive film of tin oxide, indium oxide or the like can be used.
第１図（ｂ）において、複数の第１電極2a,2bが形成さ
れた該基板１をプラズマCVD装置中に搬入し、所定の反
応ガスをグロー放電分解させ、第１電極2a,2b上に全面
に渡り連なった非晶質半導体層３を被着する。非晶質半
導体層３がｐ−ｉ−ｎ型非晶質シリコン層の構成である
ならば、先ず、プラズマCVD装置の反応室にSiH4,B2H6,H
2の各ガスを所定の比で混合した反応ガスを一定流量で
導入し、反応室内を一定ガス圧に保ち、かつ基板１を15
0〜250℃に加熱して、13.56MHzの高周波電圧を印加し、
グロー放電を発生させる。これにより反応ガスがプラズ
マ化し、基板１の第１電極2a,2b上にｐ型非晶質シリコ
ン層を生成する。次に反応ガスとしてSiH4,H2を所定の
比で混合したものを用いて、上述と同様にグロー放電を
発生させ、ｐ型非晶質シリコン層上にｉ型非晶質シリコ
ン層を生成する。さらにSiH4,PH3,H2を所定の比で混合
した反応ガスを用いて、上述と同様にグロー放電を発生
させ、ｉ型非晶質シリコン層上にｎ型非晶質シリコン層
を生成する。この様に積層された非晶質シリコン層の膜
厚は0.5〜１μｍ程度である。また、スペクトル感度特
性を広範囲にするため非晶質シリコン層を多層構造にし
たタンデム構造でもよく、上記反応ガスの主成分として
炭素C,窒素N,錫Sn,リチウムLi,酸素O,弗素F,ゲルマニウ
ムGe,セレンSeを用いることができる。In FIG. 1 (b), the substrate 1 on which a plurality of first electrodes 2a, 2b are formed is loaded into a plasma CVD apparatus, and a predetermined reaction gas is decomposed by glow discharge, and the first electrodes 2a, 2b are placed on the first electrodes 2a, 2b. A continuous amorphous semiconductor layer 3 is deposited. If the amorphous semiconductor layer 3 has a structure of a pin type amorphous silicon layer, first, SiH 4 , B 2 H 6 , and H are provided in the reaction chamber of the plasma CVD apparatus.
The reaction gas prepared by mixing the respective gases of 2 at a predetermined ratio is introduced at a constant flow rate to keep the reaction chamber at a constant gas pressure, and
Heat to 0 ~ 250 ℃, apply a high frequency voltage of 13.56MHz,
Generate glow discharge. As a result, the reaction gas is turned into plasma and a p-type amorphous silicon layer is formed on the first electrodes 2a, 2b of the substrate 1. Then, using a mixture of SiH 4 and H 2 as a reaction gas at a predetermined ratio, a glow discharge is generated in the same manner as described above to form an i-type amorphous silicon layer on the p-type amorphous silicon layer. To do. Further, using a reaction gas in which SiH 4 , PH 3 , and H 2 are mixed at a predetermined ratio, glow discharge is generated in the same manner as described above, and an n-type amorphous silicon layer is formed on the i-type amorphous silicon layer. To do. The thickness of the amorphous silicon layer thus laminated is about 0.5 to 1 μm. In addition, a tandem structure in which the amorphous silicon layer has a multi-layered structure in order to broaden the spectral sensitivity characteristics may be used, and carbon C, nitrogen N, tin Sn, lithium Li, oxygen O, fluorine F, and Germanium Ge and selenium Se can be used.
第１図（ｃ）において、非晶質半導体層３上の全面に、
第２電極4a,4bとなる第２電極層４が被着される。第２
電極層４はNi,Cr,Alなどの金属を蒸着することによって
析出する。In FIG. 1C, the entire surface of the amorphous semiconductor layer 3 is
A second electrode layer 4 to be the second electrodes 4a, 4b is deposited. Second
The electrode layer 4 is deposited by depositing a metal such as Ni, Cr and Al.
この第２電極層４は非晶質半導体層３と同一部分に形成
するため、この間の工程間にマスクの交換が不要である
ため、マスクの脱着時、非晶質半導体層３等に損傷を与
えることなく、またプラズマCVD装置の反応室と金属蒸
着装置の反応室を連設でき一連のインライン装置として
稼動させることが可能である。Since the second electrode layer 4 is formed in the same portion as the amorphous semiconductor layer 3, it is not necessary to replace the mask between the steps, so that the amorphous semiconductor layer 3 and the like are not damaged when the mask is attached and detached. Without supplying, the reaction chamber of the plasma CVD apparatus and the reaction chamber of the metal deposition apparatus can be connected in series and can be operated as a series of in-line apparatuses.
第１図（ｄ）は隣接する下部電極2a,2b間の一部におい
て上部電極層４及び非晶質半導体層３を除去し、下部電
極2a,2b及び基板１が露出する空隙部61,62を設けること
により、基板１上で下部電極2a,2b、非晶質半導体層3a,
3b及び上部電極4a,4bからなる発電区域を複数個a,bに分
割する工程を示す。In FIG. 1 (d), the upper electrode layer 4 and the amorphous semiconductor layer 3 are removed in a part between the adjacent lower electrodes 2a and 2b, and the lower electrodes 2a and 2b and the substrate 1 are exposed to voids 61 and 62. By providing the lower electrodes 2a, 2b, the amorphous semiconductor layer 3a,
The step of dividing the power generation area composed of 3b and the upper electrodes 4a and 4b into a plurality of a and b is shown.
上部電極層４及び非晶質半導体層３を除去し空隙部61,6
2を設ける手段として、レーザービーム照射によるエッ
チング、レジスト膜とエッチング液を用いてエッチング
するなどあるが、工程の簡略化を考慮し、レーザービー
ム照射が好ましい。この時用いられるレーザービームは
YAG（Y3Al5O12・イットリウム−ガーネット）レーザの
第２高調波0.53μｍを用いる。これは、金属薄膜である
第２電極層４及び非晶質半導体層３を除去するが、酸化
インジウム・錫等の第１電極2a,2b及び基板１に損傷を
与えないという点で極めて好都合である。The upper electrode layer 4 and the amorphous semiconductor layer 3 are removed to remove the voids 61, 6
As means for providing 2, there are etching by laser beam irradiation, etching using a resist film and an etching solution, and the like, but laser beam irradiation is preferable in consideration of simplification of the process. The laser beam used at this time is
The second harmonic wave 0.53 μm of a YAG (Y 3 Al 5 O 12 yttrium-garnet) laser is used. This is very convenient in that it removes the second electrode layer 4 and the amorphous semiconductor layer 3 which are metal thin films, but does not damage the first electrodes 2a, 2b such as indium oxide / tin and the substrate 1. is there.
第１図（ｅ）は前工程で設けられた空隙部61,62に銀等
の抵抗率の小さい導電性接続部81,82を形成する工程で
ある。FIG. 1 (e) shows a step of forming conductive connecting portions 81, 82 of silver or the like having a low resistivity in the void portions 61, 62 provided in the previous step.
導電性接続部81,82は空隙部61,62に厚膜手法を用いて導
電性材料である銀等の金属ペーストをプリント印刷等で
充填し、さらに焼成し形成され、これにより各発電区域
a,bを電気的に接続する。The conductive connecting portions 81, 82 are formed by filling the void portions 61, 62 with a metal paste such as silver, which is a conductive material, by print printing using the thick film method, and then firing the paste.
Electrically connect a and b.
他に導電性接続部81,82として抵抗率の小さい導電性金
属などを蒸着等の手法で各発電区域a,bを電気的に接続
させても構わない。Alternatively, as the conductive connecting portions 81 and 82, a conductive metal or the like having a low resistivity may be electrically connected to the power generation areas a and b by a method such as vapor deposition.
第１図（ｆ）は前工程で電気的に接続した各発電区域a,
bを直列接続される様に分割する工程である。Figure 1 (f) shows each power generation area a, electrically connected in the previous process.
This is a step of dividing b so as to be connected in series.
基板１上に形成された発電区域a,bに第１電極2a,2bが露
出するように絶縁溝71,72が形成される。この時、第２
電極4a,4bの上部よりレーザービームを照射して絶縁溝7
1,72となる部分の第２電極4a,4b及び非晶質半導体層3a,
3bが除去される。これによって各発電区域a,bが直列接
続される。即ち、発電区域ａの第１電極2a−非晶質半導
体層3a−第２電極4a−導電性接続部82−発電区域ｂの第
１電極2b−非晶質半導体層3b−第２電極4bと電気的に接
続される。Insulation grooves 71, 72 are formed in the power generation areas a, b formed on the substrate 1 so that the first electrodes 2a, 2b are exposed. At this time, the second
A laser beam is irradiated from above the electrodes 4a, 4b to form an insulating groove 7
The second electrodes 4a, 4b and the amorphous semiconductor layers 3a,
3b is removed. As a result, the power generation areas a and b are connected in series. That is, first electrode 2a in power generation area a-amorphous semiconductor layer 3a-second electrode 4a-conductive connection portion 82-first electrode 2b in power generation area b-amorphous semiconductor layer 3b-second electrode 4b. It is electrically connected.
この工程でレーザービームを照射する位置は導電性接続
部81,82に接するようにし、第１電極2a,2bを露出するよ
うにしてもよいが、レーザービーム照射の位置合せが困
難で、導電性接続部81,82を除去され、電気的接続が断
たれないように第１電極2a,2b上の一部に障壁部51,52が
形成される絶縁溝71,72を設けることが好ましい。In this step, the position where the laser beam is irradiated may be in contact with the conductive connecting portions 81 and 82 to expose the first electrodes 2a and 2b, but it is difficult to align the laser beam irradiation, It is preferable to remove the connecting portions 81 and 82 and provide insulating grooves 71 and 72 in which the barrier portions 51 and 52 are formed in a part of the first electrodes 2a and 2b so that the electrical connection is not broken.
以上の製造方法によって各発電区域a,bを電気的に接続
させる導電性接続部81,82となる導電性材料が簡単に充
填でき、さらにその後、レーザービーム照射により形成
される絶縁溝71,72によって隣接する発電区域の上部電
極4a,4bが互いに短絡することなく、完全に直列接続さ
れる。By the above manufacturing method, the conductive material to be the conductive connecting portions 81, 82 for electrically connecting the respective power generation areas a, b can be easily filled, and thereafter, the insulating grooves 71, 72 formed by laser beam irradiation. Thus, the upper electrodes 4a and 4b of the adjacent power generation areas are completely connected in series without short-circuiting each other.
尚、障壁部51,52を形成する空隙部61,62及び絶縁溝71,7
2の幅は、レーザビーム照射の絞り加減で数μｍまで抑
えることができるが空隙部61,62の幅Ｌは導電性接続部8
1,82に電流が流れるために少なくとも50μｍは必要であ
り、絶縁溝71,72の幅ｌは隣接する発電区域の第２電極4
a,4bが互いに短絡しない程度に設定すればよく、少なく
とも５μｍ程度でよい。The voids 61 and 62 and the insulating grooves 71 and 7 that form the barriers 51 and 52 are formed.
The width of 2 can be suppressed to several μm by adjusting the aperture of the laser beam irradiation, but the width L of the voids 61 and 62 is the conductive connecting portion 8
At least 50 μm is required for the electric current to flow in 1,82, and the width l of the insulating grooves 71,72 is equal to the width of the second electrode 4 in the adjacent power generation area.
It may be set so that a and 4b do not short-circuit with each other, and may be at least about 5 μm.
尚、本発明の実施例は基板１に透明絶縁基板を用いて透
明絶縁基板／透明電極／非晶質半導体層／金属薄膜電極
という構成の発電区域となる、基板１側から光を入射す
る場合で説明したが、基板１にセラミックなどの絶縁基
板を用いて、第１電極2a,2bに金属薄膜電極、第２電極4
a,4bに透明電極で構成した、即ち絶縁基板／金属薄膜電
極／非晶質半導体層／透明電極の発電区域を有する、基
板１とは逆側入射の光起電力装置も本発明の請求範囲を
逸脱するものではない。In the embodiment of the present invention, a transparent insulating substrate is used as the substrate 1 to form a power generation area having a structure of transparent insulating substrate / transparent electrode / amorphous semiconductor layer / metal thin film electrode. As described above, an insulating substrate such as ceramic is used for the substrate 1, the first electrodes 2a and 2b are metal thin film electrodes, and the second electrode 4 is used.
A photovoltaic device of opposite incidence to the substrate 1 which is composed of transparent electrodes on a and 4b, that is, has a power generation area of insulating substrate / metal thin film electrode / amorphous semiconductor layer / transparent electrode is also claimed in the present invention. Does not deviate from.
（発明の効果） 以上の様に構成された光起電力装置によれば、太陽電池
の全体の直列抵抗を大きく左右する各発電区域の接続部
分に極めて抵抗率の小さい良導電体の接続部を用いるた
め、光電変換によって得た出力を高く供給でき、また、
第１電極及び第２電極が直接接触していないため、該電
極を酸化などによって変質させることがない。(Effects of the Invention) According to the photovoltaic device configured as described above, a connection portion of a good conductor having an extremely low resistivity is provided at the connection portion of each power generation area that largely affects the series resistance of the entire solar cell. Since it is used, the output obtained by photoelectric conversion can be supplied high, and
Since the first electrode and the second electrode are not in direct contact with each other, the electrodes are not deteriorated by oxidation or the like.
さらに、複数の下部電極上に連続して被着形成した非晶
質半導体層及び上部電極層に空隙部を設け、この空隙部
に導電性材料を充填し導電性接続部を形成した後、各発
電区域が直列接続するように製造されるため、空隙部に
導電性材料を充填する際数μｍの精度で位置合せする必
要がなく、容易に充填することができ、最終工程で各発
電区域を直列接続させるため、空隙部からはみ出した導
電性材料があっても全く無視して絶縁溝を設け簡単に直
列接続できるという生産性にすぐれた製造方法となる。Further, after forming a void portion in the amorphous semiconductor layer and the upper electrode layer which are continuously formed on the plurality of lower electrodes and filling the void portion with a conductive material to form a conductive connection portion, Since the power generation areas are manufactured so that they are connected in series, there is no need to align with a precision of a few μm when filling the voids with a conductive material, and they can be easily filled, and each power generation area can be filled in the final step. Since they are connected in series, even if there is a conductive material protruding from the void portion, the manufacturing method is excellent in productivity in that it is possible to simply ignore the conductive material and form an insulating groove to simply connect in series.
第１図（ａ）乃至（ｆ）は本発明の光起電力装置の製造
方法を示す断面図であり、工程毎に示した図である。 第２図は従来の光起電力装置の構造を示す断面図であ
る。 １……基板、2a,2b……第１電極、3,3a,3b……非晶質半
導体層、４……第２電極層、4a,4b……第２電極、51,52
……障壁部、61,62……空隙部、71,72……絶縁溝、81,8
2……導電性接続部FIGS. 1 (a) to 1 (f) are cross-sectional views showing a method for manufacturing a photovoltaic device of the present invention, showing each step. FIG. 2 is a sectional view showing the structure of a conventional photovoltaic device. 1 ... Substrate, 2a, 2b ... First electrode, 3,3a, 3b ... Amorphous semiconductor layer, 4 ... Second electrode layer, 4a, 4b ... Second electrode, 51, 52
...... Barrier part, 61,62 …… Gap part, 71,72 …… Insulation groove, 81,8
2 ... Conductive connection
Claims (1)
成する工程と、複数の下部電極上に連続して非晶質半導
層及び上部電極層を被着する工程と、隣接する下部電極
間の一部において上部電極層及び非晶質半導体層を除去
し、下部電極及び基板が露出する空隙部を設けることに
より、基板上で下部電極、非晶質半導体層及び上部電極
からなる発電区域を複数個に分割する工程と、該空隙部
に導電性材料を充填し、互いに隣接する発電区域の一方
の発電区域の下部電極と他方の発電区域の上部電極とを
電気的に接続する工程と、隣接する発電区域の一方の発
電区域の下部電極と他方の発電区域の上部電極との電気
的接続を維持させつつ、隣接する各発電区域の上部電極
が実質的に電気的に接続しないように発電区域内で少な
くとも上部電極に絶縁溝を形成する工程と、からなる光
起電力装置の製造方法。1. A step of depositing a plurality of lower electrodes on one main surface of a substrate, and a step of depositing an amorphous semiconductor layer and an upper electrode layer continuously on the plurality of lower electrodes. By removing the upper electrode layer and the amorphous semiconductor layer at a part between the adjacent lower electrodes and providing a void portion exposing the lower electrode and the substrate, the lower electrode, the amorphous semiconductor layer, and the upper electrode on the substrate. And dividing the power generation area into a plurality of parts, and electrically filling the voids with a conductive material to electrically connect the lower electrode of one power generation area and the upper electrode of the other power generation area of the power generation areas adjacent to each other. While maintaining the electrical connection between the connecting step and the lower electrode of one power generating area of the adjacent power generating area and the upper electrode of the other power generating area, the upper electrode of each adjacent power generating area is substantially electrically At least on the upper electrode in the power generation area to avoid connecting Forming a edge groove, method for manufacturing a photovoltaic device comprising a.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60119335A JPH0671095B2 (en) | 1985-05-31 | 1985-05-31 | Photovoltaic device manufacturing method |
| US06/766,133 US4645866A (en) | 1984-08-18 | 1985-08-15 | Photovoltaic device and a method of producing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60119335A JPH0671095B2 (en) | 1985-05-31 | 1985-05-31 | Photovoltaic device manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61278170A JPS61278170A (en) | 1986-12-09 |
| JPH0671095B2 true JPH0671095B2 (en) | 1994-09-07 |
Family
ID=14758932
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60119335A Expired - Fee Related JPH0671095B2 (en) | 1984-08-18 | 1985-05-31 | Photovoltaic device manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0671095B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63253674A (en) * | 1987-04-10 | 1988-10-20 | Sanyo Electric Co Ltd | Manufacture of photovoltaic device |
| CN101958361A (en) * | 2009-07-13 | 2011-01-26 | 无锡尚德太阳能电力有限公司 | Method for etching transparent thin-film solar cell component |
-
1985
- 1985-05-31 JP JP60119335A patent/JPH0671095B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61278170A (en) | 1986-12-09 |
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