JPH0174592U - - Google Patents
Info
- Publication number
- JPH0174592U JPH0174592U JP1987170042U JP17004287U JPH0174592U JP H0174592 U JPH0174592 U JP H0174592U JP 1987170042 U JP1987170042 U JP 1987170042U JP 17004287 U JP17004287 U JP 17004287U JP H0174592 U JPH0174592 U JP H0174592U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- outputs
- signal
- motor drive
- reference clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011159 matrix material Substances 0.000 claims 2
- 230000010355 oscillation Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Electromechanical Clocks (AREA)
Description
第１図は本考案の一実施例の構成を示すブロツ
ク回路図、第２図は第１図のＲＯＭの構成を詳細
に示す図、第３図は第１図におけるラツチ回路Ａ
，Ｂの出力レベルとノアゲートＤ，Ｅの出力レベ
ルの関係を示す図、第４図は駆動パルスを示す図
である。
１……発振回路、２……分周回路、３，４……
ＲＯＭ、３ｂ……ゲート素子、４ａ……接点、５
……スイツチ回路、７，Ａ，Ｂ……ラツチ回路、
１３……ドライバー、１４……パルスモータ、Ｃ
……Ｔフリツプフロツプ、ＳＭ……モードスイツ
チ、Ｓ１……正転修正スイツチ、Ｓ２……逆転修
正スイツチ。
FIG. 1 is a block circuit diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a diagram showing details of the ROM configuration in FIG. 1, and FIG. 3 is a latch circuit A in FIG.
, B and the output levels of the NOR gates D and E. FIG. 4 is a diagram showing the drive pulses. 1... Oscillator circuit, 2... Frequency dividing circuit, 3, 4...
ROM, 3b...gate element, 4a...contact, 5
...Switch circuit, 7, A, B...Latch circuit,
13...Driver, 14...Pulse motor, C
...T flip-flop, SM...mode switch, S1...forward rotation correction switch, S2...reverse rotation correction switch.
Claims (1)
波数の異なる複数の信号を出力する分周回路と、 この分周回路の複数の出力信号が入力され、複
数の入力線と複数の出力線との交叉部に選択的に
機能素子が配されて所定のタイミングの信号を送
出するマトリツクス回路と、 このマトリツクス回路からのタイミング信号に
よりセツトおよびリセツトされ、ステツプモータ
の駆動信号を出力するラツチ回路とを備えること
を特徴とするアナログ電子時計のステツプモータ
駆動回路。[Claims for Utility Model Registration] An oscillator circuit that outputs a reference clock signal, a frequency divider circuit that divides the reference clock signal of this oscillation circuit and outputs a plurality of signals with different frequencies, and a plurality of these frequency divider circuits. A matrix circuit receives an output signal from the matrix circuit and selectively arranges functional elements at the intersections of the plurality of input lines and the plurality of output lines to send out a signal at a predetermined timing. 1. A step motor drive circuit for an analog electronic watch, comprising a latch circuit that is set and reset and outputs a step motor drive signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987170042U JPH0174592U (en) | 1987-11-09 | 1987-11-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987170042U JPH0174592U (en) | 1987-11-09 | 1987-11-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0174592U true JPH0174592U (en) | 1989-05-19 |
Family
ID=31460632
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987170042U Pending JPH0174592U (en) | 1987-11-09 | 1987-11-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0174592U (en) |
-
1987
- 1987-11-09 JP JP1987170042U patent/JPH0174592U/ja active Pending
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