JPH0170483U - - Google Patents

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Publication number
JPH0170483U
JPH0170483U JP1987163752U JP16375287U JPH0170483U JP H0170483 U JPH0170483 U JP H0170483U JP 1987163752 U JP1987163752 U JP 1987163752U JP 16375287 U JP16375287 U JP 16375287U JP H0170483 U JPH0170483 U JP H0170483U
Authority
JP
Japan
Prior art keywords
output
time base
color burst
signal
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1987163752U
Other languages
Japanese (ja)
Other versions
JPH0728787Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987163752U priority Critical patent/JPH0728787Y2/en
Publication of JPH0170483U publication Critical patent/JPH0170483U/ja
Application granted granted Critical
Publication of JPH0728787Y2 publication Critical patent/JPH0728787Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の一実施例の構成を示すブロ
ツク図。第2図はこの考案の一実施例の作用説明
に供するタイミング図。第3図は従来例の構成を
示すブロツク図。第4図は従来例の作用説明に供
するタイミング図。 1……可変遅延回路、7……積分器、8……電
圧制御発振器、9……水平同期信号分離回路、1
0……抽出回路、23……発振器、24……カウ
ンタ、25……フリツプフロツプ、26……シフ
トレジスタ、28,34および35……Dフリツ
プフロツプ、30,31および32……分周器、
40……位相比較器。
FIG. 1 is a block diagram showing the configuration of an embodiment of this invention. FIG. 2 is a timing chart for explaining the operation of one embodiment of this invention. FIG. 3 is a block diagram showing the configuration of a conventional example. FIG. 4 is a timing chart for explaining the operation of the conventional example. 1...Variable delay circuit, 7...Integrator, 8...Voltage controlled oscillator, 9...Horizontal synchronization signal separation circuit, 1
0... Extracting circuit, 23... Oscillator, 24... Counter, 25... Flip-flop, 26... Shift register, 28, 34 and 35... D flip-flop, 30, 31 and 32... Frequency divider,
40...Phase comparator.

Claims (1)

【実用新案登録請求の範囲】 (1) 可変遅延手段を備え、ビデオデイスクから
検出した複合映像信号のタイムベースエラーを検
出し、これが零に近づく方向に前記可変遅延手段
の遅延量を制御するビデオデイスク再生装置のタ
イムベース補正回路であつて、カラーバースト信
号周波数の2倍以上の周波数の発振を行なう発振
器と、前記可変遅延手段を通した前記複合映像信
号中の水平同期信号を受けて前記発振器の出力を
所定値まで計数することにより前記水平同期信号
の前縁からカラーバースト信号中にまで到る幅の
パルスを生成するパルス生成手段と、カラーバー
スト信号を毎水平走査期間毎に位相反転させる位
相反転手段と、前記パルス生成手段からの出力を
前記位相反転手段からの出力によりラツチするラ
ツチ手段と、前記発振器からの出力を分周して水
平同期信号の周波数にする分周手段と、前記ラツ
チ手段からの出力と前記分周手段からの出力とを
位相比較する位相比較手段とを備え、前記位相比
較手段からの位相比較出力に伴つて前記可変遅延
手段の遅延量を制御することを特徴とするビデオ
デイスク再生装置のタイムベース補正回路。 (2) 位相比較手段はカラーバースト信号が存在
する前後の期間で、かつカラーバースト信号が存
在する場合のみ位相比較動作を可能とする制御手
段を備えたことを特徴とする実用新案登録請求の
範囲第1項に記載のビデオデイスク再生装置のタ
イムベース補正回路。
[Claims for Utility Model Registration] (1) A video device comprising a variable delay means, which detects a time base error in a composite video signal detected from a video disk, and controls the amount of delay of the variable delay means in a direction in which the time base error approaches zero. The time base correction circuit of the disc playback device includes an oscillator that oscillates at a frequency that is at least twice the frequency of the color burst signal, and a horizontal synchronizing signal in the composite video signal that has passed through the variable delay means; pulse generating means for generating a pulse having a width ranging from the leading edge of the horizontal synchronizing signal to the color burst signal by counting the output of the horizontal synchronizing signal up to a predetermined value; and inverting the phase of the color burst signal every horizontal scanning period. a phase inversion means, a latching means for latching the output from the pulse generation means with an output from the phase inversion means, a frequency division means for dividing the output from the oscillator into a frequency of a horizontal synchronizing signal; It is characterized by comprising phase comparison means for comparing the phases of the output from the latch means and the output from the frequency dividing means, and controlling the delay amount of the variable delay means in accordance with the phase comparison output from the phase comparison means. A time base correction circuit for a video disc playback device. (2) The scope of the utility model registration claim, characterized in that the phase comparison means is equipped with a control means that enables the phase comparison operation only in the period before and after the presence of the color burst signal, and only when the color burst signal is present. A time base correction circuit for a video disc playback device according to item 1.
JP1987163752U 1987-10-28 1987-10-28 Time base correction circuit for video disc playback device Expired - Lifetime JPH0728787Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987163752U JPH0728787Y2 (en) 1987-10-28 1987-10-28 Time base correction circuit for video disc playback device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987163752U JPH0728787Y2 (en) 1987-10-28 1987-10-28 Time base correction circuit for video disc playback device

Publications (2)

Publication Number Publication Date
JPH0170483U true JPH0170483U (en) 1989-05-10
JPH0728787Y2 JPH0728787Y2 (en) 1995-06-28

Family

ID=31448756

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987163752U Expired - Lifetime JPH0728787Y2 (en) 1987-10-28 1987-10-28 Time base correction circuit for video disc playback device

Country Status (1)

Country Link
JP (1) JPH0728787Y2 (en)

Also Published As

Publication number Publication date
JPH0728787Y2 (en) 1995-06-28

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