JPH0290586U - - Google Patents
Info
- Publication number
- JPH0290586U JPH0290586U JP16826288U JP16826288U JPH0290586U JP H0290586 U JPH0290586 U JP H0290586U JP 16826288 U JP16826288 U JP 16826288U JP 16826288 U JP16826288 U JP 16826288U JP H0290586 U JPH0290586 U JP H0290586U
- Authority
- JP
- Japan
- Prior art keywords
- color burst
- output
- burst signal
- time base
- flop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002131 composite material Substances 0.000 claims 2
- 230000010355 oscillation Effects 0.000 claims 2
- 238000013459 approach Methods 0.000 claims 1
- 230000003111 delayed effect Effects 0.000 claims 1
- 238000001514 detection method Methods 0.000 claims 1
- 230000000630 rising effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Description
第１図はこの考案の一実施例の構成を示すブロ
ツク図。第２図はこの考案の一実施例の作用説明
に供するタイミング図。第３図は従来例の構成を
示すブロツク図。第４図は従来例の作用説明に供
するタイミング図。
１……可変遅延回路、９……水平同期信号分離
回路、１０……抽出回路、２３……発振器、２４
……カウンタ、２５……フリツプフロツプ、２６
，２７，２８，３５，３８，３９および４１……
Ｄフリツプフロツプ、３３……遅延回路、３６…
…シフトレジスタ、４２および４５……分周器、
４６……位相比較器、４７……積分器。
FIG. 1 is a block diagram showing the configuration of an embodiment of this invention. FIG. 2 is a timing chart for explaining the operation of one embodiment of this invention. FIG. 3 is a block diagram showing the configuration of a conventional example. FIG. 4 is a timing chart for explaining the operation of the conventional example. DESCRIPTION OF SYMBOLS 1... Variable delay circuit, 9... Horizontal synchronization signal separation circuit, 10... Extraction circuit, 23... Oscillator, 24
... Counter, 25 ... Flip-flop, 26
, 27, 28, 35, 38, 39 and 41...
D flip-flop, 33...Delay circuit, 36...
...shift register, 42 and 45...frequency divider,
46... Phase comparator, 47... Integrator.
Claims (1)
検出した複合映像信号のタイムベースエラーを検
出し、これが零に近ずく方向に前記可変遅延手段
の遅延量を制御するビデオデイスク再生装置のタ
イムベース補正回路であつて、カラーバースト信
号周波数の２倍以上の周波数で発振する発振器と
、可変遅延手段を通した複合映像信号中の水平同
期信号でセツトされるフリツプフロツプと、フリ
ツプフロツプのセツト出力を受けて発振器の発振
出力を計数してカラーバースト信号のほぼ中央位
置からカラーバースト信号周期の１／２およびカ
ラーバースト信号周期遅れた第１出力および第２
出力を発するカウンタと、カラーバースト信号の
立上りおよび立下りでフリツプフロツプのセツト
出力をラツチするＤフリツプフロツプと、トラツ
クジヤンプを検出した検出出力によりトラツクジ
ヤンプ毎にカウンタの第１出力と第２出力とを交
互に選択し、かつ選択した出力によりフリツプフ
ロツプをリセツトする選択手段と、発振器の発振
出力を分周して生成した基準水平同期信号とＤフ
リツプフロツプのラツチ出力とを位相比較する位
相比較手段とを備え、位相比較手段からの位相比
較出力に伴つて可変遅延手段の遅延量を制御する
ことを特徴とするビデオデイスク再生装置のタイ
ムベース補正回路。 (2) 請求項１項記載のタイムベース補正回路に
おいて、カラーバースト信号が存在することを検
出し、カラーバースト信号が存在するときのみ位
相比較手段への位相比較入力を供給する制御手段
を備えたことを特徴とするビデオデイスク再生装
置のタイムベース補正回路。[Claims for Utility Model Registration] (1) A variable delay device is provided, which detects a time base error in a composite video signal detected from a video disk, and controls the amount of delay of the variable delay device in a direction in which the time base error approaches zero. A time base correction circuit for a video disc playback device, which includes an oscillator that oscillates at a frequency that is more than twice the color burst signal frequency, and a flip-flop that is set by a horizontal synchronization signal in a composite video signal passed through a variable delay means. In response to the set output of the flip-flop, the oscillation output of the oscillator is counted, and the first and second outputs are delayed by 1/2 the color burst signal period and the color burst signal period from the approximately center position of the color burst signal.
A counter that generates an output, a D flip-flop that latches the set output of the flip-flop at the rising and falling edges of the color burst signal, and a detection output that detects a track jump that alternates the first and second outputs of the counter for each track jump. and a phase comparison means for comparing the phases of a reference horizontal synchronizing signal generated by dividing the oscillation output of the oscillator and the latch output of the D flip-flop, 1. A time base correction circuit for a video disc playback device, characterized in that the delay amount of a variable delay means is controlled in accordance with a phase comparison output from a phase comparison means. (2) The time base correction circuit according to claim 1, further comprising control means for detecting the presence of a color burst signal and supplying a phase comparison input to the phase comparison means only when a color burst signal is present. A time base correction circuit for a video disc playback device, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16826288U JPH0290586U (en) | 1988-12-28 | 1988-12-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16826288U JPH0290586U (en) | 1988-12-28 | 1988-12-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0290586U true JPH0290586U (en) | 1990-07-18 |
Family
ID=31457288
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16826288U Pending JPH0290586U (en) | 1988-12-28 | 1988-12-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0290586U (en) |
-
1988
- 1988-12-28 JP JP16826288U patent/JPH0290586U/ja active Pending
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