JPH0160857B2 - - Google Patents

Info

Publication number
JPH0160857B2
JPH0160857B2 JP58248422A JP24842283A JPH0160857B2 JP H0160857 B2 JPH0160857 B2 JP H0160857B2 JP 58248422 A JP58248422 A JP 58248422A JP 24842283 A JP24842283 A JP 24842283A JP H0160857 B2 JPH0160857 B2 JP H0160857B2
Authority
JP
Japan
Prior art keywords
shift
control data
shift control
mantissa
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58248422A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60142736A (ja
Inventor
Masayuki Ikeda
Koichi Ueda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58248422A priority Critical patent/JPS60142736A/ja
Priority to CA000468679A priority patent/CA1229415A/en
Priority to AU36270/84A priority patent/AU555230B2/en
Priority to ES538377A priority patent/ES8602270A1/es
Priority to EP84308518A priority patent/EP0145465B1/en
Priority to DE8484308518T priority patent/DE3481788D1/de
Priority to BR8406284A priority patent/BR8406284A/pt
Priority to KR1019840007775A priority patent/KR890004307B1/ko
Publication of JPS60142736A publication Critical patent/JPS60142736A/ja
Priority to US07/206,930 priority patent/US5016209A/en
Publication of JPH0160857B2 publication Critical patent/JPH0160857B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G06F7/485Adding; Subtracting
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49905Exception handling
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49936Normalisation mentioned as feature only

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Engineering & Computer Science (AREA)
JP58248422A 1983-12-09 1983-12-29 浮動小数点加減算方式 Granted JPS60142736A (ja)

Priority Applications (9)

Application Number Priority Date Filing Date Title
JP58248422A JPS60142736A (ja) 1983-12-29 1983-12-29 浮動小数点加減算方式
CA000468679A CA1229415A (en) 1983-12-09 1984-11-27 Floating-point addition/subtraction system
AU36270/84A AU555230B2 (en) 1983-12-09 1984-12-04 Floating-point addition/subtraction system
DE8484308518T DE3481788D1 (de) 1983-12-09 1984-12-07 Addier/substrahiersystem fuer gleitkommazahlen.
EP84308518A EP0145465B1 (en) 1983-12-09 1984-12-07 Floating-point addition/subtraction system
ES538377A ES8602270A1 (es) 1983-12-09 1984-12-07 Una instalacion electronica de suma-resta en punto flotante
BR8406284A BR8406284A (pt) 1983-12-09 1984-12-07 Sistema de adicao/subtracao com virgula flutuante para duas series de dados
KR1019840007775A KR890004307B1 (ko) 1983-12-09 1984-12-08 부동소수점 가감산 장치
US07/206,930 US5016209A (en) 1983-12-09 1988-05-31 Floating-point addition/subtraction system with digit position alignment between fractions of multiple sets of data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58248422A JPS60142736A (ja) 1983-12-29 1983-12-29 浮動小数点加減算方式

Publications (2)

Publication Number Publication Date
JPS60142736A JPS60142736A (ja) 1985-07-27
JPH0160857B2 true JPH0160857B2 (enrdf_load_stackoverflow) 1989-12-26

Family

ID=17177885

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58248422A Granted JPS60142736A (ja) 1983-12-09 1983-12-29 浮動小数点加減算方式

Country Status (1)

Country Link
JP (1) JPS60142736A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0792741B2 (ja) * 1988-11-04 1995-10-09 株式会社東芝 差動バレルシフタ

Also Published As

Publication number Publication date
JPS60142736A (ja) 1985-07-27

Similar Documents

Publication Publication Date Title
US5122981A (en) Floating point processor with high speed rounding circuit
EP0483864B1 (en) Hardware arrangement for floating-point addition and subtraction
US4999803A (en) Floating point arithmetic system and method
KR100241076B1 (ko) 조정및정규화클래스를구비한부동소수점승산및누산장치
US4758974A (en) Most significant digit location
US4719589A (en) Floating-point adder circuit
JP3345894B2 (ja) 浮動小数点乗算器
US5177703A (en) Division circuit using higher radices
US5016209A (en) Floating-point addition/subtraction system with digit position alignment between fractions of multiple sets of data
JP2511527B2 (ja) 浮動小数点演算器
JPH0160857B2 (enrdf_load_stackoverflow)
US5754458A (en) Trailing bit anticipator
JP2509279B2 (ja) 浮動小数点数一固定小数点数変換装置
JP2801472B2 (ja) 浮動小数点演算装置
EP0442220B1 (en) Decoder
JPH0367328A (ja) 浮動小数点演算装置
JP3137131B2 (ja) 浮動小数点乗算器及び乗算方法
JP2512939B2 (ja) 固定浮動デ−タ変換回路
JPH0377534B2 (enrdf_load_stackoverflow)
JPH05204606A (ja) 浮動小数点演算方式および装置
JP2931632B2 (ja) 桁移動装置及び浮動小数点演算装置
JP2622012B2 (ja) シフト回路
JPH03217938A (ja) 浮動小数点丸め正規化装置
JPH0427587B2 (enrdf_load_stackoverflow)
JPH04260122A (ja) 加減算高速桁合せ回路