JPH0156415B2 - - Google Patents

Info

Publication number
JPH0156415B2
JPH0156415B2 JP60200847A JP20084785A JPH0156415B2 JP H0156415 B2 JPH0156415 B2 JP H0156415B2 JP 60200847 A JP60200847 A JP 60200847A JP 20084785 A JP20084785 A JP 20084785A JP H0156415 B2 JPH0156415 B2 JP H0156415B2
Authority
JP
Japan
Prior art keywords
interrupt
processor
address
signal
common bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP60200847A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6261149A (ja
Inventor
Masataka Murata
Yoshikazu Kimura
Teruaki Takegawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
PFU Ltd
Original Assignee
PFU Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by PFU Ltd filed Critical PFU Ltd
Priority to JP60200847A priority Critical patent/JPS6261149A/ja
Publication of JPS6261149A publication Critical patent/JPS6261149A/ja
Publication of JPH0156415B2 publication Critical patent/JPH0156415B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)
  • Multi Processors (AREA)
JP60200847A 1985-09-11 1985-09-11 割り込み制御方式 Granted JPS6261149A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60200847A JPS6261149A (ja) 1985-09-11 1985-09-11 割り込み制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60200847A JPS6261149A (ja) 1985-09-11 1985-09-11 割り込み制御方式

Publications (2)

Publication Number Publication Date
JPS6261149A JPS6261149A (ja) 1987-03-17
JPH0156415B2 true JPH0156415B2 (ko) 1989-11-30

Family

ID=16431205

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60200847A Granted JPS6261149A (ja) 1985-09-11 1985-09-11 割り込み制御方式

Country Status (1)

Country Link
JP (1) JPS6261149A (ko)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2576899B2 (ja) * 1989-04-26 1997-01-29 セイコーエプソン株式会社 情報処理装置

Also Published As

Publication number Publication date
JPS6261149A (ja) 1987-03-17

Similar Documents

Publication Publication Date Title
US5608881A (en) Microcomputer system for accessing hierarchical buses
US5794067A (en) Digital signal processing device
EP0361176B1 (en) Method and apparatus for communicating data between multiple tasks in data processing systems
JPH0650493B2 (ja) データ処理装置
AU603876B2 (en) Multiple i/o bus virtual broadcast of programmed i/o instructions
JPH07104842B2 (ja) 外部記憶装置の割込み制御方式
US6026486A (en) General purpose processor having a variable bitwidth
KR100194850B1 (ko) 디지털 신호 처리 장치
US4152763A (en) Control system for central processing unit with plural execution units
US4837688A (en) Multi-channel shared resource processor
JPS62115542A (ja) 情報処理装置
US6223196B1 (en) Shared mac (multiply accumulate) system and method
US5642523A (en) Microprocessor with variable size register windowing
US6502182B1 (en) Digital signal processing device
JPH0156415B2 (ko)
JP2618223B2 (ja) シングルチツプマイクロコンピユータ
US4503498A (en) Multiprocessor cratecontroller
JP2585905B2 (ja) マルチタスク実行装置
JPS6097440A (ja) 仮想多重プロセツサ装置
JPH10171770A (ja) マルチプロセッサシステム
KR880001399B1 (ko) 정보 처리 장치
RU2101759C1 (ru) Вычислительное устройство с чередующимся обслуживанием нескольких командных потоков
JP2643116B2 (ja) 主記憶制御装置
JPH1091439A (ja) プロセッサ
KR930005843B1 (ko) 다중 프로세서 시스템의 다수의 서브 프로세서 제어방법