JPH0156415B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] A common bus type multiprocessor system is provided with a status determination circuit that determines that an access to the common bus is an interrupt vector reference cycle, and a state determination circuit that determines that an access to the common bus is an interrupt vector reference cycle. When the conversion control signal indicates an interrupt, the address line (original address ) by providing an address conversion mechanism to convert part or all of the address conversion instruction register, the interrupt address for each processor can be dynamically changed depending on the processor status, the contents of the address conversion instruction register, and external interrupt sources. ,
This allows each processor to generate its own interrupts.

[Industrial application field]

The present invention relates to an interrupt control method in a common bus type multiprocessor system.

With recent advances in computer technology, data processing in various fields has come to be performed by computers, and there is a demand for improvements in the processing power of these computer systems. In data processing in a communication control processing device (CCP), etc., by improving the efficiency of this interrupt processing, it is expected that the processing capacity of the communication control processing device (CCP) will be improved.

[Problems to be solved by conventional technology and invention]

In a multiprocessor system that shares memory using a common bus method, when an interrupt occurs, the contents of the shared memory at a specific address depending on the interrupt level are read, and each interrupt is processed according to that data (interrupt vector). In the case of a method that branches to processing, if multiple processors are connected, interrupt processing at the same level will
Since each processor reads the memory contents at the same address, conventional methods have solved this problem using the following method.

Divide interrupt levels for each processor. That is, the interrupt level used by one processor is made unavailable to other processors.

When each processor uses multiple interrupt sources at the same interrupt level, a display means is provided in the shared memory so that the processor can know what kind of interrupt it is. In the interrupt processing routine, the display means is searched to determine what kind of interrupt it is, and then the actual interrupt processing is started.

FIG. 4 is a diagram schematically showing the conventional interrupt control method, in which (a) shows the case where the interrupt level is assigned to each processor 1, that is, the above case, and (b) shows the common This shows a case in which an interrupt display register is provided on the shared memory on the bus 6 to display interrupt factors for each level.

In this case, there was a problem in that the number of interrupt levels that can be executed by each processor is reduced, making efficient interrupt processing difficult.

In this case, it is necessary for each processor to search for the interrupt factor display means (interrupt display register) provided on the shared memory, which causes a problem in that the interrupt processing speed decreases.

In view of the above conventional drawbacks, the present invention provides a multiprocessor system using a common bus, in which each processor connected to the common bus can independently use the interrupt level of the computer system, and when an interrupt occurs. The purpose is to provide a method for improving processing efficiency.

[Means for solving problems]

FIG. 1 is a principle block diagram of the interrupt control system of the present invention.

In the present invention, when an interrupt is accepted,
It has a function to branch to each interrupt processing routine using the contents of a specific address (vector) according to the interrupt level as an address, and a processor state information signal that can determine that it is the cycle in which processor 1 reads the interrupt vector. In a common bus type multiprocessor system that shares a memory space, the processor state information signal is decoded by the plurality of processors 1 making up the multiprocessor system, and an interrupt vector reference cycle is generated. Judging that,
a state determination circuit 2 for outputting a conversion control signal;
an address conversion mechanism 3 for converting part or all of the values of address lines output from the processors according to conversion control signals from the state determination circuit 2 and external interrupt factors for each processor; Select one of the processors 1 that make up the processor system, and
It is equipped with a common bus switching circuit (selector) 4 for passing address lines, data lines, and control lines from the processor 1 to the common bus 6, and is a register readable/writable by each processor 1, depending on its contents. , an address conversion instruction register 5 capable of outputting a conversion instruction signal to the address conversion mechanism 3 is provided, and the output signal (conversion control signal) of the status determination circuit 2 of each processor and the contents of the address conversion instruction register 5 are provided. (conversion instruction signal) and the above external interrupt factor (interrupt signal),
One of the interrupt vector addresses from each processor 1 is converted and sent to the common bus.

[Effect]

That is, according to the present invention, a common bus type multiprocessor system is provided with a status determination circuit that determines that an access to the common bus is an interrupt vector reference cycle, and conversion control from the status determination circuit is provided. When a signal indicates an interrupt, depending on the external interrupt source for each processor and the contents of the address conversion instruction register that can be read/written from each processor,
By providing an address conversion mechanism to convert part or all of the address line (original address) output from the processor, each processor can be Since the interrupt address for each processor is dynamically changed so that each processor can handle its own interrupt, it has the effect of reducing the amount of hardware, improving interrupt processing speed, and improving processing efficiency.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.
FIG. 2 is a diagram showing an embodiment of the address translation mechanism of the present invention, and FIG. 3 is a diagram showing a specific example of the address translation mechanism. Note that the same reference numerals indicate the same objects throughout the figures.

Hereinafter, an interrupt control system when the present invention is implemented will be explained with reference to FIGS. 2 and 3 while referring to the principle block diagram of FIG. 1.

First, when the status information signal in the processor 1 indicates that the cycle refers to an interrupt vector, the status determination circuit 2 sends a conversion control signal indicating an interrupt to the address conversion mechanism 3.

In the address conversion mechanism 3, by activating the demultiplexer 31 by the conversion control signal, the external interrupt factor input to the demultiplexer 31 at that time and the processor 1 can read and write. Based on the contents of the address conversion instruction register 5, address conversion signals 1 to n are output according to predetermined logical conditions, and part (or all) of the original address to the common bus 6 output from the processor 1 is output. ) is converted by the AND circuit 32 and sent to the common bus switching circuit 4.

Therefore, as is clear from the specific example in Figure 3,
Processor 1 also responds to the same interrupt cause.
For example, by changing the contents of the address conversion instruction register 5 using software means, the contents of the post-conversion addresses (AD07 to AD04) can be dynamically changed. It is understood that one can generate their own interrupt address.

That is, for the address translation mechanism 3 shown in FIG. 3a, interrupt signals 1,
2 is input, address conversion instruction register 5
Depending on the contents of bits 0 and 1, it is possible to generate the converted address shown in the truth table shown in FIG.

The converted address information and a control line and a data line (not shown) are sent to the common bus 6 in the common bus switching circuit 4 at the timing assigned to each processor 1. Activation for the interrupt processing will be executed in a time-sharing manner.

By implementing such interrupt processing, the following features can be obtained.

1) In a system that uses more interrupt sources than the number of interrupt levels possessed by processor 1, it usually has an interrupt cause display register, and the processor that accepts the interrupt reads the interrupt cause display register and analyzes the interrupt cause. However, by using the interrupt control method of the present invention, it is possible to vary the vector address depending on the interrupt factor, so the above interrupt factor register This eliminates the need for time spent on factor analysis, reducing the amount of hardware and improving processing speed.

2) When the processing content is different each time even if the interrupt is caused by the same cause, for example, in the case of timer interrupts, line interrupts, software interrupts, etc. in the communication control processing unit (CCP), the processing content for the next same interrupt may be determined in advance. Conventionally, the "next interrupt transition table" is checked during the interrupt handling routine, and after entering the interrupt, the contents of the table are read and the processing proceeds according to the table. However, in this method, the memory area where the processing start address for the next interrupt is written can be specified using the address conversion instruction register 5, so that processing is performed after the interrupt occurs. Not only can the processing time be shortened, but it is also effective in queue management through program control, and interrupt processing can be made more efficient.

3) Since this is a multiprocessor system and uses a shared memory system, there is a common bus switching circuit (selector) 4, and the switching timing is usually delayed from the address output timing of the processor, so the above address conversion is performed. The time delay caused by the mechanism is absorbed within the switching timing, and even if this system is introduced, there is no need to modify the operation timing.

〔Effect of the invention〕

As described above in detail, the interrupt control method of the present invention is provided in a common bus type multiprocessor system, and includes a state determination circuit that determines that an access to the common bus is an interrupt vector reference cycle. , when the conversion control signal from the status determination circuit indicates an interrupt, the output from the processor is determined by the external interrupt factor for each processor and the contents of the address conversion instruction register that can be read/written by each processor. By providing an address conversion mechanism for converting part or all of the address line (original address) to be processed, the interrupt address for each processor can be changed depending on the state of the processor, the contents of the address conversion instruction register, and external interrupt factors. Since this system dynamically changes the number of processors so that each processor can generate its own interrupts, it has the effect of reducing hardware requirements, increasing interrupt processing speed, and improving processing efficiency.

[Brief explanation of drawings]

FIG. 1 is a principle block diagram of the interrupt control system of the present invention, FIG. 2 is a diagram showing an embodiment of the address translation mechanism of the present invention, and FIG. 3 is a diagram showing a specific example of the address translation mechanism of the present invention. FIG. 4 is a diagram schematically showing a conventional interrupt control method. In the drawing, 1 is a processor, 2 is a state determination circuit, 3 is an address conversion mechanism, 31 is a demultiplexer, 4 is a common bus switching circuit (selector),
5 is an address conversion instruction register, 6 is a common bus,
are shown respectively.

Claims (1)

[Scope of Claims] 1. A function to branch to each interrupt processing routine using the contents (vector) of a specific address according to the interrupt level as an address when an interrupt is accepted, and a cycle in which the processor reads the interrupt vector. In a common bus type multiprocessor system that shares a memory space and has a processor state information signal that can determine that the processor state information is decode the signal,
Status determination circuit 2 for determining that it is an interrupt vector reference cycle and outputting a conversion control signal
and the conversion control signal from the state determination circuit 2 and external interrupt factors for each processor 1,
A part of the address line output from processor 1,
Or address translation mechanism 3 for converting all values.
and a common bus for selecting one of the processors 1 constituting the multiprocessor system and passing address lines, data lines, and control lines from each processor 1 to the common bus 6. an address conversion instruction register 5 which is equipped with a switching circuit (selector) 4 and is readable/writable by each processor 1 and is capable of outputting a conversion instruction signal to the address conversion mechanism 3 according to its contents; Based on the output signal (conversion control signal) of the state determination circuit 2 of each processor 1, the contents of the address conversion instruction register 5 (conversion instruction signal), and the external interrupt factor (interrupt signal), An interrupt control method characterized in that one of the interrupt vector addresses from the processor 1 is converted and sent to the common bus 6.