JPH1091439A - Processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve performance by using the processor of wide bit width as the plural processors of narrow bit width in accordance with purposes. SOLUTION: A control part 321 for 32 bit processor 320 receives an instruction from a memory and analyzes whether the instruction is for a 32 bit processor or a 16 bit processor. In the case of the former, the 32-bit processor 320 is controlled by using two 16 bit instruction control parts 1610 and 1611. In the case of the latter, the control part 321 outputs 16 bit processor mode signals to two 16 bit instruction control parts 1610 and 1611. The 16 bit instruction control parts 1610 and 1611 independently control the 32-bit processor 320 as the two divided 16 bit processors 1600 and 1601. Thus, appropriate bit width adjusted to the purposes is selected and the two different processings are operated in parallel to improve the performance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a processor, and more particularly, to a general-purpose processor which is required to perform various processes by one unit, dividing a data bit width into an optimum length for each process. In addition, the present invention relates to a device which can be changed so as to prevent redundancy and at the same time use the surplus bit width for other processing.

[0002]

2. Description of the Related Art In recent years, with the improvement of the processing capability of processors, it has been expected that a single high-performance processor can perform many processes. The processing performed by one processor covers a wide variety of areas, such as control of various devices and video / audio signal processing.

Here, a high-performance processor conventionally has a wide bit width. That is, the bit width is set wide so that the amount of data that can be processed can be increased.

[0004]

However, in the multimedia era in recent years, the types of data handled by a single processor include data that requires a wide bit width such as audio signal processing and image signal processing. There are various types of data such as processing and various controls that do not require a very wide bit width.

Therefore, at present, a processor to be used is selected in accordance with data having the widest bit width among data processed by one processor. As a result, processing is performed with a redundant bit width until processing of sufficient data with a bit width smaller than the bit width of the selected processor. For example, when sound signal processing is performed by a general-purpose processor, generally when processing with good sound quality is performed, 32
A bit processor is required. On the other hand, 16 bits are often sufficient for image signal processing, and 8 bits may be sufficient for simple control. Therefore, when the audio signal processing, the image signal processing, and the simple control are performed by one processor, the latter image signal processing and the simple control have a disadvantage that the processing is performed with a redundant bit width.

Therefore, conventionally, by parallelizing data, a plurality of data having a narrow bit width are simultaneously processed by a processor having a wide bit width to improve the processing capability. However, when it is necessary to perform sequential processing such as conditional branch processing, for example, a plurality of data cannot be parallelized, and no improvement in processing capacity can be expected. The use of the device leads to an increase in the cost of the entire device.

Under these circumstances, instead of one expensive processor, a number of processors equal to the number of processes are prepared, and the bit width of each processor is set to a bit width suitable for the corresponding process, thereby reducing cost. For example, it is necessary to use both a high-performance and inexpensive processor with a wide bit width for performing signal processing and the like and an inexpensive processor with a narrow bit width for performing sequential processing.
As a result, the number of parts is increased, which causes a drawback that the device becomes large.

[0008] An object of the present invention is to make it possible to change the bit width of a processor when a plurality of processes are processed by one processor, and to perform the plurality of processes with a bit width suitable for each process. And high performance.

In order to achieve the above object, the present invention provides a single processor having a wide bit width (for example, 32 bits),
If necessary, the configuration is such that the processor can be used as a plurality (for example, two) of processors having a narrow bit width (for example, 16 bits).

[0010]

In order to achieve the above object, the present invention is directed to an N-bit (N is a natural number) processor, comprising: an instruction for the N-bit processor; and N = M1 +... + Mn. (M1 and Mn are natural numbers, n is 2
A decoding unit that decodes n instructions for the Mn-bit processor satisfying the above natural numbers), and if the instruction decoded by the decoding unit is an instruction for the N-bit processor, decodes the instruction. An instruction control unit for an N-bit processor that controls the N-bit processor so as to execute the instruction;
If the instruction is for a bit processor, the N-bit processor is divided into n Mn bit processors, and the n Mn bit processors are controlled so that the n instructions are decoded and executed in parallel. and n instruction control units for Mn bit processors.

According to a second aspect of the present invention, in the processor of the first aspect, an instruction for the N-bit processor, an instruction for the n Mn-bit processors, and a specific instruction are separately stored. The decoding unit receives the three types of instructions, decodes the specific instruction, and receives an instruction after the specific instruction for the N-bit processor or the n instructions. It is characterized by determining whether the instruction is for an Mn bit processor.

According to a third aspect of the present invention, in the processor according to the second aspect, the specific instruction is a processor division instruction, and the decoding unit receives the division instruction,
It is characterized in that it is determined that an instruction received after the divided instruction is an instruction for n Mn bit processors.

According to a fourth aspect of the present invention, in the processor according to the second aspect, the specific instruction is a processor combination instruction, and the decoding unit receives the combination instruction,
It is characterized in that it is determined that an instruction received after the combined instruction is an instruction for an N-bit processor.

According to a fifth aspect of the present invention, in the processor according to the first aspect, when the decoded instruction is an instruction for the N-bit processor, the instruction control unit for the N-bit processor includes: The bit processor instructions are converted into n Mn bit format instructions executable by n Mn bit processors, and the converted n instructions are sent to the corresponding Mn bit processor instruction control units. , The execution of the instructions of the corresponding Mn bit format is controlled by the n Mn bit processor instruction control units.

According to a sixth aspect of the present invention, in the processor according to the first aspect, the N-bit processor is a 32-bit processor, and the n Mn-bit processors are two.
Characterized by 16 16-bit processors.

According to a seventh aspect of the present invention, in the processor of the first aspect, n Mn bit resources are provided corresponding to the n Mn bit processors, and the processor operates as the n Mn bit processors. At the time, each of the M
The instruction control unit for an n-bit processor, the corresponding Mn
When controlling the bit resources and operating as the N-bit processor, the N-bit processor instruction control unit controls the N-bit processor to combine the n Mn-bit resources to operate as the N-bit resource. Features.

The invention according to claim 8 is the processor according to claim 7, wherein the n resources are n Mn.
It is a bit arithmetic unit, n Mn bit memories, n Mn bit data registers, or n Mn bit program counters.

According to a ninth aspect of the present invention, in the processor according to the seventh aspect, the n resources are n stages of Mn-bit arithmetic units, and the N-bit processor instruction control unit includes the N-bit processor. When the operation is performed, a carry / borrow of the preceding Mn bit computing unit is sent to the next Mn bit computing unit to couple the n-stage Mn bit computing units.

According to a tenth aspect of the present invention, in the processor according to the third aspect, there are provided n program counters for each Mn-bit processor, wherein the processor division instruction is an N-bit format instruction, and Calculate the address of the instruction of the N-bit processor to be executed first after this processor division instruction, save the value, and include the n program counters for each of the Mn bit processors in the processor division instruction. It is an instruction to write an N-bit address for each Mn bit.

The invention according to claim 11 is the invention according to claim 10.
4. The processor according to claim 3, wherein the specific instruction includes a processor combination instruction, and the processor combination instruction stops the operation as the n Mn-bit processors and saves the N when executing the processor division instruction. The value of the bit program counter is restored.

According to a twelfth aspect of the present invention, in the processor according to the first aspect, a memory for storing the instructions for the N-bit processor and the instructions for n Mn-bit processors is provided. "0" of address
Address to (2 ＾ Mnmax−1) (＾ is a power, Mnm
ax represents the largest one of M1, M2,..., Mn) as a space for n Mn bit processors, and (2 ＾ Mnma) of the address of the memory space.
x) addresses to (2 @ N-1) are used as a space for an N-bit processor.

According to a thirteenth aspect of the present invention, there is provided the processor according to the third aspect, further comprising: n program counters for each Mn-bit processor; and (N−Mn) -bit page registers. The instruction is (N-
"1" is added to the value of the (Mn) -th bit, and the value of the higher (N-Mn) bit, which is the result of the addition, is written to the (N-Mn) -bit page register, and "n" is written to the n program counters. It is a command for writing 0 ".

The invention according to claim 14 is the invention according to claim 13.
In the processor described above, when operating as n Mn bit processors, the n Mn bit processor instruction control units each set the value of the (N-Mn) page register as an upper bit, and The Mn bit address of the "0" value of the counter is set as a lower bit, and an N-bit address including the upper bit and the lower bit is transmitted to a memory for storing instructions in advance.

According to a fifteenth aspect of the present invention, the above-mentioned fourteenth aspect
4. The processor according to claim 3, wherein the specific instruction includes a processor combination instruction output from a corresponding Mn bit processor instruction control unit when the n Mn bit processors complete processing. When the Mn bit processor finishes processing and the corresponding Mn bit processor instruction control unit outputs the processor combination instruction, the Mn bit instruction control unit keeps processing until another Mn bit processor finishes processing. Controlling the corresponding Mn bit processor to stop operation or execute an instruction that causes no state change.

The invention according to claim 16 is the invention according to claim 15.
In the processor described above, when all the Mn bit processors have completed the processing, the value of the (N-Mn) page register is set to the upper bit, and the value of the (N-Mn) page register corresponds to the instruction control unit for the Mn bit processor that last output the processor combination instruction. A value obtained by adding "1" to the value of the program counter is set as a lower bit, and an N-bit address including the upper bit and the lower bit is transmitted to a memory for storing instructions in advance.

According to a seventeenth aspect of the present invention, in the processor according to the first aspect, the plurality of instructions for the N-bit processor and the plurality of instructions for the Mn-bit processor are instructions having a variable word length. It is characterized by.

With the above arrangement, the invention according to claims 1 to 17 has the following effects. That is, in a process requiring a wide bit width, the processor is used as a processor that performs data processing of a wide bit width, and a process that requires a narrow bit width is used as a plurality of processors that perform data processing of a narrow bit width. Therefore, when the sequential processing is performed with a narrow bit width, the sequential processing is performed by one of the narrow bit width processors and the other narrow bit width processing is performed on the remaining narrow bit width. Can be performed in parallel by other processors.

[0028]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows an overall schematic configuration of the present embodiment. In the figure, 1600, 16
Reference numeral 01 denotes a 16-bit processor, and reference numerals 1610 and 1611 denote instruction control units (instruction control units for Mn-bit processors) of the 16-bit processor (hereinafter referred to as 16-bit instruction control units). 320 is a 32-bit processor including the two 16-bit processors, and 321 is the 3-bit processor.
It is a control unit of the 2-bit processor 320.

The 32-bit processor 320 is constructed by connecting the one 16-bit processor 1600 and the other 16-bit processor 1601 in a bit serial manner. The control unit 32 of the 32-bit processor 320
1 is the two 16-bit instruction control units 1610, 16
11 through the respective 16-bit processors 1600, 16
01 resources.

FIG. 2 shows the concept of the flow of program execution by the processor of FIG. In the figure, the programs are sequentially executed from top to bottom. In the figure, the processor initially operates as a 32-bit processor. A specific instruction “proc. When the "div" instruction (processor division instruction) is executed at the time indicated by the symbol A in the figure, thereafter, two instructions as a 16-bit processor are executed in parallel and independently by the two 16-bit processors 1600 and 1601 respectively. Is done.

Thereafter, when one of the 16-bit processors (for example, 1600) completes the execution of the process, the 16-bit processor 1600 at the time indicated by the symbol B, a specific instruction “proc.con” instruction (processor combination instruction) And then the other 16-bit processor 1
The operation is stopped until the processing of step 601 is completed, or an instruction that causes no state change (for example, a NOP instruction) is executed. This “proc.con” instruction may be defined as an instruction that waits until the other 16-bit processor 1601 completes processing and issues the “proc.con” instruction at the point of symbol C in the figure. Good. Hereinafter, the description will be made assuming that the NOP instruction is executed.

FIG. 3 shows a more specific circuit configuration diagram of the processor of the present embodiment. In the figure, reference numeral 110 denotes an arithmetic logic unit of higher 16 bits (Mn bit operator), 1
Numeral 11 denotes an arithmetic logic unit of lower 16 bits (Mn bit arithmetic unit), and 112 denotes an arithmetic and logic unit of lower 16 bits (hereinafter referred to as ALU) 111 to A of upper 16 bits.
Carry / borrow to the LU 110; 162, a data combiner for transmitting the carry / borrow; 120 to 125, 16-bit data registers (Mn bit data registers); 130, 131, 16-bit × 4 gigaword memories; It functions as a storage medium for storing the program of FIG. 2 in advance. The control unit 321 of the 32-bit processor 320 includes a decryption unit 322 and a 32-bit instruction control unit 323 (N-bit processor instruction control unit). Reference numeral 150 denotes a memory management unit (hereinafter, referred to as an MMU).

In FIG. 3, a 16-bit instruction control unit 16
10 and 1611 output address and control information for the memories 130 and 131 to the MMU 150, respectively.
50 outputs address and control information to the memories 130 and 131 according to the received address and control information.

The decoding unit 322 of the 32-bit processor 320 decodes whether the currently executed instruction is for a 32-bit processor or a 16-bit processor, and outputs processor mode signals 3220, 3221 and 3221.
222 is output. The processor mode signal 322
0 and 3221 are the 16-bit instruction control unit 16 respectively.
10, 1611. Further, the remaining processor mode signal 3222 becomes the 32-bit processor mode only when both of the two processor mode signals 3220 and 3221 are in the 32-bit processor mode.
The data is output to the data combining unit 162.

When the processor mode signal 3222 indicates the 32-bit processor mode, the 32-bit instruction control unit 323 of the 32-bit processor 320 converts the instructions read from the memories 130 and 131 into 16-bit instructions. The instruction is converted into a 16-bit processor instruction format that can be decoded by the instruction control units 1610 and 1611. At this time, if the instruction formats of the 32-bit processor and the 16-bit processor are unified, and the specifications are different only in the data width of the argument, the format conversion becomes easy. FIGS. 13 and 14 show a specific example of converting the format of a 32-bit processor instruction into a 16-bit processor instruction.

FIG. 13 shows an instruction of "load 0h05070799, Ra" as an example of using a memory as an argument. This 32-bit instruction is stored in memory 0h050
This is an instruction to read data at address 70799 into the register Ra. The 32-bit instruction control unit 323 converts “4050707991 (hexadecimal)” into “405071” and “407991” as shown in FIG.
“Load 0h0507, Ra” and “load 0h0507, Ra”
h0799, Ra "are converted to two 1-bit instructions.
6-bit processors 1600 and 1601 are executed.
The actual addressing to the memory will be described later.

FIG. 14 shows an instruction "add Ra, Rb, Rc" as an example of using only registers as arguments. This 32-bit instruction executes Ra + Rb,
This is an instruction to be stored in the register Rc. The 32-bit instruction control unit 323 changes “1123” to “1” as shown in FIG.
123 ”and“ 1123 ”(in this example, 32
Since the instruction format is unified between the bit processor and the 16-bit processor, there is no need for conversion.)
The two 16-bit instructions “add Ra, Rb, Rc” and “add Ra, Rb, Rc” are executed by the two 16-bit processors 1600 and 1601.

Further, the 32-bit instruction control unit 323
Is a 16-bit NOP when the processor mode signal 3222 indicates a 16-bit processor mode.
Instructions are 16 bit format instructions 3230, 3231
This is referred to as the 16-bit instruction control units 1610, 16
11 is output.

In addition, the 32-bit instruction control unit 323
Is the instruction word length 321 in the 32-bit processor mode.
3 is output to the lower 16-bit instruction control unit 1611.

Next, each of the 16-bit instruction control units 161
0 and 1611 are shown in FIG. In the figure,
When the processor mode signals 3220 and 3221 received from the 32-bit instruction control unit 323 are in the 32-bit processor mode, the instructions output from the 32-bit instruction control unit 323, ie, the 16-bit instruction control units 1610 and 1611, Instructions 3230 and 3231 obtained by converting a 32-bit format instruction to a 16-bit format are analyzed.
21 is in the 16-bit processor mode, the instructions in the 16-bit format output from the memories 130 and 131 are directly analyzed, and the resources (processor 16
00 indicates the ALU 110, the memory 130, and the registers 120, 122, and 124. In the processor 1601, the ALU 111, the memory 131, and the register 121.
123, 125).

The data combiner 162 receives the processor mode signal 322 from the 32-bit instruction controller 323.
2 is 32-bit processor mode, lower AL
Carry / Borrow 11 from U111 to upper ALU110
2 is sent, while in the case of the 16-bit processor mode, “0” is selected and sent to the upper ALU 110.

Next, how the 32-bit instruction control unit 323 specifically controls the flow of the division and combination of the processors shown in FIG. 2 will be described with reference to FIG.

In FIG. 15, first, the 32-bit processor 320 itself is reset. As a result, the decoding unit 322 outputs all processor mode signals 3220 and 322.
1 and 3222 are set to the 32-bit processor mode. Further, the 32-bit instruction control unit 323 includes a memory 130,
The instructions in the 32-bit format read from 131 are converted into two 16-bit instructions 3230 and 32
Convert to 31. Each 16-bit instruction control unit 1610, 1
611 receives the corresponding instruction of the 16-bit format and receives the corresponding 16-bit processor 1600, 160
1 to execute the received instruction.

Next, when the “proc.div” instruction is issued, the decryption unit 322 causes the all processor mode signals 32
20, 3221, and 3222 are set to the 16-bit processor mode. In addition, the 32-bit instruction control unit 323
The bit format NOP instruction is output to two 16-bit instruction control units 1610 and 1611, respectively. But,
Since the corresponding processor mode signals 3220 and 3221 are in the 16-bit processor mode, the respective 16-bit instruction control units 1610 and 1611
The instructions in the 16-bit format output from 0 and 131 are directly analyzed, and the instructions are executed by the corresponding 16-bit processors 1600 and 1611.

Thereafter, at the point indicated by the reference numeral B in FIG.
When the bit processor 1600 issues the “proc.con” instruction, the decoding unit 322 outputs the processor mode signal 3220 for the 16-bit processor 1600 to 32.
Switch to bit processor mode. The processor mode signal 3221 for the 16-bit processor 1601 is 16
Hold in bit processor mode. Therefore, the processor mode signal 3222 also holds the 16-bit processor mode. The 32-bit instruction control unit 323 transmits a 16-bit format NOP instruction to both 16-bit instruction control units 1.
610 and 1611 are output. In the 16-bit instruction control unit 1610 to which the “proc.con” instruction has been issued, the received processor mode signal 3220 is in the 32-bit processor mode.
Execute the NOP instruction in 16-bit format from 3. On the other hand, the remaining 16-bit instruction control unit 1611 directly analyzes the 16-bit format instruction output from the corresponding memory 131 because the received processor mode signal 3221 is in the 16-bit processor mode, and This is executed by the bit processor 1611.

Further, when the 16-bit processor 1601 issues a “proc.con” instruction at the time point C in FIG. 2, the decryption unit 322 causes the 16-bit instruction control unit 161
The processor mode signal 3221 for 1 is set to the 32-bit processor mode. Accordingly, the processor mode signal 3222 is also in the 32-bit processor mode. 32
The bit instruction control unit 323 converts a 32-bit format instruction read from each of the memories 130 and 131 into two 16-bit format instructions 3230 and 3231. 16-bit instruction control units 1610 and 1611
Since the received processor mode signals 3220 and 3221 are in the 32-bit processor mode, the instruction 3 in the 16-bit format from the 32-bit instruction control unit 323
230, 3231, respectively, decode this instruction and execute it in the corresponding 16-bit processor 1600, 1611. At this time, the data combination unit 162
Sends carry / borrow 112 to upper ALU 110.

With the above flow, the 16-bit processor mode and the 32-bit processor mode change.

In this embodiment, 3 is reset by reset.
Although an example in which the mode is the 2-bit processor mode has been described, the mode may be set so as to be the 16-bit processor mode.

With the above configuration, when operating as one 32-bit processor 320, the processor division instruction "proc. div ", then a processor is realized in which the 32-bit processor 320 can operate as two independent 16-bit processors 1600 and 1601.

Next, a configuration for generating addresses for the two memories 130 and 131 will be described below with reference to the configuration of the 16-bit instruction control unit shown in FIG.

In this embodiment, the address “0h000000” is used as the memory area of the 16-bit processor.
00 ”to“ 0h0000ffff ”(note that the first“ 0h0000ffff ”
h "indicates that the following number is in hexadecimal notation), and addresses" 0h00010000 "to" 0hff "are used as a memory area of the 32-bit processor.
ffffff ”.

In FIG. 4, reference numerals 1401 and 1411 denote program counters (Mn bit program counters),
1402 and 1412 are adders, 1403 and 1413
Is an instruction analysis unit for a 16-bit processor, 1410 is a carry from the adder 1412 to the adder 1402, 140 is
4, 1414, 1405, 1415, 1406, 141
6, 1407 and 1417 are multiplexers.

The 32-bit instruction control unit 323 transmits the processor mode signal 3211 to each of the instruction analysis units 1403 and 1413 and the multiplexer 1 of the 16-bit processor.
404, 1414, 1407, and 1417, and outputs the corresponding 16-bit format instructions 3230 and 3231 in the 32-bit processor mode to the multiplexers 1407 and 1417, respectively. The length 3213 is output to the multiplexer 1414 of the 16-bit instruction control unit 1611.

The multiplexers 1407 and 1417 are
In the 2-bit processor mode, corresponding 16-bit instructions 3230 and 3231 from the 32-bit instruction control unit 323 are selected. In the 16-bit processor mode, 16-bit instructions from the corresponding memories 130 and 131 are selected.
An instruction in a bit format is selected and output to the instruction analyzers 1403 and 1413, respectively.

The multiplexer 1404 selects “0” in the 32-bit processor mode, and selects the instruction word length from the instruction analysis unit 1403 in the 16-bit processor mode, and outputs it to the adder 1402.

The multiplexer 1414 selects the instruction word length 3213 of the 32-bit format from the 32-bit instruction control unit 323 in the 32-bit processor mode, and selects the instruction analysis unit 1 in the 16-bit processor mode.
The instruction word length from 413 is selected and output to the adder 1412.

Data combiner 162 selects the carry from adder 1412 in the 32-bit processor mode and “0” in the 16-bit processor mode.
Is selected and output to the adder 1402.

The instruction analysis units 1403 and 1413 analyze the instructions output from the corresponding multiplexers 1407 and 1417, respectively, and
Resources and built-in resources (multiplexer 140
5, 1406, 1415, 1416 and memory 130,
131), and in the 16-bit processor mode, outputs the instruction word length in the 16-bit format in this mode to the corresponding multiplexers 1404 and 1414.

Further, each of the instruction analyzers 1403, 141
3 are multiplexers 1405, 1415, 14 respectively
06 and 1416 are controlled. The former multiplexer 14
Regarding the control of steps 05 and 1415, if a program branch is necessary (for example, in the case of a branch instruction, a conditional branch instruction, a subroutine branch / return instruction, a loop instruction, a processor division instruction, etc.), its own instruction analysis unit 1403 , 14
13 is selected, and the other outputs are selected by the adders 1402, 1
412 is selected and output to the corresponding program counters 1401 and 1411. Regarding the control of the multiplexers 1406 and 1416, in the phase of reading out the instruction from the memory, the value of the corresponding program counter 1401 or 1411 is selected, and if the address is described in the program while the instruction is being executed, the instruction is executed. In the case of register indirect (that is, the value stored in the register is used as an address), the values from the processors 1600 and 1601 are selected and output to the MMU 150, respectively. Let it.

The adder 1402 adds the output of the data combining unit 162, the output of the multiplexer 1404, and the output of the program counter 1401, and outputs the addition result to the multiplexer 1405. Further, the adder 14
12 adds the output of the multiplexer 1414 and the output of the program counter 1411, and outputs the addition result to the multiplexer 1415. That is, in the 16-bit processor mode, the word length of the currently analyzed instruction is added to the address of the currently analyzed instruction (that is, the value of each of the program counters 1401 and 1411) to generate the address of the next instruction. On the other hand, in the 32-bit processor mode, the value of the program counter 1401 is set to the upper 16 bits, and the value of the program counter 1411 is set to the lower 16 bits. The word length of the middle instruction (ie, the instruction word length 32 in 32-bit format)
13) to generate the address of the next instruction.

FIG. 5 shows the internal configuration of the MMU 150 shown in FIG. In the figure, the MMU 150 has two selectors 1502, 1503, an address from two 16-bit instruction control units 1610, 1611, and a processor mode signal 32 from a decoding unit 322.
22 is input.

In the MMU 150, the selector 1502 selects an address from the upper 16-bit instruction control unit 1610 in the 32-bit processor mode, and selects and outputs “0” in the 16-bit processor mode. The selector 1503 controls the lower 16-bit instruction control unit 16 in the 32-bit processor mode.
In the 16-bit processor mode, the address from the upper 16-bit instruction control unit 1610 is selected and output. The address to the memory 130 is generated by using the upper 16 bits as the output of the selector 1502 and the lower 16 bits as the output of the selector 1503. In addition, the address to the memory 131 uses the upper 16 bits as the selector 1502.
And the lower 16 bits are used as the address from the lower 16-bit instruction control unit 1611.

FIG. 6 shows the operation of the processor split / join instruction. In the figure, a program of instructions of a 32-bit processor follows, and a processor division instruction (“proc.div 0h00100101”) of a 32-bit format is used.
Is issued, the instruction “load 0h05” to be executed by the 32-bit processor next to the divided instruction is issued.
070800, Rb ", that is, 16
Calculate the address of the instruction to be executed first when the bit processor mode is restored to the 32-bit processor mode, save this address on the stack, and then
The upper 16 bits of the argument of the division instruction are written to the program counter 1401, and the lower 16 bits of the argument are written to the program counter 1411.

When the mode shifts to the 16-bit processor mode as described above, each of the 16-bit processors has the address “0h00000010” and “0h00000010”.
1], and operate independently to perform processing. When both the 16-bit processors finish processing and issue a processor combination instruction (“proc.con” instruction),
32 to be executed next saved in the stack
The address of the bit processor instruction is stored in the program counter, and the process returns to the execution of the 32-bit processor instruction.

FIG. 7 shows the memories 130 and 13 of this embodiment.
1 shows the assignment of address 1. The flow of the program is shown by arrows in FIG. FIG. 8 shows the flow of a program according to the present embodiment in chronological order.

(Second Embodiment) Next, a second embodiment of the present invention will be described.
An embodiment will be described. In the present embodiment, the memory 13
Another configuration for generating addresses to 0 and 131 is shown.

In the first embodiment, in the 16-bit processor mode, the 16-bit processor operates at addresses "0h000000000" to "0h0000ffff".
Can use only the memory area. That is, if the processing to be used in the 16-bit processor mode requires an address area larger than this, the processing becomes impossible. The present embodiment avoids this problem. Also, processing in the 16-bit processor mode is performed at the address “0h00000”.
In the case where the area of “000” to “0h0000ffff” is sufficient, the present embodiment is significant in the sense of increasing the degree of freedom in allocating the program area.

FIG. 9 is a block diagram of each 16-bit instruction control unit 161.
0, 1611 are shown. In the figure, 1401 and 1411 are program counters, 1402 and 141
2 is an adder, 1409 and 1419 are instruction analyzers for a 16-bit processor, and 1410 is a carry from the adder 1412 to the adder 1402.

The construction and operation of the 32-bit instruction control unit 323, multiplexers 1407, 1417, 1404, 1414 and data combining unit 162 are the same as those in FIG.

Instruction analysis unit 14 of each 16-bit processor
09 and 1419 are multiplexers 1407 and 1417
Analyzes the instruction output from the 16-bit processor 1
600, 1601 resources and multiplexer 140
8, 1406, 1418, 1416 and memory 130,
131, and in the 16-bit processor mode, the word length of the instruction is
414.

The instruction analyzing unit 1409 of the 16-bit instruction control unit 1610 determines that when the processor 1600 of itself issues a processor combination instruction (“proc.connect instruction”), it issues the issuance of the other 16-bit instruction control unit 161.
1 to the instruction analyzing unit 1419. Further, the instruction analysis unit 1409 controls the multiplexer 1408 to
If a program branch is needed (eg, a branch instruction,
In the case of a conditional branch instruction, a subroutine branch / return instruction, a loop instruction, etc.), the output of its own instruction analysis unit 1409 is selected, and the processor combination instruction (proc.con, p
rc. In the case of (connect), the value of the page register (to be described later) 1501 is selected, and the output of the adder 1402 is selected otherwise, and the program counter 1401 outputs each. In the case of a processor division instruction (“proc.div” instruction), the program counter 1401 is reset.

The instruction analysis unit 1419 of the other 16-bit processor 1601 controls the multiplexer 1418 so that the instruction analysis unit 1
419 is selected, and the one 16-bit processor 1600 selects a processor combination instruction (“proc.
nect ”instruction), the adder 140
A value of 2 is selected, and otherwise, the output of the adder 1412 is selected, and each is output to the program counter 1411. In addition, the processor division instruction (“proc.
div ”instruction), the program counter 141
Reset 1

The control of the multiplexers 1406 and 1416 is the same as in FIG. The adder 14
02 is the same as that of FIG.

FIG. 10 shows an MMU 150 'according to this embodiment.
Is shown. The MMU 150 'in FIG.
03, 1504, 16-bit page register 150
A 1 and a +1 adder 1505,
The addresses from the 16-bit instruction control units 1610 and 1611, the output of the program counter 1401 in the higher-order 16-bit instruction control unit 1610, and the processor mode signal 3222 from the 32-bit instruction control unit 323 are input.

In the MMU 150 'of FIG. 10, the selector 1504 selects the address from the upper 16-bit instruction control unit 1610 in the 32-bit processor mode determined from the processor mode signal 3222. The value of the page register 1501 is selected and output. The other selector 1503 selects an address from the lower 16-bit instruction control unit 1611 in the 32-bit processor mode, and selects an address from the upper 16-bit instruction control unit 1610 in the 16-bit processor mode. And output. The address to the memory 130 is the upper 16
By setting the bits as the output of the selector 1504 and the lower 16 bits as the output of the selector 1503,
Generated. The address to the memory 131 uses the upper 16 bits as the output of the selector 1504 and outputs the lower 1 bit.
It is generated by using 6 bits as the address from the lower 16-bit instruction control unit 1611.

FIG. 11 shows the operation of the processor of the present embodiment at the time of a split / join instruction. FIG. 12 shows the address assignment of the memories 130 and 131 according to the present embodiment, and the flow of the program is indicated by arrows.

In FIG. 11, an instruction program of a 32-bit processor follows first, followed by a processor division instruction (“proc.div” instruction, which is an address “0h01a2c70f” or “0h134007” in FIG. 12).
77) is issued, then +
"1" is added to the value of the program counter 1401 by the 1 adder 1505, and the addition result (that is, "0h01a
3 "or" 0h1341 ") in the page register 1501.
And program counters 1401, 14
“0” is written to 11.

When the mode shifts to the 16-bit processor mode as described above, thereafter, each of the 16-bit processors 1600 and 1601 stores the corresponding address “0h01a”.
30,000 ”and“ 0h13410000 ”
Each of them operates independently and executes a 16-bit format instruction.

Thereafter, each 16-bit processor 160
When the processes 0 and 1601 are completed, each processor issues a processor combination instruction. At this time, the processor combination instruction issued by the processor that has used a large amount of the memory area is referred to as “proc. A “connect” instruction, and the processor combination instruction issued by the processor with the smaller used area is “proc. con ”instruction.
[Proc. 16 on the side that issued the "connect" instruction
The value of the program counter of the bit processor (the program counter 1411 in the case of the symbol A in FIG. 12 and the program counter 1401 in the case of the symbol B in FIG.
A value obtained by adding the instruction word length of the “connect” instruction (“1” in the case of the present embodiment) to the program counter 1411
And the value of the page register 1501 is stored in the program counter 1401, and the process returns to the instruction of the 32-bit processor.

In this case, a point to be noted is that
In 16-bit processor mode, the lower 1 address
The point is that the area of 6 bits “0hffff” may not be used. The reason is that when "1" is added to "0hffff", a carry occurs in the upper 16 bits, and "1" must be added to the value of the page register 1501.

In the above description, the memories 130 and 13
Although the plurality of instructions stored in 1 are variable lengths in which the word lengths of the instructions are different from each other, it is needless to say that the same fixed instruction length may be used. When the instruction word length is fixed,
Instruction word length 3 output from 32-bit instruction control unit 323
213 can be omitted.

[0083]

As described above, according to the processors of the first to seventeenth aspects, the processor is appropriately used as one processor having a wide bit width or a plurality of processors having a narrow bit width. For processing that requires a width, the processor is used as a wide bit width processor. On the other hand, when performing sequential processing with a narrow bit width, one of the narrow bit width processors performs the sequential processing. On the other hand, the remaining narrow-bit-width processors can perform other narrow-bit-width processes in parallel, thereby improving the performance of the processors.

[Brief description of the drawings]

FIG. 1 is a diagram showing an overall schematic configuration of a processor according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a flow of processing of a processor of the embodiment.

FIG. 3 shows two 1s constituting the processor of the embodiment.
FIG. 3 is a diagram illustrating an internal configuration of a 6-bit processor.

FIG. 4 is a diagram showing an internal configuration of two 16-bit instruction control units of the embodiment.

FIG. 5 is a diagram showing a configuration of a memory management unit according to the embodiment.

FIG. 6 is a diagram showing a processing flow at the time of a divided instruction and a combined instruction of the processor of the embodiment.

FIG. 7 is a diagram showing address allocation in a memory included in the processor of the embodiment.

FIG. 8 is a diagram showing a flow of a program according to the embodiment.

FIG. 9 is a diagram showing an internal configuration of two 16-bit instruction control units according to the second embodiment of the present invention.

FIG. 10 is a diagram showing a configuration of a memory management unit according to the embodiment.

FIG. 11 is a diagram showing a processing flow at the time of a division instruction and at the time of a combination instruction of the processor of the embodiment.

FIG. 12 is a diagram showing address allocation in a memory included in the processor of the embodiment.

FIG. 13 is a diagram showing a specific example of converting a 32-bit format instruction to a 16-bit format instruction.

FIG. 14 is a diagram showing another specific example.

FIG. 15 is a flowchart illustrating an example of the operation of a 32-bit instruction control unit.

[Explanation of symbols]

110, 111 ALU (Mn bit arithmetic unit) 120-125 Data register (Mn bit data register) 130, 131 Memory 150, 150 'Memory management unit (MMU) 162 Data combining unit 320 32-bit processor (N-bit processor) 321 control Unit 323 32-bit instruction control unit (N-bit processor instruction control unit) 1401, 1411 Program counter (Mn-bit program counter) 1402, 1412 Adder 1403, 1413 Instruction analysis unit 1409, 1419 Instruction analysis unit 1501 Page register 1600, 1601 16-bit processor (Mn-bit processor) 1610, 1611 16-bit instruction control unit (Mn-bit processor instruction control unit)

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI G06F 15/78 510 G06F 15/78 510G

Claims (17)

[Claims] 1. An N-bit (N is a natural number) processor, comprising: an instruction for the N-bit processor; and N = M1 +... + M
a decoding unit that decodes n instructions for Mn bit processors that satisfy n (M1, Mn are natural numbers, n is a natural number of 2 or more); and an instruction decoded by the decoding unit is an instruction for the N-bit processor. In the case of, an instruction control unit for an N-bit processor that controls the N-bit processor so as to decode and execute the instruction; and an instruction decoded by the decoding unit is an instruction for the n Mn-bit processors. In the case of the above, the N-bit processor is a Mn-bit processor divided into n pieces,
A processor comprising: n Mn bit processor instruction control units for controlling the n Mn bit processors so as to decode and execute the n instructions in parallel. 2. A memory for storing an instruction for the N-bit processor, instructions for the n Mn-bit processors, and a specific instruction, wherein the decoding unit includes the three types of instructions. And decodes the specific instruction, and the instruction received after the specific instruction
2. The processor according to claim 1, wherein it is determined whether the instruction is for a bit processor or for the n Mn bit processors. 3. The specific instruction is a processor division instruction, and the decoding unit receives the division instruction and determines that an instruction received after the division instruction is an instruction for n Mn-bit processors. The processor of claim 2, wherein 4. The specific instruction is a processor combination instruction, and the decoding unit receives the combination instruction and determines that an instruction received after the combination instruction is an instruction for an N-bit processor. 3. The processor according to claim 2, wherein: 5. When the decoded instruction is an instruction for the N-bit processor, the N-bit processor instruction control unit executes the N-bit processor instruction by n Mn-bit processors. The instructions are converted into n possible Mn bit format instructions, and the converted n instructions are sent to the corresponding Mn bit processor instruction control units, respectively.
The processor of claim 1, wherein the processor controls execution of a corresponding Mn bit format instruction. 6. The processor according to claim 1, wherein the N-bit processor is a 32-bit processor, and the n Mn-bit processors are two 16-bit processors. 7. An Mn-bit processor comprising n Mn-bit resources corresponding to the n-Mn-bit processors, and when operating as the n-Mn-bit processors, each of the Mn-bit-processor instruction controllers comprises: When controlling the corresponding Mn bit resource and operating as the N bit processor, the N
2. The processor according to claim 1, wherein the bit processor instruction control unit controls the n number of Mn bit resources to be combined to operate as an N bit resource. 8. The n resources are: n Mn bit operators, n Mn bit memories, n
8. The processor according to claim 7, wherein the processor comprises Mn bit data registers or n Mn bit program counters. 9. The n-bit resource is an n-stage Mn-bit operation unit, and the N-bit processor instruction control unit operates at the preceding stage when operating as the N-bit processor.
8. The processor according to claim 7, further comprising a data combining unit that sends the carry / borrow of the bit arithmetic unit to the next stage Mn bit arithmetic unit and connects the n stages of Mn bit arithmetic units. 10. An n-bit processor having n program counters for each Mn-bit processor, wherein the processor division instruction is an instruction in an N-bit format, and an N-bit processor which executes first after the processor division instruction. An instruction address is calculated, the value is saved, and an N-bit address included in the processor division instruction is written into the n program counters for each of the Mn-bit processors by Mn bits. The processor according to claim 3, wherein 11. The specific instruction also includes a processor combination instruction, wherein the processor combination instruction stops operating as the n Mn-bit processors and saves the N when executing the processor division instruction.
The processor according to claim 10, wherein the value of the bit program counter is restored. 12. An instruction for said N-bit processor,
and a memory for storing instructions for n Mn-bit processors, and addresses “0” to (2 ＾ Mnm) of addresses in the memory space.
ax-1) (＾ is a power, Mnmax is M1, M2,
.. Represents the largest one of Mn) up to n Mn
It is used as a space for a bit processor, and addresses (2 ＾ Mnmax) of addresses in the memory space
2. The processor according to claim 1, wherein the address (2 @ N-1) is used as a space for an N-bit processor. 13. An n-bit program counter for each Mn-bit processor, and a (N−Mn) -bit page register, wherein the processor division instruction includes: N
-1) is added to the value of the (Mn) -th bit, and the value of the upper (N-Mn) -bit, which is the result of the addition, is written to the (N-Mn) -bit page register, and is added to the n program counters. 4. The processor according to claim 3, wherein the instruction is a command for writing "0". 14. When operating as n Mn bit processors, each of the n Mn bit processor instruction control units sets the value of the (N-Mn) page register as an upper bit, and Mn of "0" value of counter
14. The processor according to claim 13, wherein the bit address is a lower bit, and an N-bit address obtained by combining the upper bit and the lower bit is transmitted to a memory for storing an instruction in advance. 15. The specific instruction includes the n Mn
M corresponding to when each bit processor completes processing
A processor combination instruction output from the n-bit processor instruction control unit is included, and one of the Mn bit processors terminates processing,
When the corresponding Mn-bit processor instruction control unit outputs the processor combination instruction, the Mn-bit instruction control unit stops operation or causes any state change until another Mn-bit processor finishes processing. 15. The processor of claim 14, wherein a corresponding Mn bit processor is controlled to execute the missing instruction. 16. When all the Mn bit processors have completed the processing, the value of the (N-Mn) page register is set to the upper bit, and the MN bit processor instruction control unit that last output the processor combination instruction is provided. A value obtained by adding "1" to the value of the program counter is set as a lower bit, and an N-bit address including the upper bit and the lower bit is transmitted to a memory for storing instructions in advance. A processor according to claim 15, 17. The instructions for the plurality of N-bit processors and the instructions for the plurality of Mn-bit processors,
The processor of claim 1, wherein the instruction is a variable word length instruction.