JPH10143494A - Single-instruction plural-data processing for which scalar/vector operation is combined - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the efficiency and speed of a program at the time of applying multi-media by providing a vector register or a scalar register as an operand and parallelly operating the multiple data elements of the vector register so as to improve calculation ability. SOLUTION: A multi-media processor 100 is provided with a processing core 105 provided with a general purpose processor 110 and a vector processor 120. The processing core 105 is connected to the remaining of the multi-media processor 100 through a cache sub system 130 provided with SRAMs 160 and 190, a ROM 170 and a cache control 180. The processor 100 is realized by using a general purpose processor architecture. In response to a signal instruction, the processing core 105 parallelly performs arithmetic operations for connecting one element among the data elements from the vector register and a scalar value from the scalar register for the respective arithmetic operations.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processor, and more particularly to the encoding of video and audio signals (e.g.
The present invention relates to a processor for performing parallel processing of multiple data elements for each instruction which is advantageously applied to multimedia functions such as ncoding and decoding.

[0002]

2. Description of the Related Art Programmable digital signal processors (DSPs) for multimedia applications such as real-time video encoding and decoding must be processed in a limited amount of time. Since a large amount of data is generated, high-speed processing capability is required. For example, as shown in JP-A-6-309349 or JP-A-6-266860, there are several architectures (architectures) for digital signal processors.
tecture) is known. Such general-purpose architectures employed in most microprocessors require fast computation cycles to provide a DSP with sufficient computing power for real-time video encoding or decoding. For this reason, such a DSP becomes expensive.

A very long instruction word (VLIW: Very Long In)
A struction word (VLIW) processor is a DSP having many functional units, most of which differ and perform relatively simple tasks. V
A single instruction to the LIWDSP is 128 bytes or more and has separate parts that execute separate functional units in parallel. The VLIWDSP has high computational power because many functional units can perform parallel operations. Also, the VLIWDSP is relatively inexpensive because each functional unit is relatively small and simple.

[0004]

The problems of the VLIW DSP are: input / output control that is not suitable for parallel execution of functional units of the VLIW DSP, communication with a host computer,
And inefficiency in handling other functions.
In addition, VLIW software is different from ordinary software and lacks programmers and program tools that are accustomed to the VLIW software architecture.
Difficult to develop.

[0005] DSPs that provide reasonable cost, high computing power, and a familiar programming environment are required for multimedia applications.

[0006]

In accordance with one aspect of the present invention, a multimedia digital signal processor includes a vector processor that operates on vector data (ie, multiple data elements per operand) to provide high computational power. Including. The processor is a single instruction having a RISC type instruction set-single-instruction-
Use multiple-data) architecture. For a programmer, the program environment is similar to that of a familiar general-purpose processor, so that the program can be easily adapted to the program environment of a vector processor.

[0007] The DSP includes a set of general purpose vector registers. Each vector register has a fixed size, but is divided into separate data elements of a user selectable size. Thus, the number of data elements stored in the vector register is determined by the selected size for the element. For example, a 32-byte register has 32 8-bit data elements, 16
Divided into 16-bit data elements or 8 32-bit data elements. The selection of data size and format is made by a vector register and an instruction for processing the operated data, and an execution data path for the instruction executes a number of parallel operations according to the data size indicated by the instruction.

Instructions to the vector processor can have vector registers or scalar registers as operands, and can operate multiple data elements of the vector registers in parallel to increase computational power. Examples of instruction sets for a vector processor according to the present invention include coprocessor interface operations, flow control operations, load / store operations, and logical / arithmetic operations. Logical / arithmetic operations combine data elements from one vector register with corresponding data elements from one or more other vector registers to generate a resulting data vector of data elements. including. Other logic / arithmetic operations mix various data elements from one or more vector registers or combine data elements from vector registers with scalar quantities.

An extension of the vector processor architecture adds scalar registers, each containing a scalar data element. Combining scalar and vector registers (combina
option) facilitates extending the instruction set of a vector processor, including instructions that combine each data element of a vector in parallel with a scalar value. For example, one instruction multiplies a vector data element by a scalar value. The scalar register also provides a storage location for a single data element to be extracted from or stored in the vector register. Scalar registers are also useful for passing information between a vector processor and a coprocessor having an architecture with only scalar registers, or for calculating effective addresses for load / store operations.

According to another feature of the invention, the vector registers of the vector processor are combined from a bank. Each bank can be selected as a "current" bank, while the other banks are "alternative" banks. The "current bank" bit in the control register of the vector processor indicates the current bank. Reducing the number of bits requires identifying the vector register, and some instructions provide only the register number to identify the vector register in the current bank. Load / store instructions have additional bits to identify a vector register from a bank. Thus, a load / store instruction can retrieve data in a replacement bank while operating on data in the current bank. This facilitates software pipelining for image processing and graphics procedures, and increases processor delays during data fetches because logical / arithmetic operations can be performed by load / store operations that access the alternate register banks out of rule. cut back. Other instructions allow the replacement bank to use double-sized vector registers, including the vector register from the current bank and the corresponding vector register from the replacement bank. Such a double size register can be identified from an instruction syntax. The control bits in the vector processor can be set so that the default vector size is one or one of the two vector registers. The replacement bank also has a shuffle with two sources and two destination registers,
Enables the use of smaller and unambiguous identified operands in compound instruction syntax such as unshuffle, saturate, and conditional move.

Further, the vector register stores the average quad (q
uad), shuffle, unshuffle, exchange with paired max, and implement new instructions such as saturation. These instructions perform operations common to multimedia functions such as video encoding and decoding, replacing two or more instructions required by other instruction sets to implement the same function. Thus, the vector processor instruction set improves the efficiency and speed of the program in multimedia applications.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. The same parts in the drawings are denoted by the same reference numerals.

FIG. 1 shows a multimedia signal processor 100 (MSP: Multimedia Sig) according to an embodiment of the present invention.
2 is a block diagram of an embodiment of the present invention. The multimedia processor 100 is a processing core 1 including a general-purpose processor 110 and a vector processor 120.
05 inclusive. The processing core 105 is an SRAM 16
0, 190, a ROM 170, and a cache subsystem 180, including a cache control 180, which are connected to the rest of the multimedia processor 100. The cache control 180 is the processor 110
Cache 162 and data cache 16 for
4 can configure the SRAM 160, and the instruction cache 192 and the data cache 194 for the vector processor 120 can configure the SRAM 190.

The one-chip ROM 170 stores the processor 11
It contains data and instructions for 0, 120, and can consist of a cache. In the preferred embodiment, ROM 170 contains reset and initialization procedures, self-test diagnostic procedures, interrupt and exception handlers, and sound blaster emulation subroutines. 3
4 Modem signal processing subroutine, general telephone function, 1-
D and 3-D graphic sublibraries and MPE
G-1, MPEG-2, H.264. 261, H .; 263, G.R.
728, G.R. Includes a subroutine library for audio and video standards such as 723.

The cache subsystem 130 connects the processors 110 and 120 to two system buses 140 and 15.
0, and the processors 110 and 120 and the bus 14
It acts as a cache and switching station for devices coupled to 0,150. System bus 1
The 50 operates at a higher clock frequency than the bus 140, and has an external local memory, a local bus of a host computer, and a direct memory access (DMA:
Direct Memory Access, and a device interface 152 for providing an interface to various analog / digital (A / D) and digital / analog (D / A) converters, a DMA controller 154, a local bus interface 156, and the memory controller 15.
8 is connected. The bus 140 has a system timer 1
42, UART (Universal Asynchronous Receiver Tra)
nsceiver) 144, bitstream processor 14
6, and the interrupt controller 148 are connected. A patent application merged with the present application, entitled "Method and Apparatus for Processing Multimedia Operation and Video Data of a Multimedia Signal Processor," has processors 110,120 accessed through cache system 130 and buses 140,150. The operation of the preferred device and cache subsystem 130 is described in further detail.

Processors 110 and 120 execute separate program threads and are structurally different to more efficiently perform the specific tasks assigned to them. Processor 110 favors control functions, such as the execution of a real-time operating system, and similar functions that do not require multiple repetitive calculations. Therefore, the processor 100
Does not require high computing power and can be implemented using a normal general-purpose processor architecture. The vector processor 120 performs number crunching including repetitive operations on common data blocks in most multimedia processing. Due to the high computational power and relatively simple programming, the vector processor 120 is a single instruction multiple result (SIMD).
Most data paths in the vector processor 120 in the illustrated embodiment have a width of one of 288 or 576 bits to support vector data operations. The instruction set for the vector processor 120 includes instructions particularly suitable for multimedia problems.

In the above embodiment, the processor 1
10 is a 32-bit RISC processor operating at 40 MHz and consistent with the ARM7 processor architecture including a register set defined by the ARM7 standard. The architecture and instruction set for the ARM7 RISC processor is described in "ARM7DMDataSheet", available from Advance RISC Machines Ltd., document number ARMDDI0010G. AR
M7DMDataSheet is included in this application by reference. Attachment A to be described later has a preferred embodiment of AR
7 illustrates the extension of the M7 instruction set.

The vector processor 120 calculates all vectors and scalar quantities. In a preferred embodiment,
The vector processor 120 is composed of a pipelined RISC engine operating at 80 MHz.
The registers of the vector processor 120 include a 32-bit scalar register, a 32-bit special purpose register, two banks of 288-bit vector registers, and two double-sized (eg, 576 bits) vector accumulator registers. Attachment C described later has a vector processor 1
The register set for the twenty preferred embodiments will now be described. In a preferred embodiment, the processor 12
0 includes 32 scalar registers whose instructions are identified by 5-bit register numbers 0-31. Further, there are provided 64 288-bit vector registers having a 32-bank vector register structure of two banks. Each vector register has a 1-bit bank number (0 or 1) and 0
３１31 are identified by 5-bit vector register numbers. Most instructions simply access the vector registers from the current bank, indicated as the default bank bit CBANK stored in the control register VCSR of the vector processor 120. Second control bit VEC6
4 indicates whether the default register number identifies a double size vector register including a register from each bank. The instruction syntax distinguishes register numbers identifying vector registers from register numbers identifying scalar registers.

Each vector register can be divided into data elements of programmable size. Table 1 shows the data formats supported for data elements in the 288 bit vector register.

[0020]

[Table 1]

In Appendix D below, additional explanations for data sizes and data formats supported by the preferred embodiment of the present invention are provided.

In the case of the int9 data format, a 9-bit byte is necessarily packed in a 288-bit vector register, but in other data formats, all the 9 bits are not used in the 288-bit vector register. A 288 bit vector register can hold 32 8 bit or 9 bit integer data elements, 16 16 bit integer data elements, or 8 32 bit integer or floating point elements. Also, two vector registers can be combined to wrap data elements in double size vectors. In the preferred embodiment of the present invention, the control bit VE is stored in the control and status register VCSR.
Setting C64 means that if double size (576 bits) is the default size of the vector register,
The vector processor 120 is set to the mode VEC64.

The multimedia processor 100 also includes a set of 32-bit extension registers 115 that can be accessed by both processors 110 and 120. A set of registers and their functions will be described in Appendix B described below in a preferred embodiment of the present invention. Extension registers and scalar and special purpose registers of the vector processor 120 may be accessed by the processor 110 in some circumstances. Two special "user" extension registers are processor 1
10, 120 have two read ports so that registers can be read simultaneously. Other extension registers cannot be accessed simultaneously.

The vector processor 120 has two optional states (VP_RUN, VP_IDLE) indicating whether the vector processor is running or idle.
Having. The processor 110 is a vector processor 12
When 0 is in state VP_IDLE, the scalar or special purpose registers of vector processor 120 can be read or written, but processor 110 can read or write registers of vector processor 120 while vector processor 120 is in state VP_RUN. The result is undecided.

The extension of the ARM7 instruction set to the processor 110 is performed by using the extension register and the vector processor 120.
And instructions to access special purpose registers. Instructions MFER and MFEP move data from the extension registers and scalar or special purpose registers of vector processor 120 to general registers of processor 110, respectively. The instructions MTER and MTE are respectively
Data is moved from general registers of processor 110 to extension registers and scalar or special purpose registers of vector processor 120. The TESTSET instruction reads the extension register and sets bit 30 of the extension register to 1
To be set. The instruction TESTSET is sent to the processor 110
Facilitates user / producer synchronization by setting the bit 30 to read the produced result or to generate a signal to the processor 120 used. Other instructions to the processor 110, such as STARTVP and INTVP, control the operation state of the vector processor 120.

The processor 110 is a vector processor 1
It functions as a master processor that controls 20 operations. Using an unbalanced split control between the processors 110, 120 simplifies the synchronization problem of the processors 110, 120. The processor 110 records the instruction address in the program counter for the vector processor 120 while the vector processor 120 is in the state VP_IDLE, thereby
Initialize 0. Thereafter, the processor 110 causes the vector processor 120 to change to the state VP_RUN (S).
Execute the TARTVP instruction. In state VP_RUN, vector processor 120 fetches instructions through cache subsystem 130, executes those instructions in parallel with processor 110, and subsequently executes its own program. After activation, the vector processor 120 may encounter an exception or VCJOIN or VJOIN
Execute the CINT instruction or continue execution until interrupted by processor 110. The vector processor 120 may record the result in an extension register, record the result in the shared address space of the processors 110 and 120, or may access a scalar or special purpose processor 110 to access when the vector processor 120 reenters the state VP_IDLE. By leaving the result in the register, the result of the program execution for the processor 110 can be passed.

The vector processor 120 cannot handle its own exception. Upon execution of the instruction causing the exception, the vector processor 120 enters the state VP_IDLE and issues an interrupt request to the processor 110 through a direct line. Vector processor 120 is in a state VP_ID until processor 110 executes another STARTVP instruction.
Left in LE. The processor 110 determines the exception event, reads the register VISRC of the vector processor 120, handles the exception as much as possible by further initializing the vector processor 120, and then, if desired, re-executes the vector processor
Adjust 0.

The IN executed by the processor 110
The TVP instruction interrupts the vector processor 120 so that the vector processor 120 enters the idle state VP_IDLE. For example, the instruction INTV
P is used in a multitasking system to exchange a vector processor from one task such as video decoding to another such as sound card emulation.

Vector processor instructions VCINT, VC
JOIN stops execution by vector processor 120 if the condition indicated by the instruction is satisfied, sets vector processor 120 to state VP_IDLE, and if such a request is not interrupted, processor 1
Issue an interrupt for 10. The program counter of the vector processor 120 (special purpose register V
(PC) indicates the instruction address next to the VCINT or VCJOIN instruction. Processor 110 may check the interrupt source register VISRC of vector processor 120 to determine whether the VCINT or VCJOIN instruction has caused an interrupt request. Because the vector processor 120 has a large data bus and is more efficient at saving and restoring registers, software executed by the vector processor 120 saves and restores registers during environmental switching. Another application related to the present application entitled "Efficient Environmental Saving and Restoration in Multiprocessors" describes a preferred system for environmental switching.

FIG. 2 shows the important functional blocks of the preferred embodiment of the vector processor 120. The vector processor 120 includes an instruction fetch unit (IFU: Instru
cfetch fetch unit (210), a decoder 220, a scheduler 230, an execution data path 240, and a load / store unit (LSU: Load / Store Unit) 250. I
The FU 210 fetches an instruction and processes a flow control instruction such as a branch. Instruction decoder 2
20 decodes one instruction every cycle according to the order of arrival from the IFU 210, and records the field value decoded from the instruction in the scheduler 230 in a FIFO manner. The scheduler 230 selects a field value issued to the execution control register required in the operation execution stage. The issue selection depends on the availability of processing resources such as the execution data path 240 or the load / storage unit 250 and the operand dependency. Execution data path 24
0 executes logical / arithmetic instructions that operate on vector or scalar data. The load / store unit 250 executes load / store instructions for accessing the address space of the vector processor 120.

FIG. 3 shows an IF including an instruction buffer divided into a main instruction buffer 310 and a second instruction buffer 312.
FIG. 4 shows a block diagram for an embodiment of U210. Main buffer 310 contains eight consecutive instructions, including the instruction corresponding to the current program count. Second instruction buffer 3
12 includes the subsequent 8 instructions of the buffer 310 instructions. IF
U210 also includes a branch target buffer 314 containing eight consecutive instructions containing the target of the next flow control instruction in buffer 310 or 312. In the preferred embodiment, the vector processor 120 uses a RISC-type instruction set if each instruction is 32 bits long, and the buffers 310, 312, 314 are 8x32 bit buffers and the cache subsystem 130 through a 256 bit instruction bus. Connected to. The IFU 210 uses the cache subsystem 13 within a single clock cycle.
0 to any one of buffers 310, 312, and 314
8 instructions can be loaded at a time. Register 34
0, 342, 344 are buffers 310, 31 respectively.
2, 314 indicates the base address for the instruction loaded.

The multiplexer MUX 332 selects the current instruction from the main instruction buffer 310. If the current instruction is not a flow control instruction and instruction register 33
If the instruction stored at 0 is before the execution of the decoding phase, the current instruction is stored in the instruction register 330 and the program count is incremented. After incrementing the program count selects the last instruction in buffer 310, the next set of eight instructions is loaded into buffer 310. If buffer 312 contains the desired eight instructions, buffer 31
2 and the contents of register 342 are immediately moved to buffer 310 and register 340, and eight or more instructions are prefetched from cache subsystem 130 to second instruction buffer 312. The adder 350 is a multiplexer MUX35.
2 determines the address of the next set of instructions from the base address of the offset register 342 selected. The result address from adder 350 is stored in register 342
Is moved to the register 340 or after that, is stored in the register 342. Further, the calculated address is sent to the cache subsystem 130 having a request for eight instructions. When a preliminary call to cache subsystem 130 is requested from buffer 310, if the next eight instructions to buffer 312 are not already provided, the previously requested instruction is stored in buffer 310 as soon as it is received from cache subsystem 130. You.

If the current instruction is a flow control instruction, IFU 210 evaluates the condition for the flow control instruction and processes the instruction by updating the program count according to the flow control instruction. The IFU 210 is suspended if the condition has not been determined because the previous instruction whose condition can be changed has not been completed. If no branch is taken, the program is incremented and the next instruction is selected as described above. If a branch is taken and branch target buffer 314 contains the target of the branch, the contents of buffer 314 and register 344 are moved to buffer 310 and register 340, and IFU 210 causes cache subsystem 130
The instruction is continuously provided to the decoder 220 without waiting for the instruction from.

To prefetch instructions for branch target buffer 314, scanner 320 looks for the next flow control instruction after the current program count.
Scan the buffers 310 and 312. If a flow control instruction is found in the buffer 310 or 312, the scanner 320 returns to the buffer containing the instruction (310
Or 312) determine an offset from the base address to an ordered set of eight instructions including the target address of the flow control instruction. Multiplexers 352, 35
4 provides the base address and offset from the flow control instruction to adder 350 which generates a new base address for buffer 314 from register 340 or 342. The new base address is applied to the cache subsystem 130 to continue providing eight instructions to the branch target buffer 314.

The "decrease and conditional branch" instruction (VD1
When processing flow control instructions such as CBR, VD2CBR, VD3CBR) and the "change control register" instruction VCHGCR, the IFU 210 can change the register value in addition to the program count. I
When the FU 210 finds an instruction that is not a flow control instruction, the instruction is sent to the instruction register 330 and then to the decoder 220.

As shown in FIG. 4, the decoder 220 decodes the instruction by recording the control value in the field of the FIFO buffer 410 by the scheduler 230. F
IFO buffer 410 includes four rows of flip-flops, and each flip-flop may include five fields of information for controlling execution of one instruction. Matrices 0 through 3 each contain information for the oldest to newest instructions, and the information in FIFO buffer 410 is shifted to lower matrices when older information is completely removed as instructions. Scheduler 23
0 issues an instruction to the execution end by selecting a necessary field of the instruction to be loaded into the control pipe 420 including the execution registers 421 to 427. Most instructions can be scheduled for issue and execution in an irregular order. In particular, the order of the logical / arithmetic operation and the load / store operation is arbitrary as long as there is no operand dependency between the load / store operation and the logical / arithmetic operation. FIFO buffer 410
A comparison of field values indicates whether an operand dependency exists.

FIG. 5 shows a six-stage execution pipeline for an instruction that performs a register-to-register operation without accessing the address space of the vector processor 120. At instruction fetch stage 511, IFU 210 fetches the instruction as described above. The fetch end requires one clock cycle unless the IFU 210 is suspended by pipeline delays, outstanding branch conditions, or delays in the cache subsystem 130 that provides prefetched instructions. In the decoding step 512, the decoder 220 decodes the instruction from the IFU 210 and records information on the instruction in the scheduler 230. Note that the decoding step 512 requires one clock cycle unless any matrix in the FIFO 410 uses a new operation. The operation may be issued to the control pipe 420 during the first cycle in the FIFO 410, but may be delayed by the issuance of older operations.

Execution data path 240 performs register-to-register operations and provides addresses for load / record operations. FIG. 8 is a block diagram of an embodiment of execution datapath 240, which is described in connection with execution stages 514, 515, 516. The execution register 421 reads the read stage 5
It provides a signal identifying two registers to the register file 610 read in a clock cycle during fourteen. Register file 610 includes 32 scalar registers and 64 vector registers. FIG. 9 is a block diagram of the register file. Register file 610 has two read ports and two write ports to accommodate two reads and two writes each clock cycle. Each port is a selection circuit 612, 614, 616 or 618
And 288 bit data buses 613, 615, 617 or 619. Circuits 612, 614, 616, 61
Selection circuits such as 8 are well known in the art,
Address signal WRADDR derived by decoder 220 from the 5-bit register number typically extracted from the instruction
1, WRADDR2, RDADDR1 or RDADD
It uses R2, bank bits from the instruction or control status register VCSR, and an instruction syntax that indicates whether the register is a vector register or a scalar register. Data reads are made to load / store unit 250 through multiplexer 656 or to multiplier 620, arithmetic logic unit 630, or accumulator 640 through multiplexers 622,624. Most operations read two registers,
The read phase 514 is completed in one cycle. However, the read stage 514 is longer than one clock cycle because some instructions, such as the multiply and add instructions VMAD and the instructions that adjust the double size vector, require data from more than one register.

During execution stage 515, while passing through multiplier 620, arithmetic logic unit 630, and accumulator 640, the processed data is stored in register file 610.
Is read in advance. The execution stage 515 can overlap the read stage 514 if a number of cycles are required to read the required data. The duration of the execution phase 515 depends on the type of data element (integer or floating point) and the amount of data processed (number of read cycles). Execution registers 422, 42
3,425 signals are used by the arithmetic and logic unit 630, the accumulator 640, for the first operation performed during the execution phase.
And input data to the multiplier 620. Execution registers 432, 433, and 435 indicate execution stage 5
The second operation performed during 15 is controlled.

FIG. 10 shows a multiplier (multiplier) 620.
And a block diagram for an embodiment of an ALU (arithmetic and logic unit) 630. Multiplier 620
Are eight independent 36 × 36 bit multipliers 62
6 is an integer multiplier. Each multiplier 626 includes four 9 × interconnected control circuits.
Includes 9-bit multiplier. If it has 8-bit and 9-bit data element sizes, the scheduler 23
The control signal from 0 separates the four 9 × 9 bit multipliers from each other so that each multiplier 626 performs four multiplications, such that the multiplier 620 performs 32 independent multiplications during one cycle. . For a 16-bit data element, the control circuit connects a pair of 9 × 9-bit multipliers to operate together, and the multiplier 620 performs 16 parallel multiplications. For the 32-bit integer data element type, eight multipliers 6
26 performs eight parallel multiplications every clock cycle. The result of the multiplication is 57 for the 9-bit data element size.
Provides 6 bits and 5 for other data sizes
Provides 12 bits.

ALU 630 can process a 576-bit or 512-bit result generated from multiplier 620 in two clock cycles. ALU6
30 includes eight independent 36-bit ALUs 636.
Each ALU 636 has 32 × for floating point addition and multiplication.
Includes a 32-bit floating point unit. For integer operations, each ALU 636 can perform independent 8-bit and 9-bit operations and includes four units that can be connected together in two or four sets for 16-bit and 32-bit integer data elements.

An accumulator 640 accumulates the result and uses two 5's for higher precision in the intermediate result.
Includes a 76-bit register.

During the recording phase 516, the results of the execution phase are stored in the register file 610. Two registers can be recorded during a single clock cycle, and input multiplexers 602 and 605 select the two data values to be recorded. During the recording phase 516 for the operation, the amount of data to be recorded as the operation result and the L to complete the load instruction by recording in the register file 610.
It depends on the completion from SU 250. Execution register 4
Signals from 26 and 427 select the register where the data of logic unit 630, accumulator 640, and multiplier 620 are recorded.

FIG. 6 shows an execution pipeline 520 for executing a load instruction. The instruction fetch stage 511, decoding stage 512, and issue stage 513 for the execution pipeline 520 are the same as described for register-to-register operations. In addition, the read stage 514 determines whether the execution data path 240 is to call the register file 6 to determine the calling address for the cache subsystem 130.
10 is the same as above except that data is used. Multiplexer 65 in address stage 525
2, 654, 656 select the addresses provided to load / store unit 250 for execution stages 526, 527. Information for the load operation is provided in steps 526 and 527
During this period, the load / store unit 250 processes the operation.

FIG. 11 shows an embodiment for the load / storage unit 250. During step 256, a call is made to the cache subsystem 130 for the data at the address determined in step 525. The preferred embodiment provides a transaction based cache call when multiple devices, including processors 110 and 120, access the local address space through cache subsystem 130.
Use l). Although the requested data may not be available during some cycles after a call to the cache subsystem 130, the load / store unit 250 makes a call to the cache subsystem while other calls are pending. be able to. Therefore, the load / store unit 250 is not stopped. The number of clock cycles required by the cache subsystem to provide the requested data is determined by the data cache 194
It depends on whether there is a hit or a mistake.

In drive stage 527, cache subsystem 130 requests a data signal to load / store unit 250. Cache subsystem 1
30 is 2 per cycle to load / store unit 250
56 bit (32 byte) data can be provided. Byte aligner 710 aligns each of the 32 bytes in a corresponding 9-bit storage location to provide a 288-bit value. The 288 bit format is convenient for multimedia applications such as MPEG encoding and decoding, which sometimes use 9 bit data elements. The 288 bit value is recorded in read data buffer 720. In the recording step 528, the scheduler 230 transmits the field 4 from the FIFO buffer 410 to the execution register (426 or 427), and records the 288 bit amount from the data buffer 720 to the register file 610.

FIG. 7 shows an execution pipeline 530 for execution of a store instruction. Retrieval stage 511, decryption stage 512, and issue stage 5 for execution pipeline 530
13 is the same as described above. The reading step 514 is the same as described above, except that the data to be stored and the data for address calculation are read. The data to be stored is stored in the recording data buffer 7 in the load / store unit 250.
30 is recorded. Multiplexer 740 converts data in a format that provides 9-bit bytes to a conventional format that has 8-bit bytes. Buffer 73
The translated data from 0 and the associated address from address calculation stage 525 are sent in parallel to cache subsystem 130 during SRAM stage 536.

In the preferred embodiment of vector processor 120, each instruction is 32 bits long and
Has one of the nine formats shown in
AR, REAI, RRRM5, RRRR, RI, CT,
RRRM9, RRRM *, and RRRM9 ** levels are given. The instruction set for the vector processor 120 will be described in Appendix E.

Some load, store, and cache operations that use scalar registers when determining the effective address have a REAR format. REAR-format instruction is identified by bits 29-31 of 000b and has two register numbers SR for the scalar register.
b, SRi and three operands identified by the register number Rn of the register which may be a scalar or a vector register by bit D. Bank bit B
Indicates the bank for the register Rn or, if the default vector register size is double size, indicates whether the vector register Rn is a double size vector register. op-code field Op
c identifies the operation to be performed on the operand, and field TT refers to the type of transmission, such as load or store. A typical REAR-format instruction is a scalar register S
An instruction VL for loading the register Rn from an address determined by adding the contents of Rb and SRi.
If bit A is set, the calculated address is stored in scalar register SRb.

The REA1-format instruction is the same as the REAR instruction except that the 8-bit intermediate value of the field IMM is used instead of the contents of the scalar register SRi. The REAR and REAI formats do not have a data element size field.

The RRRM5 format is for instructions with two source operands and one destination operand. These instructions have one of a 3-register operand or a 2-register operand and a 5-bit intermediate value.
As shown in Attachment E, the encoding of the fields D, S, and M determines whether the first source operand Ra is a scalar or a vector register, and
/ IM5 is a scalar register, a vector register, or a 5-bit intermediate value.
It is determined whether or not d is a scalar or a vector register.

The RRRR format is for instructions with four register operands. Register number R
a and Rb indicate a source register. Register number R
d indicates the destination register, and the register number Rc indicates one of the source or destination register according to the field Opc. All operands are vector registers, except when bit S is set to indicate that register Rb is a scalar register. Field D
S indicates the data element size for the vector register. Field Opc selects the data type for the 32-bit data element.

The RI-format instruction causes an intermediate value to be loaded into a register. Field IMM contains intermediate values up to 18 bits. The register number Rd is one of the scalar register by bit D and the vector register of the current bank.
Are the target registers. Fields DS and F indicate the respective data element sizes and types. 32
In the case of a bit integer data element, the 18-bit intermediate value is the sign extended before being loaded into register Rd. Bit 1 for floating point data element
8, bits 17 to 10, and bits 9 to 0 are each 3
Sine, exponent, and mantissa of two-bit floating point value
ssa).

The CT format is for a flow control instruction, and includes an op-code field Op.
c, condition field Cond, 23-bit intermediate value IMM
including. If the condition indicated by the condition field is true, a branch is taken. Possible condition codes are "always", "less than", "equal", "less than or equa"
l), “greaterthan”, “not identical (no
t equal) ”,“ greater than
or equal) "and" overflow ". Bits GT, E in the status and control register VCSR
Q, LT, and SO are used to evaluate conditions.

The format RRRM9 provides either a 3-register operand or a 2-register operand and a 9-bit intermediate value. The combination of bits D, S, and M indicates which operand is a vector register, a scalar register,
Alternatively, it indicates whether it is a 9-bit intermediate value. Field DS
Indicates a data element size. RRRM9 * and RR
The RM9 ** format is a special case of the RRRM9 format, and is distinguished by an operation code field Opc. In the RRRM9 ** format, the source register number Ra is replaced with a condition code Cond and an ID field. The RRRM9 ** format uses the most significant bit MSB of the intermediate value as the condition code Cond and bit K.
Was replaced with Additional explanations for RRRM9 * and RRRM9 ** are provided in Appendix E below in connection with the conditional move command VCMOV, the conditional move CMOVM with element mask, and the compare and set mask CMPV instruction.

While the invention has been illustrated and described in connection with specific preferred embodiments thereof, it will be understood that various modifications and alterations of the invention may be made without departing from the spirit and scope of the invention as defined by the appended claims. It will be obvious to those having ordinary skill in the art that they can be transformed.

Attachment A In the exemplary embodiment, processor 110 is a general purpose processor that meets the ARM7 processor standard. ARM architecture literature or ARM7 for description in registers in ARM7 processor
Reference is made to the data sheet (literature number ARMDDI0020C issued in December 1994).

For interaction with the vector processor 120, the processor 110 starts and stops the vector processor, tests the vector processor state including synchronization, and passes data from scalar / special registers in the vector processor 120 to the processor. The data is transmitted to the general-purpose register side in 110, and the data from the general register is transmitted to the vector processor scalar / special register side. Such transmission requires a memory as an intermediary.

Table 2 describes the ARM7 instruction set extension for vector processor interaction.

[0060]

[Table 2]

[0061]

[Table 3]

Table 3 lists ARM7 exceptions, which are detected and reported before executing the floating instruction. The exception vector address is given in hexadecimal notation.

[0063]

[Table 4]

Next, an extension syntax for the ARM7 instruction set will be described. ARM architecture literature on terminology and instruction format or ARM7 data sheet (literature number AR issued in December 1994)
Reference is made to MDDI0020C.

The ARM architecture provides three different instruction formats for the coprocessor interface.

1. 1. Coprocessor data operation (CDP) 2. Coprocessor data transmission (LDC, STC) Coprocessor Register Transfer (MRC, MCR) The MSP architecture extension uses all three forms. Data operation format CDP of the coprocessor
Is used for operations that do not need to be transmitted again to the ARM7 side.

[0067]

[Table 5]

[0068]

[Table 6]

The coprocessor data transmission format (L
DC, STC) is used to load or store a subset of the registers of the vector processor directly into memory. The ARM7 processor serves to supply word addresses, and the vector processor supplies or receives data and controls the number of words transmitted. Refer to the ARM7 data sheet for more details.

[0070]

[Table 7]

[0071]

[Table 8]

The coprocessor register transmission format (MRC, MCR) is used to communicate information directly between the ARM7 and the vector processor. This format is used to move between ARM7 registers and vector processor scalar or special registers.

[0073]

[Table 9]

[0074]

[Table 10]

Description of Extended ARM Instruction Extended ARM instruction will be described in alphabetical order.

CACHE cache operation

[0077]

[Table 11]

Assembler syntax STC {cond} p15, c0pc, (Addre
ss) CACHE ｛cond｝ Opc, (Address) where cond = ｛eq, he, cs, cc, mi,
pl, vs, vc, hi, Is, ge, It, gt, l
e, ai, nv}, Opc = {0, 1, 3}. LDC /
Note that the decimal notation of the opcode should start with the letter “c” in the first syntax (ie, use c0 instead of 0), since the CRn field of the STC format is used to specify Opc. I want to be. See ARM7 data sheet for address mode syntax.

[0079]

[Table 12]

Operation Reference is made to the ARM7 data sheet for the method of calculating EA.

Exceptions ARM7 Protection Violation INTVP Interrupt Vector Processor

[0082]

[Table 13]

Assembler syntax CDP {cond} p7,1, c0, c0, c0 INTVP {cond} where cond = {eq, ne, cs, cc, mi,
pl, vs, hi, ls, ge, lt, gt, le, a
1, ns} Description This instruction is performed only when Cond is true.

This instruction sends a signal to stop the vector processor.

The ARM 7 continues to execute the next instruction without waiting for the stop of the vector processor.

The MFER busy loop should be used to check if the vector processor has been stopped after this instruction has been performed. This instruction has no effect if the vector processor is in the VP_IDLE state in advance.

Bits 19:12, 7:15 and 3: 0 are reserved.

Exception Vector processor not available.

Move from MFER Extension Register

[0090]

[Table 14]

Assembler syntax MRC ｛cond｝ p7,1, Rd, cP, cER, 0 MFER ｛cond｝ Rd, RNAME where cond = ｛eq, he, cs, cc, mi,
pl, rs, vs, hi, ls, ge, lt, gt, l
e, al, nv}, Rd = {r0,... r15}, P
= {0,1}, ER = {0, ... 15}, and RNA
ME stands for architecturally specified register mnemonic {ie, PERO or CSR}.

[0092]

[Table 15]

Bits 19:17 and 7: 5 are reserved.

Exceptions Protection breach when trying to access PERx while in user mode Move from MFVP vector processor

[0095]

[Table 16]

Assembler syntax MRC {cond} p7,1, Rd, Crn, CRm,
0 MFVP ｛cond｝ Rd, RNAME where cond = ｛eq, ne, cs, cc, mi,
pl, vs, vc, hi, ls, ge, lt, gt, l
e, al, nv}, Rd = {r0,... r15}, C
Rn = {c0,... C15}, CRm = {c0,.
c15}, and RNAME is an architecturally specified register mnemonic {ie, SPO or VC
It means S｝.

[0097]

[Table 17]

SR0 is read as 32 bits which are always 0, and the record for this is ignored.

Exception: Unable to use vector processor MTER Move to extension register side

[0100]

[Table 18]

Assembler syntax MRC ｛cond｝ p7,1, Rd, cP, cER, 0 MERR ｛cond｝ Rd, RNAME where cond = ｛eq, he, cs, cc, mi,
pl, rs, vc, hi, ls, ge, lt, gt, l
e, al, nv}, Rd = {r0,... r15}, P
= {0,1}, ER = {0, ... 15}, and RNA
ME stands for architecturally specified register mnemonic {ie, PERO or CSR}.

[0102]

[Table 19]

Bits 19:17 and 7: 5 are reserved.

Exceptions Protection violation when trying to access PERx during user mode Move to MTVP vector processor side

[0105]

[Table 20]

Assembler syntax MRC {cond} p7,1, Rd, cRn, CRm,
0 MERR ｛cond｝ Rd, RNAME where cond = ｛eq, ne, cs, cc, mi,
pl, vs, hi, ls, ge, lt, gt, le, a
l, nv}, Rd = {r0,... r15}, CRn =
{C0,... C15}, CRm = {c0,... C1
5}, and RNAME stands for architecturally specified register mnemonic {ie, SPO or VCS}.

[0107]

[Table 21]

Exception Vector processor unavailable PFTCH prefetch

[0109]

[Table 22]

Assembler syntax MRC {cond} p15,2, (Address) MFTCH {cond} (Address) where cond = {eq, he, cs, cc, mi,
pl, rs, vc, hi, ls, ge, lt, gt, l
e, al, nv}, ARM for address mode syntax
7 Refer to the data sheet.

Description This instruction is executed only when Cond is true. The cache line specified by the EA is prefetched to the ARM7 data cache side.

Calculation The method of calculating EA is described in the ARM7 data sheet.

Exception None STARTVP Start vector processor

[0114]

[Table 23]

Assembler syntax CDP {cond} p7,2, c0, c0, c0 STARTVP {cond} where cond = {eq, he, cs, cc, mi,
pl, vs, vc, hi, ls, ge, lt, gt, l
e, al, nv} Description This instruction is performed only when Cond is true. This instruction sends a signal to the vector processor to start execution, and VISRC (vjp) and VISRC (vi
p) is automatically cleared. The ARM 7 continues to execute the next instruction without waiting for the vector processor to start executing. The state of the vector processor should be initialized to the desired state before this instruction is performed. This instruction has no effect if the vector processor has previously been in the VP_RUN state.

Bits 19:12, 7: 5, and 3: 0 are reserved.

Exceptions Vector processor unavailable TESTSET test and set

[0118]

[Table 24]

Assembler syntax MRC ｛cond｝ p7,0, Rd, c0, cER, 0 TESTSET ｛cond｝ Rd, RNAME where cond = ｛eq, he, cs, cc, mi,
pl, rs, re, hi, ls, ge, lt, gt, l
e, al, nv}, Rd = {r0,... r15}, ER
= {0,... 15}, and RANAME is an architecturally specified register mnemonic (ie, UER
1 or VASYNC).

Description This instruction is executed only when Cond is true. This instruction restores the contents of UERx through RD, and UERx (3
0) is set to 1. When the ARM7 register (15) is specified as the destination register, the UERx (30)
Returns from the Z bit of the SR, which causes a short busy (bus
y) A waiting loop can be performed. Currently, UER1
Only are defined to operate according to this instruction.

Bits 19:12 and 7: 5 are reserved.

Exceptions None [Attachment B] The multimedia processor architecture 100 is such that the processor 110 uses the MFER instruction or the MTE instruction.
An extension register to be accessed by the R instruction is defined. The extension register includes a privilege extension register and a user extension register.

The privilege extension register is mainly used to control the operation of the multimedia signal processor. These are shown in Table 12.

[0124]

[Table 25]

The control register controls the operation of the MSP (100). All bits of CTR are cleared on reset. The register definitions are shown in Table 2B.

[0126]

[Table 26]

[0127]

[Table 27]

The status register indicates the status of the MSP (100). All bits of the field STR are cleared at reset. The register definitions are shown in Table 14.

[0129]

[Table 28]

The processor version register indicates the particular version of a particular processor in the processor's multimedia signal processor family.

The vector processor interrupt mask register VIMSK controls operations that report vector processor exceptions to the processor 110. Each bit of VIMSK, when set with the corresponding bit of the VISRC register, enables an interrupt exception to ARM7. This has no effect on how to detect a vector processor exception, but only on whether the exception should interrupt ARM7. All bits of VIMSK are cleared on reset. The register definitions are shown in Table 15.

[0132]

[Table 29]

The ARM7 instruction address breakpoint register supports this during ARM7 program debugging. The register definitions are shown in Table 16.

[0134]

[Table 30]

The ARM7 data address breakpoint register supports this during ARM7 program debugging. The register definitions are shown in Table 17.

[0136]

[Table 31]

The scratch pad register configures the address and size of a scratch formed using the SRAM of the cache subsystem 130. The register definitions are shown in Table 18.

[0138]

[Table 32]

The user extension register includes the processor 110,
Mainly used for synchronization of H.120. The user extension register is currently defined to have only one bit mapped to bit 30, "MFERR15, UER
An instruction such as x "returns, for example, the bit value to the Z flag side. The bits UERx (31) and UERx (29:
0) is always read as zero. The user extension registers are described in Table 19.

[0140]

[Table 33]

Table 20 shows the state of the extension register at power-on reset.

[0142]

[Table 34]

[Appendix C] The architectural state of the vector processor 120 is 32 32-bit scalar registers; 2 banks of 32 288-bit vector registers: a pair of 576-bit vector accumulator registers; 1 set of 32-bit special registers Contains. Scalar registers, vector registers and accumulator registers are for general purpose programming and support a number of other data formats.

This and the following sections use the following notation: : VR indicates a vector register,
VRi indicates the ith vector register (zero offset), VR [i] indicates the ith data element of the vector register VR, and VR (a: b) indicates the vector register V
R indicates bits a and b of VR [i] (a:
b) shows bits a and b of the ith data element of the vector register VR.

The vector architecture has a number of additional element DML data types and sizes in one vector register. Since the vector register has a fixed size, the number of data elements that can be held depends on the size of the element. The MSP architecture defines five element sizes as shown in Table 21.

[0146]

[Table 35]

The MSP architecture interprets vector data according to the specified data type and instruction size.
Currently, two's complement (integer) format is supported for most arithmetic instruction byte, byte 9, Huffword and word element sizes. In addition, IEEE7
The four single precision format supports the word element size of most arithmetic instructions.

As long as the instruction sequence produces a meaningful result, the programmer is free to interpret the data in the desired manner. For example, programmers say that a program is "fals
e) As long as the overflow result can be handled, the byte 9 size is freely used for storing unsigned 8-bit numbers, and the unsigned 8-bit numbers of byte-size data elements are also freely stored and provided The operation can be freely performed on these using two's complement arithmetic instructions.

There are 32 scalar registers denoted by SR0 to SR31. These scalar registers are 32 bits wide and can include one data element of any size of undetermined size. The scalar register SR0 is special in that the register SR0 is 32 consisting of 0 and can always be read, and the recording in the register SR0 is ignored. The byte type, byte type 9 and Huffword data type are stored in the least significant bit of the scalar register having the most significant bit with an undefined value.

Since a register does not have a data type indicator, the programmer must know the data type of the register used for each instruction. This is different from other architectures where a 32-bit register is assumed to include a 32-bit register. The MSP architecture indicates that the result of data type A modifies only those bits that have not been determined for data type A. For example, the result of byte 9 addition modifies only the lower 9 bits of the 32-bit destination scalar register. The value of the upper 23 bits is undetermined unless otherwise specified for the instruction.

The 64-vector register is composed of two banks each having a 32-bit register. Bank 0 contains a first 32 registers and bank 1 contains a second 32 bit register. One of these two banks is used as a current bank, and the other is used as a replacement bank. All vector instructions, except for load / store and move register instructions that can access the vector registers of the replacement bank, are the default and use the registers in the current bank. The CBANK bit of the vector control and status register VCSR is used to set bank 0 or bank 1 as the current bank (other banks are alternate banks). The vector registers in the current bank are VR0 to VR31, and the vector registers in the replacement bank are VRA0 to VRA31.

Also, the two banks can be conceptually combined to provide 32 double size vector registers of 576 bits each. The VEC64 bit of the control register VCSR indicates this mode.
In VEC64 mode, there is no current bank or replacement bank, and the vector register number indicates the corresponding pair of 288 vector bit vectors from the two banks. That is, VRi (575: 0) = VR1i (287: 0): VR
0i (287: 0) Here, VR0i and VR1i indicate a vector register having a register number VRi in bank 1 and bank 0, respectively. Double size vector register is VR0
To VR31.

The vector register can contain a number of elements of byte, byte 9, huff word or word size as shown in Table 22.

[0154]

[Table 36]

Mixing between element sizes in one vector register is not supported. Excluding the byte 9 element size, only 256 bits out of 288 bits are used. In particular, not all ninth bits are used.
The unused 32 bits of the byte, huff word and word size are reserved and the programmer cannot make any assumptions about these values. The vector accumulator register provides an intermediate result to storage with higher accuracy than the result of the destination register. The vector accumulator register is composed of four 288-bit registers, that is, VAC1H, VAC1L, VAC0H, and VAC0L. The VAC0H, VAC0L pair is used by three instructions by default. VEC6
Only in 4 modes, the VAC1H, VAC1L pairs are used to mimic 64 byte 9 vector operations. To produce an extended accuracy result having the same number of elements as the source vector registers, the extended precision elements are saved over a pair of registers as shown in Table 23.

[0156]

[Table 37]

The VAC1H, VAC1L pair can only be used in VEC64 mode, where the number of elements can be 64, 32, or 16 for byte 9 (and byte), Huffword, and Word, respectively. .

There are 33 special registers that can be loaded directly from memory or stored directly in memory. Sixteen special registers, RASR0 through RASR15, form an internal return address stack and are used by subroutine call and subroutine return instructions. Seventeen or more 32-bit special registers are shown in Table 24.

[0159]

[Table 38]

Vector control and status register (VCS)
The definitions for R) are shown in Table 25.

[0161]

[Table 39]

[0162]

[Table 40]

[0163]

[Table 41]

Vector program counter register VP
C is the address of the next instruction to be executed by the vector processor 120. The ARM7 processor 110 executes STA to start the operation of the vector processor 120.
Register VPC must be loaded before issuing an RTVP instruction.

Vector exception program counter VEPC
Specifies the address of the instruction that causes the most recent exception. MSP100 does not support exact exceptions,
Therefore, the term "most likely to occur" is used.

Vector interrupt supply register VIS
RC provides interrupt source to ARM7 processor 110
To be specified. The appropriate bits are set by hardware upon detection of an exception. Software must clear register VISRC before vector processor 120 resumes execution. A certain bit set in the register VISRC sets the vector processor 120
Enters state VP_IDLE. An interrupt to processor 110 is signaled when the corresponding interrupt enable bit is set to VIMSK. Table 2
6, the contents of the register VISRC are defined.

[0167]

[Table 42]

Vector interrupt instruction register VII
NS is ARM if VCINT instruction or VCJOIN instruction
7 is executed to interrupt the processor 100, the instruction is updated to the VCINT instruction or the VCJOIN instruction.

Vector count registers VCR1 and VC
R2 and VCR3 are reduced and branch instructions VD1CBR,
For VD2CBR, VD3CBR, initialized to count of loops performed. Instruction VD1CB
When R is performed, register VCR1 is decremented by one. If the count value is not zero and the condition specified in the instruction matches VFLAG, a branch is taken. If they do not match, no branch is taken. Register VCR1 is decremented by one in two cases. Registers VCR2 and VCR3 are used in the same manner.

Vector global mask register VGM
R0 is the VR (575:
288) and V in VEC64 mode
Used to indicate an element in R (287: 0). Each bit of register VGMR0 controls the updating of 9 bits of the vector destination register. Specifically, VGMR0 (i) is VRd in the VEC32 mode.
The update of (9i + 8: 9i) is controlled, and in the VEC64 mode, the update of VR0d (9i + 8: 9i) is controlled. V
R0d indicates the target register of bank 0 in VEC64 mode. VRd means a destination register of the current bank which can be bank 0 or bank 1 in VEC32 mode. Vector global mask register VGMR0 is VCMO
Used for execution of all instructions except VM instructions.

Vector global mask register VGM
R1 is the affected VR in VEC64 mode (575:
288). Each bit of register VGMR1 controls the updating of 9 bits of the vector destination register of bank 1. Specifically, VGMR (i) controls updating of VR1d (9i + 8: 9i). Register VGRM1 is not used in VEC32 mode, but VEC64 affects the execution of all instructions except the VCMOVM instruction.

The vector overflow register VOR0 stores the V containing the overflow result after the vector arithmetic operation.
Used to indicate an element in VR (287: 0) in EC64 mode. This register is not modified for scalar arithmetic. Bit VOR1 (i) set
Indicates that the ith element of byte or byte 9, the (idiv2) element of the Huffword, or the (idiv4) element of the word data type operation contains an overflow result. For example, bit 1
And bit 3 are set to indicate the overflow of the first Huff word and the word element, respectively. VO
R0 bit mapping is VGMR0 or VGMR
This is different from the mapping of one bit.

The vector overflow register VOR1 is used to point to an element in VR (575: 288) in VEC64 mode that contains the result of the overflow after vector arithmetic. The register VOR1 is V
It is not used in EC32 mode and is not modified by scalar arithmetic. Bit VOR1 set
(I) indicates that the ith element of byte or byte 9, the first (idiv2) element of the Huffword, or the (idiv4) element of the word data type operation contains an overflow result. For example,
Bits 1 and 3 are each VR (575: 288)
Is set to indicate the overflow of the first Huff word and the word element. The bit mapping of VOR1 is different from the bit mapping of VGMR0 or VGMR1.

Vector instruction address breakpoint register V
IABR supports this during vector program debugging. This register definition is shown in Table 27.

[0175]

[Table 43]

The vector data address breakpoint register VDABR is used to debug vector programs.
g) sometimes assist in this. Table 28 shows the register definitions.

[0177]

[Table 44]

The vector movement mask register VMMR0 is always used by the VCMOVM, not only when VCSR (SMM) = 1 for the mode instruction. Register VMMR0 is the element of the destination register affected in VEC32 mode, and VR (28) in VEC64 mode.
7: 0). Each bit of VMMR0 controls a 9-bit update of the vector destination register. Specifically, VMMR0 (i) is VEC32
Update VRd (9i + 8: 9i) in mode and VEC6
Update of VR0d (9i + 8: 9i) is controlled in four modes. VR0d indicates the target register of bank 0 in VEC64 mode, and this VRd indicates the target register of bank 0 in VEC32 mode.
Alternatively, it means a target register of the current bank which can be the bank 1.

The vector movement mask register VMMR1 is always used by the VCMOVM, not only when VCSR (SMM) = 1 for all instructions. The register VMMR1 stores the affected VR (5) in the VEC32 mode.
75: 288). VMMR1
Control the update to 9 bits of the bank 1 vector destination register. Specifically, VGM
R01 (i) controls updating of VRd (9i + 8: 9i). Register VGMR1 is not used in VEC32 mode.

Vector and ARM7 synchronization register VAS
YNC provides producer / consumer style synchronization between processor 110 and processor 120. Currently bit 3
Only 0 is defined. The ARM7 processor can access the register VASYNC using instructions (MFER, MTER, TESTSET), and the vector processor 120 can read the state VP_RUN or state VP.
_IDLE. Registers VASYNC cannot access the ARM7 processor through the TVP or MFVP instructions, since these instructions cannot access the special registers of the first 16 vector processor. The vector processor can access the register VASYNC through the VMOV instruction.

Table 29 shows the state of the vector processor at the time of power-on reset.

[0182]

[Table 45]

The special register is initialized by the ARM7 processor 110 before the vector processor can execute an instruction.

[Appendix D] Each instruction means or designates a data type of a source and a destination overland. Some instructions take one data type for the source,
It has the meaning of generating a different data type for the result. This appendix describes the data types indicated in the preferred embodiment. In Table 30 of this application, the supported data types int8, int9, int16, int32,
And float. The unsigned integer format is not supported, and its unsigned integer value should first be converted to two's complement format before use. The programmer is free to use arithmetic instructions with some other format or unsigned integer format depending on their choice, as long as they handle overflow appropriately. The architecture is simply two's complement overflow and 32
Defines a bit floating point data type. The architecture requires 8, 9, 1 to detect unsigned overflow
It does not detect carry out of 6 or 32 bit operation.

Table 30 shows the data sizes supported by the load operation.

[0186]

[Table 46]

The architecture specifies memory address alignment to be on data type boundaries. That is, there is no alignment requirement for bytes. The alignment requirement for a Huffword is a Huffword boundary. The alignment requirement for a word is a word boundary.

Table 31 shows the data sizes supported by the store operation.

[0189]

[Table 47]

Since one or more dam types are mapped to registers as scalars or vectors, there must be bits in the destination register that have undefined results for some data types. Can be.
Actually, in addition to the byte 9 data size operation for the vector destination register and the word data size operation for the scalar destination register, there are bits in the destination register whose values are not defined by the operation. For these bits, the architecture specifies that their values be in an undefined state. Table 32 shows the undefined bits for each data size.

[0191]

[Table 48]

The programmer must know the source and destination registers or the data type of the memory during programming. Data type conversion from one element size to another element size temporarily stores a different number of elements in the vector register. For example, a vector register conversion of a Huff word to a word data type requires two registers to store the same number of converted elements. Conversely, conversion from the word data type, which can have a user-defined format in the vector register, to the Huffword format, produces the same number of elements in half the vector register and the remaining bits in the other half. . In either case, the data type conversion produces a structured issue with an array of converted elements having a different size than the source element.

In principle, the MSP architecture does not provide operations that secretly change the number of elements as a result. The architecture determines that the programmer knows the order in which to change the number of elements in the destination register.
The architecture provides operations to convert from one data type to another data type of the same size, and allows the programmer to adjust for data size differences when converting from one data type to another of a different size. Request.

VSHFLLL and VU described in Appendix E
Special instructions such as NSHFLL simplify the conversion from a vector having a first size to a second vector having a second data size. The basic steps involved in converting a two's complement data type from a vector VRa, eg, a smaller element size int8, to a larger size int16, for example, are as follows.

1. Elements in VRa having different vectors VRb are shuffled into two vectors (VRc: VRd) using a byte data type. VRa
Is a double size register (VRc: V
The element is moved to the lower byte of the int16 data element in Rd), and the element of VRb not related to the value is moved to the upper byte of VRc: VRd. This operation effectively moves one half of the VRa element to VRc and the other half to VRd while the size of each element is doubled from bytes to Huffwords.

The elements at 2.8 bits in VRc: VRd are arithmetically shifted to sign extend them.

The basic steps involved in converting a two's complement data type from a vector VRa, eg, a larger element size int16, to a smaller size int8, for example, are as follows.

1. Check to ensure that each element of int16 data type can be represented in byte size. If necessary, saturate the elements at both ends to fit the smaller size.

2. Unshuffle elements in VRa with different vectors VRb into two vectors VRc: VRd. The upper half of each element in VRa and VRb is moved to VRc, and the lower half is moved to VRd. This is the lower one of all elements of VRa
/ 2 is effectively collected in the lower half of VRd.

Special instructions are provided for the following data type conversions: int32 to single precision floating point; single precision floating point to fixed point (XY note); single precision floating point to int32. Int8 to Int9; in
t9 to int16; and int16 to int9.

Most vector instructions use element masks to perform operations only on elements selected from within the vector to provide room for vector programming. Vector global mask register
(Vector Global Mask Register: VGMR0, VGMR
1) identifies the elements to be modified in the vector accumulator and destination register by the vector instruction. VGMR0 for byte and byte 9 data size operations
(Or VGMR1) each of the 32 bits identifies the element to be operated on. Set bit (VGM
R0 (i) is a byte-sized element (i, where i
Indicates that 0 to 31) are affected. Each VGMR0 (or VGMR1) 32-bit pair identifies the element to be operated on for Huffword data size operation. The bit VGMR0 (2i: 2) in the set state
i + 1) indicates that the element (i, where i is from 0 to 15) is affected. If only one bit of a pair is set for a Huffword data size operation in VGMR0, only that bit is modified in the corresponding byte. Each VGMR0 (or VGMR1) 4-bit set identifies the element to be operated on for word data size operation. The bit VGMR0 (4i: 4i + 3) in the set state includes the element (i,
Where i is from 0 to 7). If in VGMR0 not all bits of the 4-bit set are set for word data size operation,
Only that bit is modified in the corresponding byte.

VGMR0 and VGMR1 are vector or scalar registers or VCMPV.
It can be set by comparing to the immediate value using the instruction. This instruction sets the mask appropriately according to the specified bit size. Since a scalar register is defined to contain only one data element, scalar operations (ie, the destination register is a scalar) are not affected by the element mask.

To provide room for vector programming, most MSP instructions support three forms of vector and scalar operations. They are as follows: Vector = vector op vector 2. Vector = vector op scalar Scalar = scalar op scalar In case 2 where the scalar register is specified as a B operand, a single element in the scalar register is copied as many times as required to match as many elements in the vector A overland. The duplicated element has the same value as the element in the specified scalar operand. A scalar operand can be in the form of an immedoate operand from a scalar register or instruction. In the case of the immediate obland, if the specified data type uses a data size that is larger than the useful value of the immediate field size, an appropriate sign-extension is added.

Many multimedia applications require special attention to the precision of the source, intermediate and final results. Moreover, the integer multiply instruction produces a "double precision" intermediate result that can be stored in a two vector register.

The MSP architecture is currently 8, 9, 1
2's complement integer format for 6 and 32 bit elements and IEEE 7 for 32 bit elements
Supports 54 single precision formats. Overflow is defined to result in more than the most positive or most negative value that can be represented by the specified data type. When an overflow occurs, the value recorded in the destination register is not a valid number. Underflow is defined only for floating point operations.

If not otherwise, all floating point operations use one of the four rounding modes specified by the bits (VCSR <RMODE). Some instructions use what is known as round away from the zero (round even) rounding mode.

Saturation is an important feature in many multimedia applications. The MSP architecture supports saturation for all four integer and floating point operations. Bit ISAT in register VCSR specifies the integer saturation mode. The floating point saturation mode, known as the fast IEEE mode, is specified in the FCSR bit in the VCSR.
When saturation mode is enabled, results that are greater than or equal to the most positive or most negative value are set to the most positive or most negative value, respectively. No overflow can occur in this case and the overflow bit cannot be set.

Table 33 shows a list of Precise Exceptions that are detected and reported before executing the faulty instruction.

[0209]

[Table 49]

Table 34 shows that an inexact exception (Imprecise Exc.) Detected and reported after executing a numbered instruction that is later in the program order than the defective instruction.
2 shows a list for the eption).

[0211]

[Table 50]

[Appendix E] The instruction set for the vector processor includes 11 classes as shown in Table 35.

[0213]

[Table 51]

[0214]

[Table 52]

Table 36 shows the flow control (Flow Control).
l) Show a list for instructions.

[0216]

[Table 53]

Logical classification supports Boolean data types and is affected by element masks. Table 37 is a list of logic instructions.

[0218]

[Table 54]

The shift / rotate classification instruction operates on int8, int9, int16 and int32 data types (not float data types),
Affected by element mask. Table 38 is a list of shift / rotate classification instructions.

[0220]

[Table 55]

Arithmetic classification instructions are generally int
Supports 8, int9, int16, int32, and flow data types and is affected by element masks. See the detailed description of each instruction below for any special restrictions on unsupported data types. V
The CMPV instruction is not affected by the element mask because it operates on the element mask. Table 39
Is an arithmetic operation instruction list.

[0222]

[Table 56]

The MPEG instruction is an instruction class particularly suitable for MPEG encoding and decoding, but can be used in various ways. MPEG instructions are int8, int9,
Supports int16 and int32 data types and is affected by element masks. Table 40 is MPEG
This is an instruction list.

[0224]

[Table 57]

Each data type conversion (Data Type Conversio)
n) Instructions support special data types and are not affected by element masks because the architecture does not support more than one data type in registers. Table 41
Is a data type conversion instruction list.

[0226]

[Table 58]

Inter-element arithmetic
Arithmetic) Classification instructions are int8, int9, int1
Supports 6, int32 and flow data types. Table 42 is an inter-element arithmetic classification instruction list.

[0228]

[Table 59]

[0229] Inter-element M
ove) The sort instruction supports byte, byte 9, huff word and word data sizes. Table 43 is an inter-element move classification instruction list.

[0230]

[Table 60]

The Load / Store instruction supports the byte, Huffword, and Word data sizes plus the data size operation associated with the special byte 9 and is unaffected by the element mask. Table 44 is a list of load / store classification instructions.

[0232]

[Table 61]

Most Register Moves
Instructions support int8, int9, int16, int32 and flow data types and are unaffected by element masks. However, the VCMOVM instruction is affected by the element mask. Table 45 is an instruction list of the register move classification.

[0234]

[Table 62]

Table 46 is a list of instructions of a cache operation classification for controlling the cache subsystem 130.

[0236]

[Table 63]

Instruction Description Nomenclature To simplify the description of the instruction set, special terms are used throughout the appendix. For example, the instruction operand is a signed two's complement integer of byte, byte 9, Huffword or word size, unless otherwise noted.
The word "register" is used to refer to a general purpose (scalar or vector) register. Other types of registers are explicitly described. In the assembly language syntax, the suffixes b, b9, h and w are the data size (bytes, bytes 9, huff words, and words) and integer data types (int8, int9, int16, and in).
t32). Also, instruction operands, operations,
The terms and symbols used in the description of the assembly language syntaxes are as follows.

Rd destination register (vector,
Scalar or special purpose) Ra, Rb source register (a, b) (vector,
Scalar or special purpose) Rc Source or destination register (c) (vector or scalar) Rs Store data source register (vector or scalar) S 32-bit scalar or special purpose register VR Current bank vector register VRA Alternative bank vector register VR0 Bank 0 vector Register VR1 Bank 1 vector register VRd Vector destination register (default for current bank unless VRA is specified) VRa, VRb Vector source register (a and b) VRc Vector source or destination register (c) VRs Vector store data source register VAC0H vector Accumulator register 0 high VAC0L Vector accumulator register 0 low VAC1H Vector accumulator register 1 High VAC1L Vector accumulator register 1 Low SRd Scalar purpose register SRa, SRb Scalar source register (a and b) SRb + Update base register with effective address SRs Scalar store data source register SP Special purpose register VR [i] i in vector register VR Bit [a] (a: b) of the i-th element in the vector register VR (ab) VR [i] (msb) Most significant bit of the element i in the vector register VR EA Effective address for MEM memory BYTE [EA] 1 byte of memory addressed by EA HALF [EA] Huff word of memory addressed by EA. Bits (15: 8) are addressed by EA + 1.

WORD [WA] Word of memory addressed by EA. Bits (31:24) are EA
Addressed by +3.

NumElem Indicates the number of elements for a given data type. It is 32, 16, or 8 for byte, byte 9, huffword, or word data size, respectively, in VEC32 mode. It is 6 bytes for byte, byte 9, huff word or word data size in VEC64 mode, respectively.
4, 32, or 16. Nu for scalar operation
mElem is 0.

EMASK [i] Indicates the element mask for the i-th element. It is VGMR0 / 1 to VGMR0 / 1, VGMR for byte, byte 9, Huffword or word data size respectively.
0/1, or ~ VGMR0 / 1 indicates 1, 2, or 4 bits. In the case of a scalar operation, EMASK [i] = 0
However, it is estimated that the element mask has been set.

MMASK [i] Indicates the element mask for the i-th element. It indicates 1, 2, or 4 bits in VMMR0 or VMMR1, respectively, for byte, byte 9, Huffword, or word data size.

VCSR Vector control and status register VCSR (x) One bit or a plurality of bits is indicated by VCSR. “X” is a field name.

VPC Vector Processor Program Counter VECSIZE The vector register size is VEC3
2 for 32 and 64 for VEC64 mode.

The SPAD scratchpad C programming construct is used to describe the control flow of the operation. Exceptions are summarized as follows:

= Assignment: consentation {x {y} indicating selection between x and y (not logical or) sex sign-extend to specific data size sex-dp specific data size Sign-extend with double precision zex zero-extend to specific data size zero zero-extended (logical) move right shift left (zero fill) trnc7 truncate 7 leading bits (from Huffword) trac1 leading 1 Truncate bit (from byte 9)% Modulo operator | Expression | Absolute value of expression / Divide (use one of 4 IEEE rounding modes for float data type) // Divide (Zero rounding mode to round away (round away)) for saturated integer data types Or it saturates to the most positive value. For the float data type, saturation can be done to positive infinity, positive zero, negative zero, or negative infinity.

The general instruction format is shown in FIG. 12 and is described below.

The REAR format is used by load, store and cache operation instructions, where the fields have the following meanings as given in Table 47.

[0249]

[Table 64]

Bits 17:15 are reserved.
The architecture should be zero to ensure interchangeability in future extensions. B: Coding with D and TT fields is not defined.

Programmers should not use such encodings because the architecture does not specify the expected results when such encodings are used. Table 4
8 supported in VEC32 and VEC64 modes (LT
A scalar load operation (encoded in the TT field as).

[0252]

[Table 65]

Table 49 shows the vector load operations supported in VEC30 mode (encoded in the TT field as LT) when bit VCSR (0) is clear.

[0254]

[Table 66]

The B bit is used to indicate the current or replacement bank.

Table 50 shows the vector load operations supported in VEC64 mode (encoded in the TT field as LT) when bit VCSR (0) is clear.

[0257]

[Table 67]

Since the concept of the current and replacement banks does not exist in the VEC64 mode, bit B is used to indicate a 64-byte vector operation.

Table 51 is a list of scalar store operations supported (encoded in the TT field as LT) supported in VEC32 and VEC64 modes.

[0260]

[Table 68]

Table 52 is a list of vector store operations supported (encoded in field TT as LT) supported in VEC32 mode when bit VCSR (0) is clear.

[0262]

[Table 69]

Table 53 supports the VEC64 mode when bit VCSR (0) is set (T as LT
5 is a vector store operation list (encoded in the T field).

[0264]

[Table 70]

Since the concept of the current and replacement banks does not exist in the VEC64 mode, bit B is used to indicate a 64-byte vector operation.

The REAI format is used by the load, store and cache operation instructions, where the fields have the following meanings as given in Table 54.

[0267]

[Table 71]

The REAR and REAI formats apply the same coding to the transfer type. For details on encoding, refer to the REAR format.

The RRRM5 format provides three or two registers and a 5-bit immediate operand.
Table 55 defines the fields for the RRRM5 format.

[0270]

[Table 72]

The bits 19:15 are RESERVED and should be zero to ensure compatibility with future extensions in the architecture.

All vector register operands are in the current bank (bank 0 or bank 1) unless otherwise specified.
Can be referred to). Table 56 shows DC (1:
When 0) is 00, 01, or 10, it is a D: S: M encoding table.

[0273]

[Table 73]

When DS (1: 0) is 11, D: S: M
The encoding has the meaning shown in Table 57 below.

[0275]

[Table 74]

The RRRR format provides four register operands.

Table 58 shows the fields in RRRR format.

[0278]

[Table 75]

All vector register operands are in the current bank (bank 0 or bank 1) unless otherwise specified.
Can be).

The R1 format is only used by load immediate instructions. Table 59 shows the fields in RI format.

[0281]

[Table 76]

F: The coding with the DS (1: 0) field is not defined. Programmers should not use such encodings, as the architecture does not specify the expected behavior when such encodings are used.
The value loaded into Rd depends on the data type as shown in Table 60.

[0283]

[Table 77]

The CT format includes the fields shown in Table 61.

[0285]

[Table 78]

The branch condition is VCSR [GT: EQ: L
T] field.

The overflow condition uses the VCSR [S0] bit, which, when set, precedes the GT, EQ, and LT bits. VCCS and VCBARR interpret the Cond (2: 0) field differently from the above.
Please refer to the detailed instruction explanation.

The RRRM9 format specifies 3 or 2 registers and a 9-bit immediate operand.
Table 62 shows the fields of the RRRM9 format.

[0289]

[Table 79]

When the D: S: M encoding does not specify an immediate operand, bits 19:15 are reserved and should be zero to ensure future compatibility.

All vector register operands refer to the current (can be bank 0 or bank 1) unless otherwise. Tables 56 and 57 for the RRRM5 format except that the D: S: M encoding is affected by DS (1: 0) encoding as shown in Table 63, with the immediate values extracted from the immediate field.
Is the same as that shown in FIG.

[0292]

[Table 80]

The immediate format is not useful for float data types.

The MSP vector instructions are shown in the following alphabetical order. Notes: The instruction is affected by the element mask unless another state exists. CT format instructions are not affected by the element mask. REAR and REAI format instructions consisting of load, store, and cache instructions are also unaffected by the element mask.

2.9-bit immediate operands are not useful for float data types.

[0296] 3. In the description of the operation, only the vector form is given. In the case of a scalar operation, it is assumed that only the 0th element is defined.

[0297] 4. For the RRRM5 and RRRM9 formats, the encodings shown in Table 64 below are used for integer data types (b, b9, h, w).

[0298]

[Table 81]

[0299] 5. For RRRM5 and RRRM9 formats, the encoding shown in Table 65 below is used for the float data type.

[0300]

[Table 82]

6. Int8, int9, int6, in for all instructions that may cause overflow
The limit value of t32 maximum value or minimum value is VCSR (ISA
T) Applied when the bit is set. Thus, the floating point result is saturated to -infinity, -zero, + zero, or + infinity when the VCSR (ISAT) bit is set.

7. Syntactically. .n indicates the byte 9 data size. It can be used instead of b9.

[0303] 8. The floating point result returned to the destination register or vector accumulator for all instructions is in IEEE 754 single precision format. Floating point results are recorded in the lower part of the accumulator and the upper part is not modified.

VAAS3 Addition and (1,0,1) Addition

[0305]

[Table 83]

Assembler syntax VAAS3. dt VRd, VRa, VRb VAAS3. dt VRd, VRa, SRb VAAS3. dt SRd, SRa, SRb where dt = {b, b9, h, w}

[0307]

[Table 84]

Description The contents of the vector / scalar register Ra are added to Rb to generate an intermediate result, and the final result obtained by adding the sign of Ra to the intermediate result is stored in the vector / scalar register Rd.

[0309] Exception Overflow VADAC Addition and accumulation

[0310]

[Table 85]

Assembler syntax VADAC. dt VRc, VRd, VRa, VRb VADAC. dt SRc, SRd, SRa, SRb where dt = {b, b9, h, w}.

[0312]

[Table 86]

Description Ra and Rb add each element of the operand to each double precision element of the vector accumulator, and store the double precision sum of each element in the vector accumulator and the target registers Rc and Rd. Ra and R
b uses the specified data type, while VAC uses the appropriate double precision data type (int8, int, respectively).
16, 18, for 9, int16 and int32
32 and 64 bits). The upper part of each double precision element is stored in VACH and Rc.
If Rc = Rd, the result of Rc is undefined.

Operation for (i = 0; i <NumElem && EMASK [i]; i ++) ｛Aop [i] = {VRa [i] ‖SRa｝; Bop [i] = ｛VRb [i] ‖SRb｝; VACH [i]: VACL [i] = sex (Aop [i] + Bop [i] + VACH [i]: VACL [i]; Rc [i] = VACH [i]; Rd [i] = VACL [i ]; ＡＤ VADACL addition and low accumulation

[0315]

[Table 87]

Assembler syntax VADACL. dt VRd, VRa, VRb VADACL. dt VRd, VRa, SRb VADACL. dt VRd, VRa, #IMM VADACL. dt SRd, SRa, SRb VADACL. dt SRd, SRa, #IMM where dt = {b, b9, h, w}.

[0317]

[Table 88]

Description Each element of the Ra and Rb / immediate operands is added to each extended precision element of the vector accumulator, and the lower precision is added to the destination register (R
Return to d). While Ra and Rb / immediate use the specified data type, VAC uses the appropriate double precision data type (int8, int9, int16,
And int32 for 16, 18, 32, and 64 bits). The upper part of each extended precision element is stored on the VACH.

Operation for (i = 0; i <NumElem && EMASK [i]; i ++) ｛Bop [i] = ｛VRb [i] ‖SRb‖sex (IMM <8: 0>)｝; VACH [i] : VACL [i] = sex (Ra [i] + Bop [i] + VACH [i]: VACL [i]; Rd [i] = VACL [i]; Ｖ VADD addition

[0320]

[Table 89]

Assembler syntax VADD. dt VRd, VRa, VRb VADD. dt VRd, VRa, SRb VADD. dt VRd, VRa, #IMM VADD. dt SRd, SRa, SRb VADD. dt SRd, SRa, #IMM where dt = {b, b9, h, w, f}.

[0322]

[Table 90]

Description Adds Ra and Rb / immediate operands and returns the sum to destination register Rd.

Operation for (i = 0; i <NumElem && EMASK [i]; i ++) ｛Bop [i] = ｛VRb [i] ‖SRb‖sex (IMM <8: 0>)｝; Rd [i] = Ra [i] + Bop [i]; 例外 Exception Overflow, floating-point invalid operand VADDH Addition of adjacent cell elements

[0325]

[Table 91]

Assembler syntax VADDH. dt VRd, VRa, VRb VADDH. dt VRd, VRa, SRb where dt = {b, b9, h, w}.

[0327]

[Table 92]

[0328]

[Table 93]

Operation for (i = 0; i <NumElem-1; i ++) ｛Rd [i] = Ra [i] + Ra [i + 1];; Rd [NumElem-1] = Ra [NumElem-1] + {VPb [0]} SRb}; Exception Overflow, floating-point invalid operand Programming note This instruction is not affected by the element mask.

[0330] VAND AND

[0331]

[Table 94]

Assembler syntax VAND. dt VRd, VRa, VRb VAND. dt VRd, VRa, SRb VAND. dt VRd, VRa, #IMM VAND. dt SRd, SRa, SRb VAND. dt SRd, SRa, #IMM where dt = {b, b9, h, w},. w and. Note that f specifies the same operation.

[0333]

[Table 95]

Description Logically AND the Ra and Rb / immediate operands and return the result to the destination register Rd.

Operation for (i = 0; i <NumElem && EMASK [i]; i ++) ｛Bop [i] = ｛VRb [i] ‖SRb‖sex (IMM <8: 0>)｝; Rd [i] <k> = Ra [i] <k>& Bop [i] <k>, k = for all bits in element i;｝ No exception VANDC complement AND

[0336]

[Table 96]

Assembler syntax VANDC. dt VRd, VRa, VRb VANDC. dt VRd, VRa, SRb VANDC. dt VRd, VRa, #IMM VANDC. dt SRd, SRa, SRb VANDC. dt SRd, SRa, #IMM where dt = {b, b9, h, w},. w and. Note that f specifies the same operation.

[0338]

[Table 97]

Description The complement of Ra and Rb / immediate operand is logically ADN.
Then, the result is returned to the destination register Rd.

Operation for (i = 0; i <NumElem && EMASK [i]; i ++) ｛Bop [i] = ｛VRb [i] ‖SRb‖sex (IMM <8: 0>)｝; Rd [i] <k> = Ra [i] <k>& -Bop [i] <k>, k = for all bits in element i;｝ Exceptions None VASA arithmetic accumulator move

[0341]

[Table 98]

Assembler syntax VASAL. dt VASAR. dt Here, dt = {b, b9, h, w}, and R indicates the left or right rotation direction.

[0343]

[Table 99]

Description Each data element of the vector accumulator register is shifted one bit position to the left with zerofill from the right (if R = 0) or one bit position to the left with sign-extension. Moved (if R =
1). This result is stored in the vector accumulator.

Operation for (i = 0; i <NumElem && EMASK [i]; i ++) ｛if (R = 1) VACOH [i]: VACOL [i] = VACOH [i]: VACOL [i] sign >>1; else VACOH [i]: VACOL [i] = VACOH [i]: VACOL [i] <<1; 例外 Exception Overflow VASL Move arithmetic left

[0346]

[Table 100]

Assembler syntax VASL. dt VRd, VRa, SRb VASL. dt VRd, VRa, #IMM VASL. dt SRd, SRa, SRb VASL. dt SRd, SRa, #IMM where dt = {b, b9, h, w}.

[0348]

[Table 101]

Description Each data element of the vector / scalar register Ra is filled with zeros from the right side and moved to the left by the moving amount given to the scalar register Rb or the IMM field, and the result is stored in the vector / scalar register Rd. . For those elements that cause overflow, the result saturates to the maximum explicit or negative value depending on their sign. The amount of movement is defined to be an unsigned integer.

Operation shift_amount = ｛SRb% 32‖IMM <4: 0>｝; for (i = 0; i <NumElem && EMASK [i]; i ++) ｛Rd [i] = saturate (Ra [i] << ＿ 注意 移動 移動 な し ＿ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ ＿ ＿ ＿ ＿ ＿ ＿ ＿ ＿ ＿ ＿ ＿ ＿ ＿ ＿ ＿ ＿ ＿ ＿ ＿ ＿ ＿ ＿ ＿ ＿ ＿ ＿ ＿ ＿ ＿ ＿ ＿ ＿ ＿ ＿. It is obligatory to specify exactly the same or smaller amount of movement: if the amount of movement is greater than the specified data size, the element is zero-filled.

VASR Arithmetic Move Right

[0352]

[Table 102]

Assembler syntax VASR. dt VRd, VRa, SRb VASR. dt VRd, VRa, #IMM VASR. dt SRd, SRa, SRb VASR. dt SRd, SRa, #IMM where dt = {b, b9, h, w}.

[0354]

[Table 103]

Description Each data element of the vector / scalar register Ra is sign-extended at the most significant bit position and arithmetically moved right by the amount of movement given to the least significant bit of the scalar register Rb or IMM field, The result is stored in the vector / scalar register Rd. The amount of movement is defined to be an unsigned integer.

Operation shift_amount = ｛SRb% 32‖IMM <4: 0>｝; for (i = 0; i <NumElem && EMASK [i]; i ++) ｛Rd [i] = Ra [i] sign >> shift_amount ｝; 例外 無 し 無 し 無 し プ ロ グ ラ ミ ン グ 注意 プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ 注意 プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ; 注意 無 し プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ 注意 注意 プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グ プ ロ グ ラ ミ ン グByte, byte 9,
For the Huffword data type, the programmer has an obligation to specify exactly the same amount of movement that is less than or equal to the number of bits of the data size. If the displacement is larger than the specified data size, the element is filled with sign bits.

The VASS3 addition and (−1,
Sign subtraction of 0,1)

[0358]

[Table 104]

Assembler syntax VASS3. dt VRd, VRa, VRb VASS3. dt VRd, VRa, SRb VASS3. dt SRd, SRa, SRb where dt = {b, b9, h, w}.

[0360]

[Table 105]

Description The intermediate result is added to Rb of the vector / scalar register Ra to generate an intermediate result, and the final result obtained by subtracting the sign of Ra from the intermediate result is the vector / scalar register Rd.
Is stored.

Operation for (i = 0; i <NumElem && EMASK [i]; i ++) ｛if (Ra [i]> 0) extsgn3 = 1; else if (Ra [i] <0) extsgn3 = −1; else extsgn3 = 0; Rd [i] = Ra [i] + Rb [i]-extsgn3;｝ Exceptions Overflow Absub Absolute value of subtraction

[0363]

[Table 106]

Assembler syntax VASUB. dt VRd, VRa, VRb VASUB. dt VRd, VRa, SRb VASUB. dt VRd, VRa, #IMM VASUB. dt SRd, SRa, SRb VASUB. dt SRd, SRa, #IMM where dt = {b, b9, h, w}.

[0365]

[Table 107]

Description The contents of the vector / scalar register Rb or the IMM field are subtracted from the contents of the vector / scalar register Ra, and the absolute value is stored in the vector / scalar register Rd.

[0367] Exceptions Overflow, floating-point invalid operand Programming notes If the result of the subtractor is the largest implicit, an overflow occurs after the absolute operation. If saturation mode is enabled, the result of the absolute value operation will be the largest positive number.

VAVG Two Element Average

[0369]

[Table 108]

Assembler syntax VAVG. dt VRd, VRa, VRb VAVG. dt VRd, VRa, SRb VAVG. dt SRd, SRa, SRb where dt = {b, b9, h, w, f} and use VAVGT to specify the "truncated" rounding mode for integer data types.

[0371]

[Table 109]

Description The contents of vector / scalar register Ra are added to the contents of vector / scalar register Rb to generate an intermediate result,
Then the intermediate result is divided by 2 and the final result is stored in the vector / scalar register Rd. If T = 1 for an integer data type, rounding mode is aborted and T =
If 0, round down from zero (default). In the case of the float data type, the rounding mode is specified in VCSR (RMODE).

[0373] Exception None VAVGH Average of two adjacent elements

[0374]

[Table 110]

Assembler syntax VAVGH. dt VRd, VRa, VRb VAVGH. dt VRd, VRa, SRb where dt = {b, b9, h, w, f} and use VAVGHT to specify the "truncated" rounding mode for integer data types.

[0376]

[Table 111]

[0377]

[Table 112]

Operation for (i = 0; i <NumElem-1; i ++) ｛Rd [i] = (Ra [i] + Ra [i + 1]) // 2;｝ Rd [NumElem-1] = ( Ra [NumElem-1] + {VRb [0] {SRb}) // 2; Exceptions None Programming note This instruction is not affected by the element mask.

VAVGQ Quadruple Average

[0380]

[Table 113]

Assembler syntax VAVGQ. dt VRd, VRa, VRb where dt = {b, b9, h, w} and use VAVGQT to specify the "truncated" rounding mode for integer data types.

[0382]

[Table 114]

[0383]

[Table 115]

Operation for (i = 0; i <NumElem-1; i ++) ++ Rd [i] = (Ra [i] + Rb [i] + (Ra [i + 1] + Rb [i + 1]) // 4;｝ No exception VCACHE Cache operation

[0385]

[Table 116]

Assembler syntax VCACHE. fc SRb, SRi VCACHE. fc SRb, #IMM VCACHE. fc SRb +, SRi VCACHE. fc SRb +, #IMM where fc = {0, 1}.

[0387]

[Table 117]

Operation Exceptions None Programming Notes This instruction is not affected by the element mask.

VCAND Complementary Addition

[0390]

[Table 118]

Assembler syntax VCAND. dt VRd, VRa, VRb VCAND. dt VRd, VRa, SRb VCAND. dt VRd, VRa, #IMM VCAND. dt SRd, SRa, SRb VCAND. dt SRd, SRa, #IMM where dt = {b, b9, h, w} and. w and.
Note that f specifies the same operation.

[0392]

[Table 119]

Description The complements of Ra and Rb / immediate operands are logically ANDed.
Then, the result is returned to the destination register Rd.

Operation for (i = 0; i <NumElem && EMASK [i]; i ++) ｛Bop [i] = ｛VRb [i] ‖SRb ‖sex (IMM <8: 0>)｝; Rd [i] <k> = -Ra [i] <k>& Bop [i] <k>, k = for all bits in element i;｝ Exception None VCBARR Conditional barrier

[0395]

[Table 120]

Assembler syntax VCBARR. cond Here, cond = {0, -7}, and each condition is given later by a symbol.

[0397]

[Table 121]

During the operation (Cond = true), all subsequent instructions are stopped.

Exceptions None Programming Notes This instruction is provided to software to enforce serialization of instruction execution. This instruction is used to provide accurate reporting of confidential exceptions. For example, if this instruction is used immediately after an arithmetic instruction that may cause an exception, the exception is reported to the program counter addressing the instruction.

VCBR Conditional Branch

[0401]

[Table 122]

[0402] Assembler syntax VCBR. cond #Offset where cond = {un, lt, eq, le, gt,
ne, ge, ov｝.

Description If Cond is true, branch. This is not a delayed branch.

[0404] Exception Instruction address invalid VCBRI Conditional indirect branch

[0405]

[Table 123]

Assembler syntax VCBRI. cond SRb where cond = {un, lt, eq, le, gt,
ne, ge, ov｝.

Description If Cond is true, branch. This is not a delayed branch.

[0408] Exception Instruction address invalid VCCS Conditional context switch

[0409]

[Table 124]

Assembler Syntax VCCS #Offset Description If VIMSK (cse) is true, jump to the context switch subroutine. This is not a delayed branch. If VIMSK (cse) is true, VPC +
4 (return address) is saved on the return address stack. If not, execution is VPC + 4
Continue with.

[0411] Exception Address stack overflow return VCHGCR Control register change

[0412]

[Table 125]

[0413] Assembler syntax VCHGCR Mode

[0414]

[Table 126]

Operations Exceptions None Programming Notes This instruction is provided to change the control bits in the VCSR in a more efficient manner than the hardware worked with the VMOV instruction.

[0416] VCINT Conditional ARM7 In
Taraput

[0417]

[Table 127]

Assembler syntax VCINT. cond #CODE where cond = {un, lt, eq, le, gt,
ne, ge, ov｝.

Description If Cond is true, stop execution and interrupt ARM7 if enabled.

Operation If ((Cond = VCSR [SO, GT, EQ, LT]) | (Cond == un)) ｛VISRC <vip> = 1; VIINS = [VCINT.cond #ICODE instruction]; VEPC = VPC ; if (VIMSK <vie> == 1) signal ARM7 interrupt; VP STATE = VP IDLE;｝ else VPC = VPC + 4; Exception VCINT interrupt VCJOIN Conditional with ARM7 task
Combination

[0421]

[Table 128]

Assembler syntax VCJOIN. cond #Offset where cond = {un, lt, eq, le, gt,
ne, ge, ov｝.

Description If Cond is true, stop execution and interrupt ARM7 if enabled.

Operation If ((Cond = VCSR [SO, GT, EQ, LT]) | (Cond = un)) ｛VISRC <vjp>=-1; VIINS = [VCJOIN.cond #Offset instruction]; VEPC = VPC ; if (VIMSK <vje> == 1) signal ARM7 interrupt; VP STATE = VP IDLE;｝ else VPC = VPC + 4; Exception VCJOIN interrupt VCJSR Conditional access to subroutine
Pump

[0425]

[Table 129]

Assembler syntax VCJSR. cond #Offset where cond = {un, lt, eq, le, gt,
ne, ge, ov｝.

Description If Cond is true, jump to subroutine. This is not a delayed branch.

If Cond is true, VPC + 4
(Return address) is saved on the return address stack. If not, execution continues at VPC + 4.

Operation If ((Cond == VCSR [SO, GT, EQ, LT]) | (Cond == un)) ｛if (VSP <4 >> 15) ｛VISRC <RASO> = 1; signal ARM7 with RASO exception; VP STATE = VP IDLE;｝ else ｛RSTACK [VSP <3: 0>] = VPC + 4; VSP <4: 0> = VSP <4: 0>+1; VPC = VPC + sex (Offset <22: 0> ^* 4) ;｝｝ Else VPC = VPC + 4; Exception Address stack overflow return VCJSRI Conditional indirect to subroutine
Jump

[0430]

[Table 130]

[0431] Assembler syntax VCJSRI. cond SRb where cond = {un, lt, eq, le, gt,
ne, ge, ov｝.

Description If Cond is true, an indirect jump is made to a subroutine. This is not a delayed branch.

If Cond is true, VPC + 4
(Return address) is saved on the return address stack. If not, execution continues at VPC + 4.

Operation If ((Cond == VCSR [SO, GT, EQ, LT]) | (Cond = un)) ｛if (VSP <4: 9> 15) ｛VISRC <RASO> = 1; signal ARM7 with RASO exception; VP STATE = VP IDLE;｝ else ｛RSTACK [VSP <3: 0>] = VPC + 4; VSP <4: 0> = VSP <4: 0>+1; VPC = SRb <31: 2>: b'OO;｝｝ else VPC = VPC + 4; Exception Address stack overflow return VCMOV Conditional move

[0435]

[Table 131]

Assembler syntax VCMOV. dt Rd, Rb, cond VCMOV. dt Rd, #IMM, cond where dt = {b, b9, h, w, f}, cond =
｛Un, lt, eq, le, gt, ne, ge, o
v｝,. f and. w is. Specify the same operation except that the f data type is not supported by the 9-bit immediate operand.

[0437]

[Table 132]

[0438]

[Table 133]

Operation If ((Cond = VCSR [SOV, GT, EQ, LT]) | (Cond == un)) for (i = 0; i <NumElem; i ++) Rd [i] == ｛Rb [i ] ‖SRb ‖sex (IMM <8: 0>)｝; Exception None Programming Note This instruction is not affected by the element mask,
VCMOVM is affected by the element mask. The floating point precision representation extended with the vector accumulator uses all 576 bits for 8 elements. Therefore, a vector register move that includes an accumulator is. b9 Data size should be specified.

[0440] The VCMOVM element mask is
Conditional move with

[0441]

[Table 134]

Assembler syntax VCMOVM. dt Rd, Rb, cond VCMOVM. dt Rd, #IMM, cond where dt = {b, b9, h, w, f}, cond =
｛Un, lt, eq, le, gt, ne, ge, o
v｝,. f and. w is. Specify the same operation except that the f data type is not supported by the 9-bit immediate operand.

[0443]

[Table 135]

[0444]

[Table 136]

Operation If ((Cond = VCSR [SO, GT, EQ, LT]) | (Cond = un)) for (i = 0; i <NumElem;&& MMASK [i]; i ++) Rd [i] = ｛Rb [i] ‖SRb ‖sex (IMM <8: 0>)｝; Exceptions None Programming notes This instruction is affected by the VMMR element mask, -VCMOV is not affected by the element mask. The floating point precision representation extended with the vector accumulator uses all 576 bits for 8 elements. Therefore, a vector register move that includes an accumulator is. b9 Data size should be specified.

[0446] VCMPV Comparison and Mask Set
G

[0447]

[Table 137]

The assembler syntax VCMPV. dt VRd, VRb, cond. mas
k VCMPV. dt VRd, SRb, cond. mas
k where dt = {b, b9, h, w, f}, cond =
｛Un, lt, eq, le, gt, ne, ge, o
v}, mask = {VGMR, VMMR}, if no mask is specified, VGMR is virtual.

[0449]

[Table 138]

Description The contents of the vector registers VRa and VRb are subtracted (V
By performing Ra [i] -VRb [i], comparison is performed in an elemental manner, and VGMR (if K = 0) or VMM
The corresponding bit (#i) in the R (if K = 1) register is set if the result of the comparison matches the Cond field of the VCMPV instruction. For example, if the Cond field is smaller than LT, VGMR [i] (or V
MMR [i]) is set when VRa [i] <VRb [i].

Operation for (i = 0; i <NumElem; i ++) ｛Bop [i] = ｛Rb [i] ‖SRb‖sex (IMM <8: 0>)｝; relationship [i] = Ra [i] Bop [i]; if (k = 1) MMASK [i] = (relationship [i] == Cond)? True: False; else EMASK [i] = (relationship [i] == Cond)? True: False ; Exceptions None Programming Notes This instruction is not affected by the element mask.

VCNTLZ Leading zero count

[0453]

[Table 139]

Assembler syntax VCNTLZ. dt VRd, VRb VCNTLZ. dt SRd, SRb where dt = {b, b9, h, w}.

[0455]

[Table 140]

Description The number of leading zeros is counted for each element of Rb, and the count is returned to Rd.

Operation for (i = 0; i <NumElem && EMASK [i]; i ++) ｛Rd [i] = number of leading zeroes (Rb [i]);｝ Exceptions None Programming attention All bits of element are zero , The result is the element size (8, 9, 16, or 32 for bytes, bytes 9, huff words, or words, respectively)
Is the same as The leading zero count is inversely related to the element position index (if used next to the VCMPR instruction). NumElem to V for a given data type to convert element position
Subtract the result of CNTLZ.

VCOR Complement's OR

[0459]

[Table 141]

The assembler syntax VCOR. dt VRd, VRa, VRb VCOR. dt VRd, VRa, SRb VCOR. dt VRd, VRa, #IMM VCOR. dt SRd, SRa, SRb VCOR. dt SRd, SRa, #IMM where dt = {b, b9, h, w and {,. w and.
Note that f specifies the same operation.

[0461]

[Table 142]

Explanation The logical complement of Ra and Rb / the complement of the immediate operand is logically ORed.
The result is returned to the destination register Rd.

Operation for (i = 0; i <NumElem && EMASK [i]; i ++) ｛Bop [i] = ｛VRb [i] ‖SRb ‖sex (IMM <8: 0>)｝; Rd [i] <k> = -Ra [i] <k> │Bop [i] <k>, k = for all bits in element;｝ Exceptions None Conditional return from VCRSR subroutine
N

[0464]

[Table 143]

Assembler syntax VCRSR. cond where cond = {un, lt, eq, le, gt,
ne, ge, ov｝.

Description If Cond is true, return to the subroutine. This is not a delayed branch.

If Cond is true, execution continues from the return address saved on the return address stack. If not, execution is VPC + 4
Continue with.

Operation If ((Cond == VCSR [SO, GT, EQ, LT]) | (Cond = un)) ｛if (VSP <4: 0> == 0) ｛VISRC <RASU> = 1; signal ARM7 with RASU exception; VP STATE = VP IDLE;｝ else ｛VSP <4: 0> = VSP <4: 0>-1; VPC = RSTACK [VSP <3: 0>]; VPC <1: 0> = b'00;｝｝ else VPC = VPC +4; Exception Instruction address invalid, address stack overflow return.

[0469] VCVTB9 byte 9 data type
Conversion

[0470]

[Table 144]

Assembler syntax VCVTB9. md VRd, VRb VCVTB9. md SRd, SRb where md = {bb9, b9h, hb9}

[0472]

[Table 145]

Explanation Each element of Rb is from byte to byte 9 (bb9)
, Byte 9 to Huffword (b9h), or Huffword to byte 9 (hb9).

Operation if (md <1: 0> = 0) ｛// bb9 for byte to byte 9 conversion VRd = VRb; VRd <9i + 8> = VRb <9i + 7>, I = 0 to 31 (or 63 in VEC64 mode)｝ else if (md <1: 0> == 2) ｛// b9h for byte9 to halfword conversion VRd = VRb; VRd <18i + 16: 18i + 9> = VRb <18i + 8>, i = 0 to 15 (or 31 in VEC64 mode)｝ else if (md <1: 0> = 3) ｛// hb9 for halfword to byte9 conversion VRd <18i + 8> = VRb <18i + 9>, i = 0 to 15 (or 31 in VEC64 mode) else VRd = undefined; Exceptions None Programming notes b9h is a programmer before using such an instruction with mode the programmer must have the reduced number of elements in the vector register with shuffle operation. Is required to be adjusted. After using such an instruction with the hb9 mode, the programmer is required to adjust the increased number of elements to the destination vector register with unshuffle operation. This instruction is not affected by the element mask.

VCVTFF Convert floating point to fixed point

[0476]

[Table 146]

Assembler syntax VCVTFF VRd, VRa, SRb VCVTFF VRd, VRa, #IMM VCVTFF SRd, SRa, SRb VCVTFF SRd, SRa, #IMM

[0478]

[Table 147]

Description The content of the vector / scalar register Ra is such that the width of Y is Rb.
(Modulo 32) or specified by the IMM field and if the width of X is defined as (32-Y width), 3
It is converted from a 2-bit floating point to a fixed point real number in the format (X, Y).

Operation Y size = ｛SRb% 32 ‖ IMM <4.0>｝; for (i = 0; i <NumElem; i ++) ｛Rd [i] = convert to <32-Y size.Y size> format (Ra [i]);｝ Exceptions Overflow Programming Note This instruction only supports word data size only. This instruction does not use an element mask because the architecture does not support multiple data types in registers. This instruction uses truncation from zero rounding mode for integer data types.

VCVTIF Integer floating point number
Convert to points

[0482]

[Table 148]

Assembler syntax VCVTIF VRd, VRb VCVTIF VRd, SRb VCVTIF SRd, SRa

[0484]

[Table 149]

Description The contents of the vector / scalar register Rb are converted from int32 to the float data type, and the result is stored in the vector / scalar register Rd.

Operation for (i = 0; i <NumElem: i ++) ｛Rd [i] = convert to floating point format (Rb [i]);｝ Exceptions None Programming note This instruction only supports word data size only . This instruction does not use an element mask because the architecture does not support multiple data types in registers.

VD1CBR VCR1 Reduction and Conditions
Branch with condition

[0488]

[Table 150]

Assembler syntax VD1CBR. cond #Offset where cond = {un, lt, eq, le, gt,
ne, ge, ov｝.

Description Decreases VCR1 and branches if Cond is true. This is not a delayed branch.

Operation VCR1 = VCR1-1; If ((VCR1> 0) & ((Cond = VCSR [SO, GT, EQ, LT]) | (Cond == un))) VPC = VPC + sex (Offset < 22: 0> ^* 4); else VPC = VPC + 4; Exception Instruction address invalid Programming note VCR1 is decremented before branch condition is checked. Executing this instruction when VCR1 is 0 effectively sets the loop count 2 ³² -1.

VD2CBR VCR2 Reduction and Conditions
Branch with condition

[0493]

[Table 151]

Assembler syntax VD2CBR. cond #Offset where cond = {un, lt, eq, le, gt,
ne, ge, ov｝.

Description Decreases VCR2 and branches if Cond is true. This is not a delayed branch.

Operation VCR2 = VCR2−1; If ((VCR2> 0) & ((Cond = VCSR [SO, GT, EQ, LT]) | (Cond = un))) VPC = VPC + sex (Offset <22 : 0> ^* 4); else VPC = VPC + 4; Exception Instruction address invalid Programming note VCR2 is decremented before branch condition is checked. Executing this instruction when VCR2 is 0 effectively sets the loop count 2 ³² -1.

VD3CBR VCR3 Reduction and Conditions
Branch with condition

[0498]

[Table 152]

Assembler syntax VD3CBR, cond #Offset where cond = {un, lt, eq, le, gt,
ne, ge, ov｝.

Description Decreases VCR3 and branches if Cond is true. This is not a delayed branch.

Operation VCR3 = VCR3-1; If ((VCR3> 0) & ((Cond = VCSR [SO, GT, EQ, LT]) | (Cond = un))) VPC = VPC + sex (Offset <22 : 0> ^* 4); else VPC = VPC + 4; Exception Instruction address invalid Programming note VCR3 is decremented before branch condition is checked. Executing this instruction when VCR3 is 0 effectively sets the loop count 2 ³² -1.

Division by VDIV2N 2 ⁿ

[0503]

[Table 153]

Assembler syntax VDIV2N. dt VRd, VRa, VRb VDIV2N. dt VRd, VRa, #IMM VDIV2N. dt SRd, SRa, SRb VDIV2N. dt SRd, SRa, #IMM where dt = {b, b9, h, w}

[0505]

[Table 154]

Description The contents of the vector / scalar register Ra is 2 ⁿ if ⁿ is an explicit integer in a scalar register (Rb or IMM).
And the final result is stored in the vector / scalar register Rd. This instruction uses truncation (round toward zero) as in rounding mode.

[0507] Exceptions None Programming Notes Note that N is obtained in 5 bits from SRb or IMM (4: 0). For the Byte, Byte 9, Huffword data type, the programmer is responsible for accurately specifying the same or smaller value of N in data size.
If it is greater than the precision of the specified data size, the element is filled with sign bits. This instruction uses round toward zero as the rounding mode.

VDIV2N. Split by F 2 ⁿ float

[0509]

[Table 155]

Assembler syntax VDIV2N. f VRd, VRa, VRb VDIV2N. f VRd, VRa, #IMM VDIV2N. f SRd, SRa, SRb VDIV2N. f SRd, SRa, #IMM

[0511]

[Table 156]

Description The contents of the vector / scalar register Ra are divided by 2 ⁿ if ⁿ is an explicit integer of a scalar register (Rb or IMM), and the final result is stored in the vector / scalar register Rd.

[0513] Exceptions None Programming Notes Note that N is obtained in 5 bits from SRb or IMM (4: 0).

VDIVI Split Initialization-Incomplete

[0515]

[Table 157]

Assembler syntax VDIVI. ds VRb VDIVI. ds SRb where ds = {b, b9, h, w}.

[0517]

[Table 158]

Description Performs the initialization step of non-restored signed integer division. The dividend is an accumulator and is a double precision signed integer. If the dividend is single precision, it should be sign-extended with double precision and stored in VACOH and VACOL. The divisor is Rb, a single precision signed integer.

If the sign of the dividend is the same as the sign of the divisor, Rb is subtracted from the upper part of the accumulator; otherwise, Rb is added to the upper part of the accumulator.

[0520] Exceptions None Programming Notes The programmer is required to detect overflow or division by zero before the division step.

VIDVS Split Step-Incomplete
all

[0522]

[Table 159]

Assembler syntax VDIVS. ds VRb VDIVS. ds SRb where ds = {b, b9, h, w}.

[0524]

[Table 160]

Description One repetition step of the restored signed division is performed. This instruction is multiple times the data size (ie, 8 times for int8 data type, 9 times for int9, int16
16 times for the int32 data type and 32 times for the int32 data type). The VDIVI instruction should be used once before the divide step to generate the remainder of the initial part in the accumulator. The divisor is R
b is a single precision signed integer. First, the quotient bit is extracted at each step and shifted to the least significant bit of the accumulator. If the sign of the partial remainder is the same as the sign of the divisor of Rb, Rb is subtracted from the upper part of the accumulator. If not, Rb is added to the top of the accumulator. The quotient bit is 1 if the sign of the resulting partial remainder (addition or subtraction) in the accumulator is the same as the sign of the divisor. Otherwise, the quotient bit is zero (0). The accumulator is shifted left one bit position with the quotient bit filled. At the conclusion of the division step, the remainder is recorded above the accumulator and the quotient is recorded below the accumulator. The quotient is in one's complement form.

Operation VESL Shift element left by one

[0527]

[Table 161]

Assembler syntax VESL. dt SRc, VRd, VRa, SRb where dt = {b, b9, h, w, f},. w and. f
Specifies the same operation.

[0529]

[Table 162]

Description The elements of the vector register Ra are shifted one position to the left, and are filled from the scalar register Rb. The shifted leftmost element is returned to the scalar register Rc, and the remaining elements are returned to the vector register Rd.

[0531]

[Table 163]

[0532] Exceptions None Programming Notes This instruction is not affected by the element mask.

[0533] VESR Only 1 element
Shift right

[0534]

[Table 164]

Assembler syntax VESR. dt SRc, VRd, VRa, SRb where dt = {b, b9, h, w, f},. w and. f
Specifies the same operation.

[0536]

[Table 165]

Description The elements of the vector register Ra are shifted right by one position, and are filled from the scalar register Rb. The rightmost shifted element is returned to the scalar register Rc, and the remaining elements are returned to the vector register Rd.

[0538]

[Table 166]

[0539] Exceptions None Programming Notes This instruction is not affected by the element mask.

VEXTRT One Element Extraction

[0541]

[Table 167]

The assembler syntax VEXTRT. dt SRd, VRa, SRb VEXTRT. dt SRd, VRa, #IMM where dt = {b, b9, h, w, f},. w and. f
Specifies the same operation.

[0543]

[Table 168]

Description An element is extracted from the Ra vector register whose index is specified by the scalar register Rb or the IMM field and stored in the scalar register Rd.

Operation index32 = ｛SRb% 32 ‖ IMM <4: 0>｝; index64 = ｛SRb% 64 ‖ IMM <5: 0>｝; index = (VCSR <vec64>)? index64: index32; SRd = VRa [index]; Exceptions None Programming notes This instruction is not affected by the element mask.

[0546] Code of VEXTSNG2 (1, -1)
Extraction

[0547]

[Table 169]

Assembler syntax VEXTSNG2. dt VRd, VRa VEXTSNG2. dt SRd, SRa where dt = {b, b9, h, w}.

[0549]

[Table 170]

Description The sign value of the contents of the vector / scalar register Ra is calculated like an element, and the result is stored in the vector / scalar register Rd.

Operation for (i = 0; i <NumElem && EMASK [i]; i ++) ｛Rd [i] = (Ra [i] <0)? -1: 1;｝ Exceptions None VEXTSNG3 Extract code of (1,0, -1)

[0552]

[Table 171]

Assembler syntax VEXTSNG3. dt VRd, VRa VEXTSNG3. dt SRd, SRa where dt = {b, b9, h, w}.

[0554]

[Table 172]

Description The sign value of the contents of the vector / scalar register Ra is calculated like an element, and the result is stored in the vector / scalar register Rd.

Operation for (i = 0; i <NumElem && EMASK [i]; i ++) ｛if (Ra [i]> 0) Rd [i] = 1; else if (Ra [i] <0) Rd [ i] =-1; else Rd [i] = 0;｝ Exception None VINSRT 1 element insertion

[0557]

[Table 173]

The assembler syntax VINSRT. dt VRd, SRa, SRb VINSRT. dt SRd, SRa, #IMM where dt = {b, b9, h, w, f},. w and. f
Specify the same operation.

[0559]

[Table 174]

Description The elements of the scalar register Ra are replaced with the scalar register Rb.
Alternatively, the data is inserted into the vector register Rd at the index specified by the IMM field.

Operation index32 = ｛SRb% 32 ‖ IMM <4: 0>｝; index64 = ｛SRb% 64 ‖ IMM <5: 0>｝; index = (VCSR <vec64>)? index64: index32; VRd [index] = SRa; Exceptions None Programming note This instruction is not affected by the element mask.

VL Load

[0563]

[Table 175]

[0564] Assembler syntax VL. lt Rd, SRb, SRi VL. lt Rd, SRb, #IMM VL. lt Rd, SRb +, SRi VL. lt Rd, SRb +, #IMM where lt = {b, bz9, bs9, h, w, 4,
8, 16, 32, 64}, Rd = {VRd, VRAd,
SRd｝,. w and. f designates the same operation, and. 64
And VRAd cannot be specified together. Use VLOFF for cache offload.

Description Loads a vector register into the current or replacement bank or scalar register.

Operation EA = SR _b + ｛SR _i ‖ sex (IMM <7: 0>)); if (A == 1) SR _b = EA; R _d = see table below;

[0567]

[Table 176]

Exceptions Data Address, Unaligned Access Invalid Programming Note This instruction is not affected by the element mask.

VLCB Load from circular buffer

[0570]

[Table 177]

Assembler syntax VLCB. lt Rd, SRb, SRi VLCB. lt Rd, SRb, #IMM VLCB. lt Rd, SRb +, SRi VLCB. lt Rd, SRb +, #IMM where lt = {b, bz9, ds9, h, w, 4,
8, 16, 32, 64}, Rd = {VRd, VRAd,
SRd｝. . b and. ds9 designates the same operation,.
Note that neither 64 nor VRAd can be specified. Use VLCBOFF for cache offload.

[0572] To load the vector register or a scalar register from the circular buffer pointed to by END pointers residing in BEGIN pointer and SR _{b + 2} present in the described SR _{b + 1.}

If the address is larger than the END address before loading, of course, the effective address is adjusted. Also, the circular buffer bounds are. h
as well as. Should be aligned on halfwords and word boundaries for w scalar registers.

[0574]

[Table 178]

Exceptions Invalid Data Address, Unaligned Access Programming Notes This instruction is not affected by the element mask.

A programmer cannot operate as expected unless the following conditions are satisfied.

BEGIN <EA <2 * END-BEGIN That is, EA-END <ENG-BEGIN, of course,
EA> BEGIN VLD Double Road

[0578]

[Table 179]

Assembler syntax VLD. lt Rd, SRb, SRi VLD. lt Rd, SRb, #IMM VLD. lt Rd, SRb +, SRi VLD. lt Rd, SRb +, #IMM where lt = {b, bz9, bs9, h, w, 4,
8, 16, 32, 64}, Rd = {VRd, VRAd,
SRd｝,. b and. bs9 specifies the same operation.
Note that 64 and VRAd cannot be specified together. Use VLDOFF for cache offload.

Description Loads two vector registers into the current or replacement bank or two scalar registers.

[0581]

[Table 180]

Exceptions Data Address, Unaligned Access Invalid Programming Note This instruction is not affected by the element mask.

VLI Immediate Load

[0584]

[Table 181]

Assembler syntax VLI. dt VRd. #IMM VLI. dt SRd. #IMM where dt = {b, b9, h, w, f}.

Description Loads an immediate into a scalar or vector register.

For scalar register loads, bytes, bytes 9, halfwords or words are loaded by data type. For byte, byte 9 and halfword data types, the unaffected byte (byte 9) is not modified.

Operation Rd = Refer to the following table:

[0589]

[Table 182]

[0590] Exceptions None VLQ Quadruple Load

[0591]

[Table 183]

Assembler syntax VLQ. lt Rd, SRb, SRi VLQ. lt Rd, SRb, #IMM VLQ. lt Rd, SRb +, SRi VLQ. lt Rd, SRb +, #IMM where lt = {b, bz9, bs9, h, w, 4,
8, 16, 32, 64}, Rd = {VRd, VRAd,
SRd｝,. b and. bs9 specifies the same operation.
Note that both 64 and VRAd cannot be specified. Use VLQOFF for cache offload.

Description Loads 4 vector registers into the current or replacement bank or 4 scalar registers.

Operation EA = SR _b + ｛SR _i ‖ sex (IMM <7: 0>)｝; if (A == 1) SR _b = EA ;; R _d : R _{d + 1} : R _{d + 2} : R _{d + 3} = see table below;

[0595]

[Table 184]

Exceptions Data Address, Unaligned Access Invalid Programming Note This instruction is not affected by the element mask.

VLR Load Reverse

[0598]

[Table 185]

Assembler syntax VLR. lt Rd, SRb, SRi VLR. lt Rd, SRb, #IMM VLR. lt Rd, SRb +, SRi VLR. lt Rd, SRb +, #IMM where lt = {4,8,16,32,64}, Rd =
{VRd, VRAd},. Note that 64 and VRAd cannot be specified together. Use VLROFF for cache offload.

Description Loads vector registers in reverse element order. This instruction does not support scalar destination registers.

[0601]

[Table 186]

Exceptions Data Address, Unaligned Access Invalid Programming Note This instruction is not affected by the element mask.

VLSL Logical Move Left

[0604]

[Table 187]

Assembler syntax VLSL. dt VRd, VRa, SRb VLSL. dt VRd, VRa, #IMM VLSL. dt SRd, SRa, SRb VLSL. dt SRd, SRa, #IMM where dt = {b, b9, h, w,}.

[0606]

[Table 188]

Description Each element of the vector / scalar register Ra is logically bit-shifted to the left by the amount of shift given to the scalar register Rb or the IMM field by zero-filling the least significant bit LSB to zero. It is stored in the vector / scalar register Rd.

[0608] Exceptions None Programming notes Note that the travel distance is obtained from SRb or IMM (4: 0) as a 5-bit number. For byte, byte 9, and huff word data types, the programmer is obliged to specify exactly the same amount of movement that is less than or equal to the number of bits in the data size. If the displacement is larger than the specified data size, the element is zero filled.

VLSR Logic Move Right

[0610]

[Table 189]

Assembler syntax VLSR. dt VRd, VRa, SRb VLSR. dt VRd, VRa, #IMM VLSR. dt SRd, SRa, SRb VLSR. dt SRd, SRa, #IMM where dt = {b, b9, h, w,}.

[0612]

[Table 190]

Description Each element of the vector / scalar register Ra is logically bit-shifted to the right by a shift amount given to the scalar register Rb or the IMM field by zero-filling the position of the most significant bit MSB. It is stored in the vector / scalar register Rd.

[0614] Exceptions None Programming notes Note that the travel distance is obtained from SRb or IMM (4: 0) as a 5-bit number. For byte, byte 9, and huff word data types, the programmer is obliged to specify exactly the same amount of movement that is less than or equal to the number of bits in the data size. If the displacement is larger than the specified data size, the element is filled with zeros.

Load VLWS Stride
Do

[0616]

[Table 191]

Assembler syntax VLWS. lt Rd, SRa, SRi VLWS. lt Rd, SRb, #IMM VLWS. lt Rd, SRb +, SRi VLWS. lt Rd, SRb +, #IMM where lt = {4, 8, 16, 32, 64}, Rd =
{VRd, VRAd},. Note that both 64 and VRAd cannot be specified. Use VLWSOFF for cache offload.

Description Starting from the effective address, the stride control register (Strid
e Control register) as scalar register SRb + 1
Is used to load 32 bytes from the memory into the vector register VRd. LT specifies the number of consecutive bytes and the block size for loading for each block. SRb + 1 specifies the number and stride that separate the beginning of two consecutive blocks. Stride should be equal to or greater than the block size. EA must be aligned data size. Stride and block size should be many times the data size.

Operation EA = SR _b + {SR _i {sex (IMM <7: 0>)}; if (A = 1) SR _b = EA; Block_size = {4‖8‖16‖32}; stride = SR _{b + 1} <31: 0>; for (i = 0; i <VECSIZE / Block_size; i ++) for (j = 0; j <Block_size; j ++) VRd [i ^* Block_size + j] <8: 0 > = sex BYTE [EA + i ^* Stride + j]; Exception Data address, non-aligned access invalid VMAC multiplication and accumulation

[0620]

[Table 192]

Assembler syntax VMAC. dt VRa, VRb VMAC. dt VRa, SRb VMAC. dt VRa, #IMM VMAC. dt SRa, SRb VMAC. dt SRa, # IMM where dt = {b, h, w, f}.

[0622]

[Table 193]

Description Each element of Ra is multiplied by each element of Rb to generate a double-precision intermediate result, and each double-precision element of the intermediate result is added to each double-precision element of the vector accumulator, and each element is added to the vector accumulator. The sum of the double precision of is stored. Ra and Rb use the specified data type, while VAC uses the appropriate double precision data type (int8, int16, and in, respectively).
16, 32, and 64 bits for t32). The upper part of each double precision element is stored in the VACH.

All operands and results are single precision for the float data type.

Operation for (i = 0; i <NumElem && EMASK [i]; i ++) ｛Aop [i] = ｛VRa [i] ‖SRa｝; Bop [i] = ｛VRb [i] ‖SRb｝; if (dt == float) VACL [i] = Aop [i] ^* Bop [i] + VACL [i]; else VACH [i]: VACL [i] = Aop [i] ^* Bop [i] + VACH [ i]: VACL [i]; Exceptions Overflow, floating point invalid operand Programming Notes This instruction does not support the int9 data type, but uses the int16 data type instead.

VMCF Multiplication and Decimal Part A
Cumulate

[0627]

[Table 194]

Assembler syntax VMACF. dt VRa, VRb VMACF. dt VRa, SRb VMACF. dt VRa, #IMM VMACF. dt SRa, SRb VMCF. dt SRa, # IMM where dt = {b, h, w,}.

[0629]

[Table 195]

Description Each element of Ra is multiplied by each element of Rb to generate a double-precision intermediate result, the intermediate result is shifted one bit to the left, and each double-precision element of the shifted intermediate result is stored in the vector accumulator. The sum of the double precision of each element is stored in the vector accumulator in addition to the double precision element. VRa and Rb use the specified data type, while VAC uses the appropriate double precision data type (int8, int16, and in, respectively).
16, 32, and 64 bits for t32). The upper part of each double precision element is stored in the VACH.

Operation for (i = 0; i <NumElem && EMASK [i]; i ++) ｛Bop [i] = {VRb [i] ‖SRb‖sex (IMM <8: 0>)}; VACH [i] : VACL [i] = ((VRa [i] ^* Bop [i]) << 1) + VACH [i]: VACL [i]; 例外 Exception overflow, programming note This instruction does not support int9 data type Instead, use the int16 data type.

VMACL Multiplication and Row Space
Cumulate

[0633]

[Table 196]

Assembler Syntax VMCL. dt VRa, VRb VMCL. dt VRa, SRb VMACL. dt VRa, #IMM VMACL. dt SRa, SRb VMCL. dt SRa, # IMM where dt = {b, h, w, f}.

[0635]

[Table 197]

Description Each element of Ra is multiplied by each element of Rb to generate a double-precision intermediate result, and each double-precision element of the intermediate result is added to each double-precision element of the vector accumulator, and each element is added to the vector accumulator. Is stored, and the lower part is returned to the target register VRd.

Ra and Rb use the specified data type, while VAC uses the appropriate double precision data type (16, 32, and 64 bits for int8, int16, and int32, respectively). The upper part of each double precision element is stored in the VACH.

All operands and results are single precision for the float data type.

Operation for (i = 0; i <NumElem && EMASK [i]; i ++) ｛Bop [i] = ｛VRb [i] ‖SRb｝; if (dt == float) VACL [i] = VRa [ i] ^* Bop [i] + VACL [i]; else VACH [i]: VACL [i] = VRa [i] ^* Bop [i] + VACH [i]: VACL [i]; VRd [i] = VACL [i]; Exceptions Overflow, floating point invalid operand Programming Notes This instruction does not support the int9 data type, but instead uses the int16 data type.

VMAD Multiplication and Addition

[0641]

[Table 198]

The assembler syntax VMAD. dt VRc, VRd, VRa, VRb VMAD. dt SRc, SRd, SRa, SRb where dt = {b, h, w}.

[0643]

[Table 199]

Description Each element of Ra is multiplied by each element of Rb to generate a double precision intermediate result, and each double precision element of the intermediate result is added to each element of Rc to obtain a target register (Rd
+1: Rd) stores the double precision sum of each element.

Operation for (i = 0: i <NumElem && EMASK [i]; i ++) ｛Aop [i] = {VRa [i] ‖SRa｝; Bop [i] = ｛VRb [i] ‖SRb｝; Rd + 1 [i]: Rd [i] = Aop [i] ^* Bop [i] + sex_dp (Cop [i]);｝ No exception VMADL multiplication and Row addition

[0646]

[Table 200]

The assembler syntax VMADL. dt VRc, VRd, VRa, VRb VMADL. dt SRc, SRd, SRa, SRb where dt = {b, h, w, f}.

[0648]

[Table 201]

Description Each element of Ra is multiplied by each element of Rb to generate a double-precision intermediate result, and each double-precision element of the intermediate result is added to each element of Rc. The partial double precision sum is stored.

All operands and results are single precision for the float data type.

Operation for (i = 0; i <NumElem && EMASK [i]; i ++) ｛Aop [i] = {VRa [i] ‖SRa｝; Bop [i] = ｛VRb [i] ‖SRb｝; Cop [i] = {VRc [i] ‖SRc}; if (dt == float) Lo [i] = Aop [i] ^* Bop [i] + Cop [i]; else Hi [i]: Lo [i ] = Aop [i] ^* Bop [i] + sex_dp (Cop [i]); Rd [i] = Lo [i];｝ Exceptions Overflow, floating point invalid operand.

VMAS Multiplication and Accumulation
Subtraction from data

[0653]

[Table 202]

Assembler Syntax VMAS. dt VRa, VRb VMAS. dt VRa, SRb VMAS. dt VRa, #IMM VMAS. dt SRa, SRb VMAS. dt SRa, # IMM where dt = {b, h, w, f}.

[0655]

[Table 203]

Description Each element of Ra is multiplied by each element of Rb to generate a double-precision intermediate result, and each double-precision element of the intermediate result is subtracted from each double-precision element of the vector accumulator, and each element is added to the vector accumulator. The sum of the double precision of is stored.

Ra and Rb use the specified data type, while VAC uses the appropriate double precision data type (16, 32, and 64 bits for int8, int16, and int32, respectively). The upper part of each double precision element is stored in the VACH.

All operands and results are single precision for the float data type.

Operation for (i = 0; i <NumElem && EMASK [i]; i ++) ｛Bop [i] = {VRb [i] ‖SRb｝; if (dt == float) VACL [i] = VACL [ i] -VRa [i] ^* Bop [i]; else VACH [i]: VACL [i] = VACH [i]: VACL [i] -VRa [i] ^* Bop [i]; 例外 Exception Overflow, floating point Invalid Operands Programming Note This instruction does not support the int9 data type, but instead uses the int16 data type.

VMASF Multiplication and Accumulation
Subtraction from decimal fraction

[0661]

[Table 204]

Assembler syntax VMASF. dt VRa, VRb VMASF. dt VRa, SRb VMASF. dt VRa, #IMM VMASF. dt SRa, SRb VMASF. dt SRa, # IMM where dt = {b, h, w}.

[0663]

[Table 205]

Description Each element of Ra is multiplied by each element of Rb to generate a double precision intermediate result, the double precision intermediate result is shifted left by one bit, and each double precision element of the shifted intermediate result is vector Subtraction is performed from each double precision element of the accumulator, and the vector accumulator stores the sum of the double precision of each element.

Ra and Rb use the specified data type, while VAC uses the appropriate double precision data type (16, 32, and 64 bits for int8, int16, and int32, respectively). The upper part of each double precision element is stored in the VACH.

Operation for (i = 0; i <NumElem && EMASK [i]; i ++) ｛Bop [i] = {VRb [i] ‖SRb‖sex (IMM <8: 0>)｝; VACH [i] : VACL [i] = VACH [i]: VACL [i] -VRa [i] ^* Bop [i];｝ Exception Overflow Programming Note This instruction does not support int9 data type, but uses int16 data type instead .

VMASL Multiplication and Accumulation
Subtraction from Latarrow

[0668]

[Table 206]

Assembler syntax VMASL. dt VRd, VRa, VRb VMASL. dt VRd, VRa, SRb VMASL. dt VRd, VRa, #IMM VMASL. dt SRd, SRa, SRb VMASL. dt SRd, SRa, #IMM where dt = {b, h, w, f}.

[0670]

[Table 207]

Description Each element of Ra is multiplied by each element of Rb to generate a double-precision intermediate result, and each double-precision element of the intermediate result is subtracted from each double-precision element of the vector accumulator, and each element is added to the vector accumulator. Is stored, and the lower part is returned to the target register VRd.

Ra and Rb use the specified data type, while VAC uses the appropriate double precision data type (16, 32, and 64 bits for int8, int16, and int32, respectively). The upper part of each double precision element is stored in the VACH.

All operands and results are single precision for the float data type.

Operation for (i = 0; i <NumElem && EMASK [i]; i ++) ｛Bop [i] = ｛VRb [i] ‖SRb｝; if (dt == float) VACL [i] = VACL [ i] -VRA [i] ^* Bop [i]; else VACH [i]: VACL [i] = VACH [i]: VACL [i] -VRa [i] ^* Bop [i]; VRd [i] = VACL [i];｝ 命令 注意 注意 注意 注意 注意 命令 This instruction does not support the int9 data type;

VMAX Bi-directional maximum and exchange

[0676]

[Table 208]

Assembler syntax VMAXE. dt VRd, VRb where dt = {b, b9, h, w, f}.

[0678]

[Table 209]

Description VRa and VRb must be the same. VRa is V
When different from Rb, the result is undefined.

Each even / odd data element of vector register Rb is compared in pairs, the larger value of each data element pair being stored in the even position of vector register Rd, and the smaller value of each data element pair being the odd number. Stored in position.

Operation for (i = 0; i <NumElem && EMASK [i]: i = i + 2) ｛VRd [i] = (VRb [i]> VRb [i + 1])? VRb [i]: VRb [i + 1]; VRd [i + 1] = (VRb [i]> VRb [i + 1])? VRb [i + 1]: VRb [i]; Ｖ No exception VMOV move

[0682]

[Table 210]

Assembler syntax VMOV. dt Rd, Rb where dt = {b, b9, h, w, f} and Rd
And Rb are indicated by register names designated structurally.

[0684]

[Table 211]

[0685]

[Table 212]

[0686]

[Table 213]

Operation Rd = Rb Exceptions Setting an exception status bit in VCSR or VISRC causes a corresponding exception.

Programming Note This instruction is not affected by the element mask.
Note that this instruction cannot be used to move to the alternate bank register in VEC64 mode because the alternate bank concept does not exist in VEC64 mode.

VMUL Multiplication

[0690]

[Table 214]

[0691] Assembler syntax VMUL. dt VRc, VRd, VRa, VRb VMUL. dt SRc, SRd, SRa, SRb where dt = {b, h, w}.

[0692]

[Table 215]

Description Each element of Ra is multiplied by each element of Rb to generate a double precision result, and the sum of the double precision of each element is returned to the target register Rc: Rd.

Ra and Rb use the specified data types, while Rc: Rd use the appropriate double precision data types (int8, int16, and int3, respectively).
2 for 16, 32, and 64 bits), the upper part of each double precision element is stored in Rc.

[0696] Exceptions None Programming Notes This instruction does not support the int9 data type, but instead uses the int16 data type. Also, this instruction does not support the float data type because the extended result is not a supported data type.

[0696] VMULA accumulator multiplication

[0697]

[Table 216]

Assembler syntax VMULA. dt VRa, VRb VMULA. dt VRa, SRb VMULA. dt VRa, #IMM VMULA. dt SRa, SRb VMULA. dt SRa, # IMM where dt = {b, h, w, f}.

[0699]

[Table 217]

Description Each element of Ra is multiplied by each element of Rb to generate a double precision intermediate result, and the result is recorded in an accumulator.

All operands and results are single precision for float data types.

[0702] Exceptions None Programming Notes This instruction does not support the int9 data type, but instead uses the int16 data type.

VMULAF Accumulator Decimal Part Multiply

[0704]

[Table 218]

The assembler syntax VMULAF. dt VRa, VRb VMULAF. dt VRa, SRb VMULAF. dt VRa, #IMM VMULAF. dt SRa, SRb VMULAF. dt SRa, # IMM where dt = {b, h, w}.

[0706]

[Table 219]

Description Each element of Ra is multiplied by each element of Rb to generate a double precision intermediate result, the double precision intermediate result is shifted left by one bit, and the result is recorded in the accumulator.

Operation for (i = 0; i <NumElem && EMASK [i]: i ++) ｛Bop [i] = {VRb [i] ‖SRb‖sex (IMM <8: 0>)｝; VACH [i] : VACL [i] = (VRa [i] ^* Bop [i]) <<1;｝ Exceptions None Programming note This instruction does not support the int9 data type, but uses the int16 data type instead.

VMULF Fractional Part Multiplication

[0710]

[Table 220]

Assembler syntax VMULF. dt VRa, VRb VMULF. dt VRa, SRb VMULF. dt VRa, #IMM VMULF. dt SRa, SRb VMULF. dt SRa, # IMM where dt = {b, h, w}.

[0712]

[Table 221]

[0713] Description: Each element of Ra is multiplied by each element of Rb to generate a double-precision intermediate result, the double-precision intermediate result is shifted by one bit to the left, and the upper part of the result is stored in the destination register (VRd + 1). And the lower part of the result is returned to the destination register VRd. VRd must be an even numbered register.

Operation for (i = 0; i <NumElem && EMASK [i]; i ++) ｛Bop [i] = {VRb [i] ‖SRb‖sex (IMM <8: 0>)}; Hi [i] : Lo [i] = (VRa [i] ^* Bop [i]) <<1; VRd + 1 [i] = Hi [i]; VRd [i] = Lo [i];｝ No exception Programming attention This instruction Does not support the int9 data type, but instead uses the int16 data type.

VMULFR Decimal part multiplication and rounding
Goiri

[0716]

[Table 222]

Assembler syntax VMULFR. dt VRd, VRa, VRb VMULFR. dt VRd, VRa, SRb VMULFR. dt VRd, VRa, #IMM VMULFR. dt SRd, SRa, SRb VMULFR. dt SRd, SRa, #IMM where dt = {b, h, w}.

[0718]

[Table 223]

Description Each element of Ra is multiplied by each element of Rb to generate a double precision intermediate result, the double precision intermediate result is shifted left by one bit, and the shifted intermediate result is shifted to the upper part. Round off and return the upper part to the destination register (VRd).

Operation for (i = 0; i <NumElem && EMASK [i]: i ++) ｛Bop [i] = {VRb [i] ‖SRb‖sex (IMM <8: 0>)｝; Hi [i] : Lo [i] = (VRa [i] ^* Bop [i]) <<1; if (Lo [i] <msb> == 1) Hi [i] = Hi [i] +1; VRd [i] = Hi [i];｝ Exceptions None Programming notes This instruction does not support the int9 data type, but uses the int16 data type instead.

VMULL Row Multiplication

[0722]

[Table 224]

The assembler syntax VMULLL. dt VRd, VRa, VRb VMULL. dt VRd, VRa, SRb VMULL. dt VRd, VRa, #IMM VMULL. dt VRd, SRa, SRb VMULL. dt VRd, SRa, #IMM where dt = {b, h, w, f}.

[0724]

[Table 225]

[0725] Description: Each element of Ra is multiplied by each element of Rb to generate a double precision intermediate result, and the lower part of the result is returned to the destination register VRd.

All operands and results are single precision for the float data type.

[0727] Exceptions Overflow, floating point invalid operand Programming Notes This instruction does not support the int9 data type, but instead uses the int16 data type.

[ 0727 ] VNAND NAND

[0729]

[Table 226]

[0731] Assembler syntax VNAND. dt VRd, VRa, VRb VNAND. dt VRd, VRa, SRb VNAND. dt VRd, VRa, #IMM VNAND. dt VRd, SRa, SRb VNAND. dt VRd, SRa, #IMM where dt = {b, h, w, f},. w and. Note that f specifies the same operation.

[0731]

[Table 227]

[0732] Description: Each bit of each element in Ra is logically NANDed with the corresponding bit in the Rb / immediate operand, and the result is returned to Rd.

Operation for (i = 0; i <NumElem && EMASK [i]; i ++) ｛Bop [i] = {VRb [i] ‖SRb‖sex (IMM <8: 0>)}; Rd [i] (k) =-(Ra [i] <k>& Bop [i] <k>, for k = all bits in element;｝ Exception None VNOR NOR

[0734]

[Table 228]

[0735] Assembler syntax VNOR. dt VRd, VRa, VRb VNOR. dt VRd, VRa, SRb VNOR. dt VRd, VRa, #IMM VNOR. dt SRd, SRa, SRb VNOR. dt SRd, SRa, #IMM where dt = {b, b9, w, f},. w and. Note that f specifies the same operation.

[0736]

[Table 229]

[0738] Description: The bits of each element in Ra and the corresponding bits in the Rb / immediate operand are logically NORed, and the result is returned to Rd.

Operation for (i = 0; i <NumElem && EMASK [i]; i ++) ｛Bop [i] = {VRb [i] ‖SRb‖sex (IMM <8: 0>)｝; Rd [i] (k) =-(Ra [i] <k> 1 Bop [i] <k>, for k = all bits in element;｝ Exception None VOR OR

[0739]

[Table 230]

[0739] Assembler syntax VOR. dt VRd, VRa, VRb VOR. dt VRd, VRa, SRb VOR. dt VRd, VRa, #IMM VOR. dt SRd, SRa, SRb VOR. dt SRd, SRa, #IMM where dt = {b, b9, w, f},. w and. Note that f specifies the same operation.

[0741]

[Table 231]

[0739] Description: The bits of each element in Ra are logically ORed with the corresponding bits in the Rb / immediate operand, and the result is returned to Rd.

Operation for (i = 0; i <NumElem && EMASK [i]; i ++) ｛Bop [i] = {VRb [i] ‖SRb‖sex (IMM <8: 0>)｝; Rd [i] <k> =-(Ra [i] <k> 1 Bop [i] <k>, for k = all bits in element;｝ Exception None Vorc Complement OR

[0744]

[Table 232]

[0745] Assembler syntax Vorc. dt VRd, VRa, VRb VORC. dt VRd, VRa, SRb VORC. dt VRd, VRa, #IMM VORC. dt SRd, SRa, SRb VORC. dt SRd, SRa, #IMM where dt = {b, b9, h, w},. w and. Note that f specifies the same operation.

[0746]

[Table 233]

[0747] Description: Logically OR each bit of each element in Ra with the complement of the corresponding bit in the Rb / immediate operand, and return the result to Rd.

Operation for (i = 0: i <NumElem && EMASK [i]; i ++) ｛Bop [i] = ｛VRb [i] ‖SRb‖sex (IMM <8.0>)｝; Rd [i] <k > = Ra [i] <k> 1-Bop [i] <k>. f
or k = all bits in element i:｝ No exception VPFTCH Prefetch

[0749]

[Table 234]

The assembler syntax VPFTCH. dt SRb, SRi VPFTCH. dt SRb, #IMM VPFTCH. dt SRb +, SRi VPFTCH. dt SRb +, #IMM where ln = {1, 2, 4, 8}.

Description A large number of vector data cache lines starting from an effective address are fetched in advance. The number of cache lines is specified as follows: LN (1: 0) = 00: One 64-byte cache line is prefetched. LN (1: 0) = 01: Two 64-byte cache lines are prefetched.

LN (1: 0) = 10: Four 64-byte cache lines are prefetched.

LN (1: 0) = 11: Eight 64-byte cache lines are prefetched.

If the valid cache line is not at a 64-byte boundary, it is truncated first so that it is aligned at a 64-byte boundary.

Operation Exception Data Address Exception Invalid Invalid Programming Note EA (31: 0) indicates the byte address of the local memory.

VPFTCHSP Advance to Temporary Pad
Take out

[0757]

[Table 235]

[0758] Assembler syntax VPFTCHSP. ln SRp, SRb, SRi VPFTCHSP. ln SRp, SRb, #IMM VPFTCHSP. ln SRp, SRb +, SRi VPFTCHSP. ln SRp, SRb +, #IMM where ln = {1, 2, 4, 8}, VPFTCH and V
PFTCHSP has the same opcode Description A number of 64-byte blocks are transmitted from the memory to the temporary pad. The effective address provides the start address to the memory, and SRp provides the start address to the temporary pad. 6
The number of 4-byte blocks is specified as follows.

[0759] LN (1: 0) = 00: One 64-byte block is transmitted.

LN (1: 0) = 01: Two 64-byte blocks are transmitted.

LN (1: 0) = 10: Four 64-byte blocks are transmitted.

LN (1: 0) = 11: Eight 64-byte blocks are transmitted.

If the valid cache line is not at a 64-byte boundary, it is truncated first so that it is aligned at a 64-byte boundary. If the temporary pad pointer address of SRp is not at a 64-byte boundary, it is also truncated first so that it is aligned at the 64-byte boundary. The aligned temporary pad pointer address is incremented by the number of bytes transmitted.

[0764] Exception Data address exception invalid VVOL Rotate left

[0765]

[Table 236]

[0766] Assembler syntax VVOL. dt VRd, VRa, SRb VVOL. dt VRd, VRa, #IMM VOL. dt VRd, SRa, SRb VVOL. dt VRd, SRa, #IMM where dt = {b, b9, h, w}.

[0767]

[Table 237]

Description Each data element of the vector / scalar register Ra is rotated left by the bit amount given to the scalar register Rb or the IMM field, and the result is stored in the vector / scalar register Rd.

[0769] Exceptions None Programming notes Note that the amount of rotation is obtained from SRb or IMM (4: 0) as a 5-bit number. For byte, byte 9, and huff word data types, the programmer is obliged to specify exactly the same amount of rotation that is less than or equal to the number of bits in the data size. If the amount of rotation is much larger than the specified data size, the result is undefined. Turning left by n is equivalent to turning right by ElemSize-n, where ElemSize indicates the number of bits of a given data size.

[0770] VROR Rotate right

[0771]

[Table 238]

[0772] Assembler syntax VROR. dt VRd, VRa, SRb VROR. dt VRd, VRa, #IMM VROR. dt VRd, SRa, SRb VROR. dt VRd, SRa, #IMM where dt = {b, b9, h, w}.

[0773]

[Table 239]

Description Each data element of the vector / scalar register Ra is rotated right by the bit amount given to the scalar register Rb or the IMM field, and the result is stored in the vector / scalar register Rd.

[0775] Exceptions None Programming notes Note that the amount of rotation is obtained from SRb or IMM (4: 0) as a 5-bit number. For byte, byte 9, and huff word data types, the programmer is obliged to specify exactly the same amount of rotation that is less than or equal to the number of bits in the data size. If the amount of rotation is much larger than the specified data size, the result is undefined. Rotating right by n is equivalent to rotating left by ElemSize-n, where ElemSize indicates the number of bits for a given data size.

VROUND Round floating point to integer

[0777]

[Table 240]

[0778] Assembler syntax VROUND. rm VRd, VRb VROUND. rm SRd, SRb where rm = {ninf, zero, near, pi
nf｝.

[0779]

[Table 241]

Description In floating point data format, the contents of vector / scalar register Rb are rounded to the nearest 32-bit integer (word) and the result is vector / scalar register Rb.
stored in d. Rounding mode is defined in RM.

[0781]

[Table 242]

[0782] Exceptions None Programming Notes This instruction is not affected by the element mask.

VSATL Saturation to Lower Boundary

[0784]

[Table 243]

[0785] Assembler syntax VSATL. dt VRd, VRa, VRb VSATL. dt VRd, VRa, SRb VSATL. dt VRd, VRa, #IMM VSATL. dt SRd, SRa, SRb VSATL. dt SRd, SRa, #IMM where dt = {b, b9, h, w, f},. Note that the f data type is not supported with a 9-bit immediate.

[0786]

[Table 244]

Description Each data element of the vector / scalar register Ra is checked against the vector / scalar register Rb or its corresponding lower limit in the IMM field.
If the value of the data element is even smaller than the lower limit, it is set equal to the lower limit and the final result is stored in the vector / scalar register Rd.

[0788] Exception None VSATU Saturation to upper boundary

[0789]

[Table 245]

[0790] Assembler syntax VSATU. dt VRd, VRa, VRb VSATU. dt VRd, VRa, SRb VSATU. dt VRd, VRa, #IMM VSATU. dt SRd, SRa, SRb VSATU. dt SRd, SRa, #IMM where dt = {b, b9, h, w, f},. Note that the f data type is not supported with a 9-bit immediate.

[0791]

[Table 246]

Each data element in the description vector / scalar register Ra is checked against the vector / scalar register Rb or its corresponding upper limit in the IMM field. If the value of the data element is even smaller than the upper limit, it is set equal to the upper limit and the final result is stored in the vector / scalar register Rd.

[0793] No exception VSHFL shuffle

[0794]

[Table 247]

[0795] Assembler syntax VSHFL. dt VRc, VRd, VRa, VRb VSHFL. dt VRc, VRd, VRa, SRb where dt = {b, b9, h, w},. w and. Note that f specifies the same operation.

[0796]

[Table 248]

Description The contents of vector register Ra are shuffled with Rb as shown below, and the result is
c: Stored in Rd.

[0798]

[Table 249]

Operation Exceptions None Programming Caution This instruction does not use element asks.

VSHFLH High Shuffle

[0801]

[Table 250]

[0802] Assembler syntax VSHFLH. dt VRd, VRa, VRb VSHFLH. dt VRd, VRa, SRb where dt = {b, b9, h, w},. w and. Note that f specifies the same operation.

[0803]

[Table 251]

Description The contents of the vector register Ra are shuffled with Rb as described below, and the upper part of the result is stored in the vector register Rd.

[0805]

[Table 252]

Operation Exceptions None Programming Notes This instruction does not use an element mask.

VSHFLLL Low Shuffle

[0808]

[Table 253]

[0809] Assembler syntax VSHFLLL. dt VRd, VRa, VRb VSHFLLL. dt VRd, VRa, SRb where dt = {b, b9, h, w, f},. w and. f
Specify the same operation.

[0810]

[Table 254]

Description The contents of the vector register Ra are shuffled with Rb as described below, and the lower part of the result is stored in the vector register Rd.

[0812]

[Table 255]

Operation Exceptions None Programming Note This instruction does not use an element mask.

[0814] VST storage

[0815]

[Table 256]

[0816] Assembler syntax VST. st Rs, SRb, SRi VST. st Rs, SRb, #IMM VST. st RS, SRb +, SRi VST. st Rs, SRb +, #IMM where st = {b, b9t, h, w, 4, 8, 16,
32, 64}, Rs = {VRs, VRAs, SR
s｝,. b and. b9t specifies the same operation, 64
Note that both and VRAs cannot be specified. Use VSTOFF for cache off storage.

Description Stores a vector or scalar register.

[0818] calculation EA = SR _b + {SR _i ‖ sex (IMM <7: 0>)}; if (A == 1) SR b = EA; MEM [EA] = see table belo
w;

[0819]

[Table 257]

Exceptions Data Address, Unaligned Access Invalid Programming Note This instruction is not affected by the element mask.

VSTCB With circular buffer
Memory

[0822]

[Table 258]

[0823] Assembler syntax VSTCB. st Rs, SRb, SRi VSTCB. st Rs, SRb, #IMM VSTCB. st RS, SRb +, SRi VSTCB. st Rs, SRb +, #IMM where st = {b, b9t, h, w, 4, 8, 16,
32, 64}, Rs = {VRs, VRAs, SR
s｝,. b and. b9t specifies the same operation, 64
And VRAd cannot be specified together. Use VSTCBOFF for cache offload.

[0824] Description: BEGIN pointer at SRb + 1, END at SRb + 2
Store a vector or scalar register from a circular buffer bounded by a pointer.

The effective address is adjusted if it is larger than the END address before the address update operation as well as the storage. In addition, each circular buffer boundary is. h and. Huff words and word boundaries should be aligned for w scalar loads.

[0826] calculation EA = SR _b + {SRi ‖ sex (IMM <7: 0>)}; BEGIN = SR b + 1; END = SR b + 2; cbsize = END - BEGIN; if (EA> END) EA = BEGIN + (E
A-END); if (A == 1) SR _b = EA; MEM [EA] = see table bello
w;

[0827]

[Table 259]

Exceptions Data Address, Unaligned Access Invalid Programming Note This instruction is not affected by the element mask.
The programmer should ensure that the following conditions work for this instruction to work as expected: BEGIN <EA <2 ^* END-BEGIN, ie EA> BEGIN and EA-END <END-B
EGIN VSSTD Double memory

[0829]

[Table 260]

[0832] Assembler syntax VSTD. st Rs, SRb, SRi VSTD. st Rs, SRb, #IMM VSTD. st RS, SRb +, SRi VSTD. st Rs, SRb +, #IMM where st = {b, b9t, h, w, 4, 8, 16,
32, 64}, Rs = {VRs, VRAs, SR
s｝,. b and. b9t specifies the same operation, 64
Note that both and VRAs cannot be specified. Use VSTDOFF for cache off storage.

Description Stores two vector registers from the current or replacement bank or two scalar registers.

Operation EA = SR _b + {SR _i {sex (IMM <7: 0>)}; if (A == 1) SR _b = EA; MEM [EA] = seeable bello
w;

[0832]

[Table 261]

Exceptions Data Address, Unaligned Access Invalid Programming Note This instruction is not affected by the element mask.

[ 0832 ] VSTQ Quadruple Memory

[0836]

[Table 262]

[0837] Assembler syntax VSTQ. st Rs, SRb, SRi VSTQ. st Rs, SRb, #IMM VSTQ. st RS, SRb +, SRi VSTQ. st Rs, SRb +, #IMM where st = {b, b9t, h, w, 4, 8, 16,
32, 64}, Rs = {VRs, VRAs, SR
s｝,. b and. b9t specifies the same operation, 64
Note that both and VRAs cannot be specified. Use VSTQOFF for cache off storage.

Description Stores 4 vector registers from the current or replacement bank or 4 scalar registers.

Operation EA = SR _b + {SR _i {sex (IMM <7: 0>)}; if (A == 1) SR _b = EA; MEM [EA] = see table bello
w;

[0840]

[Table 263]

Exceptions Data Address, Unaligned Access Invalid Programming Note This instruction is not affected by the element mask.

VSTR Reverse Order Storage

[0843]

[Table 264]

[0844] Assembler syntax VSTR. st Rs, SRb, SRi VSTR. st Rs, SRb, #IMM VSTR. st RS, SRb +, SRi VSTR. st Rs, SRb +, #IMM where st = {b, b9t, h, w, 4, 8, 16,
32, 64}, Rs = {VRs, VRAs, SR
s｝,. Note that 64 and VRAd cannot be specified together. VSTROF for cache off storage
Use F.

Description Stores vector registers in reverse element order. This instruction does not support scalar data source registers.

[0846] calculation EA = SR _b + {SRi ‖ sex (IMM <7: 0>)}; if (A == 1) SR b = EA; MEM [EA] = see table below;

[0847]

[Table 265]

Exceptions Data Address, Unaligned Access Invalid Programming Note This instruction is not affected by the element mask.

[0849] VSTWS Stride Memory

[0850]

[Table 266]

[0851] Assembler syntax VSTWS. st Rs, SRb, SRi VSTWS. st Rs, SRb, #IMM VSTWS. st RS, SRb +, SRi VSTWS. st Rs, SRb +, #IMM where st = {4, 8, 16, 32}, Rs = {VR
s, VRAs},. Note that the 64 mode is not supported and uses VST instead. Use VSTWSOFF for cache off storage.

Description Starting from the effective address, the stride control register (Strid
e Control Register) as scalar register SRb + 1
, 32 bytes are stored in the memory from the vector register VRs.

[0853] ST specifies the number of continuous bytes and the block size for storage from each block. SRb +
1 specifies the byte number and stride separating the start of two consecutive blocks.

The stride must be equal to or larger than the block size. EA must be aligned data size. Stride and block size should be many times the data size.

Operation EA = SR _b + ｛SR _i ‖ sex (IMM <7: 0>)｝; if (A == 1) SR _b = EA; Block size = ｛4 ‖ 8 ‖ 16 ‖ 32｝; Stride = SR _{b + 1} <31: 0>; for (i = 0; j <VECSIZE / Block size; i ++) for (j = 0; j <Block size; j ++) BYTE ｛EA + i ^* Stride + j] = VR _s (i ^* Block size + j] <7: 0>; Exception Data address, non-aligned access invalid VSUB subtraction

[0856]

[Table 267]

[0857] Assembler syntax VSUB. st VRd, VRa, VRb VSUB. st VRd, VRa, SRb VSUB. st VRd, VRa, #IMM VSUB. st SRd, SRa, SRb VSUB. st SRd, SRa, #IMM where st = {b, b9t, h, w, f}

[0858]

[Table 268]

[0859] Description: The contents of vector / scalar register Rb are subtracted from the contents of vector / scalar register Ra, and the result is stored in vector / scalar register Rd.

[0860] Exception overflow, floating point invalid operand VSUBS subtraction and set

[0861]

[Table 269]

[0832] Assembler syntax VSUBS. dt SRd, SRa, SRb VSUBS. dt SRd, SRa, #IMM where dt = {b, b9, h, w, f}.

[0863]

[Table 270]

[0864] Description: SRb is subtracted from SRa, the result is stored in SRd, and the VFLAG bit is set in VCSR.

Operation Bop = {SRb} sex (IMM <8: 0>)}; SRd = SRa-Bop; VCSR <lt, eq, gt> = status (SRa-Bop); Exception Overflow, floating point invalid operand VUNSHFL Unshuffle

[0866]

[Table 271]

[0867] Assembler syntax VUNSHFL. dt VRc, VRd, VRa, VR
b VUNSHFL. dt VRc, VRd, VRa, SR
b where dt = {b, b9, h, w, f}. . w and. f
Specifies the same operation.

[0868]

[Table 272]

[0869] Description The contents of the vector register VRb are unshuffled with Rb in the vector register VRc: VRd as shown below.

[0870]

[Table 273]

Operation Exceptions None.

Programming Notes This instruction does not use an element mask.

[0873] VUNSHFLH High Anshuff
Le

[0874]

[Table 274]

[0887] Assembler syntax VUNSHFLH. dt VRd, VRa, VRb VUNSHFLH. dt VRd, VRa, SRb where dt = {b, b9, h, w, f},. w and. f
Specify the same operation.

[0876]

[Table 275]

[0877] Description The contents of the vector register Ra are unshuffled with Rb as described below, and the upper part of the result is returned to the vector register Rd.

[0878]

[Table 276]

Operation Exceptions None Programming Note This instruction does not use an element mask.

[0880] VUNSHFLL Low unshuffle

[0881]

[Table 277]

[0882] Assembler syntax VUNSHFLLL. dt VRd, VRa, VRb VUNSHFLLL. dt VRd, VRa, SRb where dt = {b, b9, h, w, f},. w and. f
Specify the same operation.

[0883]

[Table 278]

Description The contents of the vector register Ra are unshuffled with Rb as described below, and the upper part of the result is returned to the vector register Rd.

[0885]

[Table 279]

Operation Exceptions None Programming Notes This instruction does not use an element mask.

[0887] VWBACK re-recording

[0888]

[Table 280]

[0889] Assembler syntax VWBACK. ln SRb, SRi VWBACK. ln SRb, #IMM VWBACK. ln SRb +, SRi VWBACK. ln SRb +, #IMM where ln = {1, 2, 4, 8}.

Description The cache line indexed by the EA in the vector data cache (as opposed to the one whose tag matches the EA) is updated to memory if it contains modified data. If more than one cache line is specified, the next sequential cache line will be updated to memory if they contain modified data. The number of cache lines is specified as follows: LN (1: 0) = 00: One 64-byte cache line is recorded.

[0891] LN (1: 0) = 01: Two 64-byte cache lines are recorded.

[1030] LN (1: 0) = 10: Four 64-byte cache lines are recorded.

[0893] LN (1: 0) = 11: Eight 64-byte cache lines are recorded.

If the valid address is not on a 64-byte boundary, it is truncated first so that it is aligned on a 64-byte boundary.

[0895] Operation Exception Data address exception invalid Invalid programming note EA (31: 0) indicates the byte address of the local memory.

[ 0896 ] VWBACKSP Replay from temporary pad.
Record

[0897]

[Table 281]

[0898] Assembler syntax VWBACKSP. ln SRp, SRb, SRi VWBACKSP. ln SRp, SRb, #IMM VWBACKSP. ln SRp, SRb +, SRi VWBACKSP. ln SRp, SRb +, #IMM where ln = {1, 2, 4, 8}, VWBACK and V
WBACKSP uses the same operation code.

Description A number of 64-byte blocks are transmitted from the temporary pad to the memory. The effective address provides the start address to the memory, and SRp provides the start address to the temporary pad. 6
The number of 4-byte blocks is specified as follows: LN (1: 0) = 00: One 64-byte block is recorded.

[0900] LN (1: 0) = 01: Two 64-byte blocks are recorded.

LN (1: 0) = 10: Four 64-byte blocks are recorded.

LN (1: 0) = 11: Eight 64-byte blocks are recorded. If the effective address is not on a 64-byte boundary, it is truncated first so as to be aligned on the 64-byte boundary. If the temporary pad pointer address of SRp is not at a 64-byte boundary, it is truncated first to be aligned at the 64-byte boundary. The aligned temporary pad pointer address is incremented by the number of bytes transmitted.

[0903] Exception Data address exception invalid VXNOR XNOR (Exclusive NOR)

[0904]

[Table 282]

[0905] Assembler syntax VXNOR. dt VRd, VRa, VRb VXNOR. dt VRd, VRa, SRb VXNOR. dt VRd, VRa, #IMM VXNOR. dt SRd, SRa, SRb VXNOR. dt SRd, SRa, #IMM where dt = {b, b9, h, w, f}.

[0906]

[Table 283]

Description The contents of vector / scalar register Ra are logically XNORed into the contents of vector / scalar register Rb, and the result is stored in vector / scalar register Rd.

Operation for (i = 0: i <NumElem && EMASK [i]; i ++) ｛Bop [i] = ｛VRb [i] ‖SRb‖sex (IMM <8.0>)｝; Rd [i] <K > =-(Ra [i] <k> ＾ Bop [i] <k>, for k = all bits in element i;｝ Exception None VXOR XOR (Exclusive OR)

[0909]

[Table 284]

[0991] Assembler syntax VXOR. dt VRd, VRa, VRb VXOR. dt VRd, VRa, SRb VXOR. dt VRd, VRa, #IMM VXOR. dt SRd, SRa, SRb VXOR. dt SRd, SRa, #IMM where dt = {b, b9, h, w}.

[0911]

[Table 285]

Description The contents of vector / scalar register Ra are logically XORed with the contents of vector / scalar register Rb, and the result is stored in vector / scalar register Rd.

Operation for (i = 0: i <NumElem && EMASK [i]; i ++) ｛Bop [i] = ｛VRb [i] ‖SRb‖sex (IMM <8: 0>)｝; Rd [i] <k> = Ra [i] <k> ＾ Bop [i] <k>), for k = all bits in element i;｝ Exception None VXORALL All elements XOR (exclusive
OR)

[0914]

[Table 286]

[0915] Assembler syntax VXORALL. dt SRd, VRb where dt = {b, b9, h, w, f},. b and. b
9 indicates the same operation

[0916]

[Table 287]

Description In VRb, the least significant bit of each element is XORed together, and the 1-bit result is returned to the least significant bit of SRd. This instruction is not affected by the element mask.

Operation Exceptions None

[Brief description of the drawings]

FIG. 1 is a block diagram of a multimedia signal processor according to an embodiment of the present invention.

FIG. 2 is a block diagram of a vector processor of the multimedia signal processor shown in FIG. 1;

FIG. 3 is a block diagram of an instruction fetch unit in the vector processor shown in FIG. 2;

FIG. 4 is a block diagram of an instruction fetch unit in the vector processor shown in FIG. 2;

5 is a stage diagram showing a stage execution pipeline for a register-to-register instruction in the vector processor shown in FIG. 2;

FIG. 6 is a stage diagram showing an execution pipeline for executing a load instruction in the vector processor shown in FIG. 2;

FIG. 7 is a stage diagram showing an execution pipeline for executing a stored instruction word in the vector processor shown in FIG. 2;

FIG. 8 is a block diagram of an execution data path in the vector processor shown in FIG. 2;

FIG. 9 is a block diagram of a register file in the execution data path shown in FIG. 8;

FIG. 10 is a block diagram of a parallel processing logic unit in the execution data path shown in FIG. 8;

FIG. 11 is a block diagram of a load / store unit in the vector processor shown in FIG. 2;

FIG. 12 is a format diagram of an instruction set of the vector processor according to the embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 100 Multimedia processor 105 Processing core 110 Main processor 115 Extension register 120 Vector processor 130 Cache subregister 140 System bus 142 System timer 144 Full duplex UART 146 Bit stream processor 148 Interrupt controller 150 System bus 152 Device interface 154 DMA controller 156 Local bus Controller 158 Memory controller 160, 190 SRAM 162, 192 Instruction cache 164, 194 Data cache 170 ROM 180 Cache control 210 Instruction fetch unit (IFU) 220 Decoder 230 Scheduler 230 Execution data path 250 Load / storage unit (LSU) 61 0 Register file

Continuing on the front page (72) Inventor Litron Guyen, USA 95030 Monteselena Daniel Place, California 15095 (72) Inventor Ronnie Sir Don Won United States of America 94086 Sunnyvale Larkspur Ave 946

Claims (9)

[Claims] A scalar register adapted to store a single scalar value; a vector register adapted to store a number of data elements; coupled to the scalar register and the vector register. In response to a single instruction, wherein the processing circuit performs in parallel an operation in which each operation combines one of the data elements from the vector register with a scalar value from the scalar register. A processor, characterized in that: 2. A method of operating a processing circuit for executing an instruction, comprising: reading from a register data element forming a vector value component; and combining a scalar value with the respective data element to generate a vector result. Performing a calculation. 3. The method as claimed in claim 2, wherein the parallel performing step multiplies the scalar value by the respective data elements to generate a vector data result. 4. The method of claim 2, wherein the parallel performing step adds the scalar value to each of the data elements to generate a vector data result. 5. The method of claim 1, further comprising reading the scalar value from a second register for combining with the data element, wherein the second register is adapted to store a single scalar value. The processing circuit operation method according to claim 2. 6. The method of claim 2, further comprising extracting the scalar value from the instruction to combine with the data element. 7. A method of operating a processor, wherein each scalar register is adapted to store a single scalar value, and each vector register is adapted to store a number of data elements forming a vector component. Providing a scalar register and a vector register in the processor; assigning a register number to each scalar register that is distinct from a register number assigned to another scalar register; and Assigning a register number to each vector register, wherein at least some of the register numbers are the same as the register numbers assigned to the scalar registers, and distinguishing the register numbers from the register numbers assigned to other vector registers Know the registers Forming an instruction including a first operand that is a register number to be executed and a second operand that is a register number for identifying a vector register; and identifying the scalar register identified by the first operand and the second operand. Moving the data to and from a data element in the vector register and executing the instruction. 8. The formed instruction further includes a third operand identifying a data element in the vector,
Moving data between the scalar register identified by the first operand and the data element identified by the third operand in the vector register identified by the second operand to execute an instruction; The processor operation method according to claim 7, further comprising: 9. The formed instruction further includes a third operand identifying a second scalar register, wherein the scalar register identified by the first operand and the second scalar register identified by the second operand are stored in the second operand. 8. The method of claim 7, further comprising moving data to and from a data element in the vector register identified by a stored value and executing an instruction.