JPH0153500B2 - - Google Patents
Info
- Publication number
- JPH0153500B2 JPH0153500B2 JP58071362A JP7136283A JPH0153500B2 JP H0153500 B2 JPH0153500 B2 JP H0153500B2 JP 58071362 A JP58071362 A JP 58071362A JP 7136283 A JP7136283 A JP 7136283A JP H0153500 B2 JPH0153500 B2 JP H0153500B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- sio
- alloy
- etching
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910045601 alloy Inorganic materials 0.000 claims description 21
- 239000000956 alloy Substances 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 14
- 229910052802 copper Inorganic materials 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 7
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 6
- 229910017604 nitric acid Inorganic materials 0.000 claims description 6
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims 5
- 238000000151 deposition Methods 0.000 claims 1
- 238000010030 laminating Methods 0.000 claims 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 31
- 125000006850 spacer group Chemical group 0.000 description 14
- 229910000881 Cu alloy Inorganic materials 0.000 description 12
- 229910018182 Al—Cu Inorganic materials 0.000 description 11
- 238000002955 isolation Methods 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 8
- 238000001020 plasma etching Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 229910017855 NH 4 F Inorganic materials 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000005477 sputtering target Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Weting (AREA)
Description
【発明の詳細な説明】
［発明の技術分野］
本発明は例えば半導体基板上に素子分離領域を
形成する際に用られる半導体装置の製造方法に関
する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device used, for example, when forming an element isolation region on a semiconductor substrate.
［発明の技術的背景とその問題点］
半導体基板上に回路パターンを形成する技術の
一つにリフトオフがある。リフトオフの技術は、
例えば半導体基板に形成されたトランジスタ等の
複数の素子を互いに分離するために、素子分離領
域を半導体基板上に設ける際に用いられる。従来
のリフトオフを用いた素子分離方法の一例を第１
図に示す。シリコン（Si）基板１上に二酸化シリ
コン（SiO2）膜２及びアルミニウム（Al）膜３
を順次形成する（第１図ａ）。[Technical background of the invention and its problems] Lift-off is one of the techniques for forming a circuit pattern on a semiconductor substrate. Lift-off technology is
For example, it is used when providing an element isolation region on a semiconductor substrate in order to isolate a plurality of elements such as transistors formed on the semiconductor substrate from each other. An example of an element isolation method using conventional lift-off is shown in the first example.
As shown in the figure. A silicon dioxide (SiO 2 ) film 2 and an aluminum (Al) film 3 are formed on a silicon (Si) substrate 1.
are sequentially formed (Fig. 1a).
次にフオトエツチング法により素子形成領域上
にレジスト膜４を形成する（第１図ｂ）。このレ
ジスト膜４をマスクにして、Al膜３、SiO2膜２
及びSi基板１をリアクテイブイオンエツチング
（RIE）技術を用いてエツチングする（第１図
ｃ）。残存したAl膜３がリフトオフを行うための
スペーサとなる。レジスト膜４を除去した後、プ
ラズマCVD法によりSiO2膜５を堆積させる。（第
１図ｄ）この時SiO2膜５の膜厚は素子形成領域
と素子分離領域の境界の段差部において他部より
もかなり薄い。このため次にNH4F溶液でSiO2膜
５のエツチングを行うと段差部のSiO2膜は速く
除去され、SiO2膜５は素子分離領域と素子形成
領域とに分離される（第１図ｅ）。その後スペー
サであるAl膜３をエツチングにより除去し、同
時に素子形成領域上のSiO2膜５を除去する（第
１図ｆ）。このようにしてSiO2膜５のリフトオフ
を行い、素子分離領域を形成する。 Next, a resist film 4 is formed on the element formation region by photoetching (FIG. 1b). Using this resist film 4 as a mask, Al film 3, SiO 2 film 2
Then, the Si substrate 1 is etched using reactive ion etching (RIE) technology (FIG. 1c). The remaining Al film 3 serves as a spacer for lift-off. After removing the resist film 4, a SiO 2 film 5 is deposited by plasma CVD. (FIG. 1d) At this time, the thickness of the SiO 2 film 5 is considerably thinner at the stepped portion at the boundary between the element formation region and the element isolation region than at other portions. Therefore, when the SiO 2 film 5 is etched next with an NH 4 F solution, the SiO 2 film at the stepped portion is quickly removed, and the SiO 2 film 5 is separated into an element isolation region and an element formation region (Fig. 1). e). Thereafter, the Al film 3 serving as a spacer is removed by etching, and at the same time the SiO 2 film 5 on the element formation region is removed (FIG. 1f). In this way, the SiO 2 film 5 is lifted off to form an element isolation region.
リフトオフ技術を用いて素子分離を行う際には
スペーサの側面に形成されるSiO2膜の膜厚はで
きる限り薄いことが望ましいが、従来の方法では
スペーサ側面にかなり厚いSiO2膜が形成される
のが避けられない。このためSiO2膜５を素子形
成領域と素子分離領域に分離するためにエツチン
グを行うと素子形成領域の周囲に大きなＶ字溝６
が形成されてしまう。このＶ字溝６をそのままに
しておくと金属配線を行う際に断線等が起きる原
因となるため、Ｖ字溝６にSiO2を埋め込むこと
により平面を平坦化することが必要となるが、充
分な平坦度を得るのは難しい。また平坦化する工
程も複雑であり、長い処理時間が必要となる。 When performing element isolation using lift-off technology, it is desirable that the SiO 2 film formed on the side of the spacer be as thin as possible, but in conventional methods, a fairly thick SiO 2 film is formed on the side of the spacer. is unavoidable. Therefore, when etching is performed to separate the SiO 2 film 5 into an element formation region and an element isolation region, a large V-shaped groove 6 is formed around the element formation region.
is formed. If this V-shaped groove 6 is left as it is, it may cause disconnection when metal wiring is performed, so it is necessary to flatten the plane by filling SiO 2 into the V-shaped groove 6, but it is not enough. It is difficult to obtain good flatness. Furthermore, the planarization process is complicated and requires a long processing time.
［発明の目的］
本発明は上記の事情を鑑みてなされたもので、
リフトオフを行う際のスペーサに適した形状の合
金膜を得ることができる半導体装置の製造方法を
提供することを目的とする。[Object of the invention] The present invention was made in view of the above circumstances, and
It is an object of the present invention to provide a method for manufacturing a semiconductor device that can obtain an alloy film having a shape suitable for a spacer during lift-off.
［発明の概要］
半導体基板上にAlとCuとを含み、半導体基板
側においてCu濃度が高い第一の膜を形成する。
この第一の膜を硝酸を含むエツチング液によりエ
ツチングすると、Cu濃度が高い半導体基板側の
部分の第一の膜が速くエツチングされ、第一の膜
の段差部はオーバーハング状となる。この上に第
二の膜を形成すると、その膜厚は第一の膜の側面
において他部よりもかなり薄くなるため良好なリ
フトオフを行うことができる。[Summary of the Invention] A first film containing Al and Cu and having a high Cu concentration on the semiconductor substrate side is formed on a semiconductor substrate.
When this first film is etched with an etching solution containing nitric acid, the portion of the first film on the semiconductor substrate side where the Cu concentration is high is etched quickly, and the stepped portion of the first film becomes overhang-like. When a second film is formed on top of this, the thickness of the second film becomes considerably thinner on the side surfaces of the first film than on other parts, so that good lift-off can be performed.
［発明の実施例］
本発明の第一の実施例を図面を参照して説明す
る。第２図に本発明を用いた素子分離の工程図を
示す。まず始めにSi基板１１上にSiO2膜１２を
形成した後、Al−Cu合金膜１３をスパツタリン
グにより形成する（第２図ａ）。この時Al−Cu合
金膜１３中のCu濃度はAl−Cu合金膜１３の厚さ
方向に関して不均一になつている。例えばCuを
２％含んだAl−Cu合金をターゲツトとして用い
てAl−Cu合金膜１３を形成するならば、Al−Cu
合金膜１３中のCu濃度は第３図のようになる。
Al−Cu合金膜１３の厚さ方向のCu濃度は表面部
において２％弱であり、深さが深くなるにつれ漸
増した後急減する。そしてSiO2膜１２との境界
面に近づくと再びCu濃度は増大し始め、SiO2膜
１２との境界部では約８％という高濃度となる。[Embodiments of the Invention] A first embodiment of the present invention will be described with reference to the drawings. FIG. 2 shows a process diagram of element isolation using the present invention. First, an SiO 2 film 12 is formed on a Si substrate 11, and then an Al--Cu alloy film 13 is formed by sputtering (FIG. 2a). At this time, the Cu concentration in the Al--Cu alloy film 13 is non-uniform in the thickness direction of the Al--Cu alloy film 13. For example, if the Al-Cu alloy film 13 is formed using an Al-Cu alloy containing 2% Cu as a target, the Al-Cu
The Cu concentration in the alloy film 13 is as shown in FIG.
The Cu concentration in the thickness direction of the Al--Cu alloy film 13 is a little less than 2% at the surface, gradually increases as the depth increases, and then rapidly decreases. Then, as it approaches the interface with the SiO 2 film 12, the Cu concentration begins to increase again, reaching a high concentration of about 8% at the interface with the SiO 2 film 12.
次にフオトエツチング法により素子形成領域１
２上にレジスト膜１４を形成する。このレジスト
膜１４をマスクにしてRIEを行い素子分離領域の
SiO2膜１２を露出させる。（第２図ｂ）。硝酸を
含んだエツチング液によりAl−Cu合金膜１３の
エツチングを行うと、Cu濃度が高い部分ほど速
くエツチングされる。そのためAl−Cu合金膜１
３側面部においてはSiO2膜１２側がレジスト膜
１４側よりも速くエツチングされ、Al−Cu合金
膜１３の段差部はオーバーハング状となる（第２
図ｃ）。 Next, the element formation area 1 is etched by the photoetching method.
A resist film 14 is formed on 2. Using this resist film 14 as a mask, RIE is performed to form the element isolation region.
The SiO 2 film 12 is exposed. (Figure 2b). When the Al--Cu alloy film 13 is etched with an etching solution containing nitric acid, the higher the Cu concentration, the faster the etching occurs. Therefore, Al-Cu alloy film 1
In the third side part, the SiO 2 film 12 side is etched faster than the resist film 14 side, and the stepped part of the Al-Cu alloy film 13 becomes an overhang (second
Figure c).
再びレジスト膜１４をマスクにして、RIEによ
りSiO2膜１２及びSi基板１１をエツチングした
後、レジスト膜１４を除去する（第２図ｄ）。次
にプラズマCVD法によりSiO2膜１５を堆積させ
る（第２図ｅ）。この時、スペーサとなるAl−Cu
合金膜１３の段差部はオーバーハング状になつて
いるため、このAl−Cu合金膜１３の側面に形成
されたSiO2膜１５の膜厚は他の部分に比較する
と非常に薄くなつている。 Using the resist film 14 as a mask again, the SiO 2 film 12 and the Si substrate 11 are etched by RIE, and then the resist film 14 is removed (FIG. 2d). Next, a SiO 2 film 15 is deposited by plasma CVD (FIG. 2e). At this time, Al-Cu which becomes a spacer
Since the stepped portion of the alloy film 13 has an overhang shape, the thickness of the SiO 2 film 15 formed on the side surface of the Al--Cu alloy film 13 is extremely thin compared to other parts.
次にNH4F溶液を用いてスペーサの側面を露出
させるべくSiO2膜１５のエツチングを行う。（第
２図ｆ）スペーサの側面のSiO2膜１５は膜厚が
薄いため、スペーサの側面を露出させるのに要す
る時間はとても短くてすむ。このためスペーサの
側面部以外のSiO2膜１５のエツチングされる量
は少なく、また素子形成領域の周囲に形成される
Ｖ字溝１６は小さくてすむ。次にスペーサである
Al−Cu合金膜１３をエツチングにより除去し、
同時に素子形成領域上のSiO2膜１５も除去する
（第２図ｇ）。 Next, the SiO 2 film 15 is etched using an NH 4 F solution to expose the side surfaces of the spacers. (FIG. 2f) Since the SiO 2 film 15 on the side surface of the spacer is thin, the time required to expose the side surface of the spacer is very short. Therefore, the amount of the SiO 2 film 15 other than the side surfaces of the spacer that is etched is small, and the V-shaped groove 16 formed around the element forming region can be small. Next is the spacer
The Al-Cu alloy film 13 is removed by etching,
At the same time, the SiO 2 film 15 on the element formation region is also removed (FIG. 2g).
本実施例によれば素子形成領域の周囲に形成さ
れるＶ字溝１６は小さいため、素子を形成後に金
属配線を行つても配線の断線が起こる恐れは小さ
い。またＶ字溝１６にSiO2を埋め込めば良好な
平坦度を得ることができる。 According to this embodiment, since the V-shaped groove 16 formed around the element forming region is small, there is little risk of disconnection of the wiring even if metal wiring is formed after forming the element. Further, by filling the V-shaped groove 16 with SiO 2 , good flatness can be obtained.
本実施例においてはスパツタリングのターゲツ
トとしてAlのCuより成る合金を用いたが、Al及
びCu以外の元素がターゲツトに含まれていても
形成された合金膜中におけるCu濃度分布が第３
図と同様な傾向を示す限り、硝酸を含んだエツチ
ング液を用いてエツチングを行えば段差部がオー
バーハング状となつた合金膜を得ることができ
る。 In this example, an alloy of Al and Cu was used as the sputtering target, but even if the target contained elements other than Al and Cu, the Cu concentration distribution in the formed alloy film would be
As long as the same tendency as shown in the figure is shown, an alloy film with an overhanging stepped portion can be obtained by etching using an etching solution containing nitric acid.
次に第４図を用いて本発明の第二の実施例を説
明する。Si基板２１上にSiO2膜２２を形成した
後、例えばスパツタリングによりCuを８％含む
Al−Cu合金膜２３ａを形成する。さらにその上
にCuをそれぞれ５及び２％含むAl−Cu合金膜２
３ｂ，２３ｃを順次形成する（第４図）。フオト
エツチング法を用いてレジスト膜を所定領域に形
成し、このレジスト膜をマスクにしてRIEを行つ
てAl−Cu合金膜２３を所定領域にのみ残存させ
る。次に硝酸を含んだエツチング液を用いてAl
−Cu合金膜２３をエツチングするとCu濃度が高
い部分ほどよくエツチングされるため、Al−Cu
合金膜２３の段差部はオーバーハング状となる。 Next, a second embodiment of the present invention will be described using FIG. 4. After forming the SiO 2 film 22 on the Si substrate 21, the SiO 2 film 22 containing 8% Cu is formed by sputtering, for example.
An Al--Cu alloy film 23a is formed. Furthermore, Al-Cu alloy film 2 containing 5% and 2% Cu, respectively.
3b and 23c are formed in sequence (FIG. 4). A resist film is formed in a predetermined region using a photoetching method, and RIE is performed using this resist film as a mask to leave the Al--Cu alloy film 23 only in a predetermined region. Next, Al was etched using an etching solution containing nitric acid.
- When etching the Cu alloy film 23, the areas with higher Cu concentration are etched better, so Al-Cu
The stepped portion of the alloy film 23 has an overhang shape.
本実施例によればAl−Cu合金膜２３ａ，２３
ｂ，２３ｃそれぞれの膜厚やCu濃度を適宜選択
することによりAl−Cu合金膜２３の段差部の形
状を容易に制御することができる。 According to this embodiment, the Al-Cu alloy films 23a, 23
The shape of the stepped portion of the Al--Cu alloy film 23 can be easily controlled by appropriately selecting the film thickness and Cu concentration of each of the Al--Cu alloy film 23b and 23c.
［発明の効果］
本発明によればAlとCuとを含む合金膜の段差
部を容易にオーバーハング状にすることができ
る。そして本発明により得られた合金膜をSiO2
膜のリフトオフを行う際のスペーサとして用いれ
ば、スペーサ側面に形成されるSiO2膜の膜厚は
薄いためスペーサ段差部において容易にSiO2膜
を分離させることができ、良好なリフトオフを行
うことができる。[Effects of the Invention] According to the present invention, the stepped portion of the alloy film containing Al and Cu can be easily formed into an overhang shape. Then, the alloy film obtained according to the present invention was made of SiO 2
If used as a spacer when performing film lift-off, the SiO 2 film formed on the side surface of the spacer is thin, so the SiO 2 film can be easily separated at the spacer step, and good lift-off can be performed. can.
第１図ａ〜ｆは従来の素子分離方法を示す断面
図、第２図ａ〜ｇは本発明の第一の実施例を示す
断面図、第３図はAl−Cu合金膜中のCu濃度を示
すグラフ、第４図は本発明の第二の実施例を示す
断面図である。
１１，２１……Si基板、１３，２３……Al−
Cu合金膜。
Figures 1 a to f are cross-sectional views showing the conventional device isolation method, Figures 2 a to g are cross-sectional views showing the first embodiment of the present invention, and Figure 3 is the Cu concentration in the Al-Cu alloy film. FIG. 4 is a cross-sectional view showing a second embodiment of the present invention. 11, 21...Si substrate, 13, 23...Al-
Cu alloy film.
Claims (1)
程と、前記シリコン酸化膜の一主面上にAlとCu
とを含み前記主面側においてCu濃度が高い合金
膜を形成する工程と、 硝酸を含むエツチング液により前記合金膜を所
定時間エツチングする工程とを備えたことを特徴
とする半導体装置の製造方法。 ２ 前記合金膜はスパツタリングにより形成され
ることを特徴とする請求項１記載の半導体装置の
製造方法。 ３ 前記合金膜はCu濃度が異なる複数の膜が積
層されてなることを特徴とする請求項１記載の半
導体装置の製造方法。 ４ 半導体装置上にシリコン酸化膜を形成する工
程と、前記シリコン酸化膜の一主面上にAlとCu
とを含み前記主面側においてCu濃度が高い第一
の膜を形成する工程と、 硝酸を含むエツチング液により前記第１の膜を
所定時間エツチングする工程と、 第２の膜を被着させる工程と、 前記第１の膜の側面が露出するまで前記第２の
膜をエツチングする工程と、 前記第１の膜をエツチングして除去する工程と
を備えたことを特徴とする半導体装置の製造方
法。 ５ 前記第２の膜はシリコン酸化膜であることを
特徴とする請求項４記載の半導体装置の製造方
法。[Claims] 1. A step of forming a silicon oxide film on a semiconductor substrate, and forming Al and Cu on one main surface of the silicon oxide film.
1. A method of manufacturing a semiconductor device, comprising: forming an alloy film having a high Cu concentration on the main surface side; and etching the alloy film for a predetermined period of time with an etching solution containing nitric acid. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the alloy film is formed by sputtering. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the alloy film is formed by laminating a plurality of films having different Cu concentrations. 4 Step of forming a silicon oxide film on a semiconductor device, and forming Al and Cu on one main surface of the silicon oxide film.
forming a first film with a high Cu concentration on the main surface side; etching the first film for a predetermined time with an etching solution containing nitric acid; and depositing a second film. A method for manufacturing a semiconductor device, comprising: etching the second film until a side surface of the first film is exposed; and etching and removing the first film. . 5. The method of manufacturing a semiconductor device according to claim 4, wherein the second film is a silicon oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7136283A JPS59197140A (en) | 1983-04-25 | 1983-04-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7136283A JPS59197140A (en) | 1983-04-25 | 1983-04-25 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59197140A JPS59197140A (en) | 1984-11-08 |
| JPH0153500B2 true JPH0153500B2 (en) | 1989-11-14 |
Family
ID=13458307
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7136283A Granted JPS59197140A (en) | 1983-04-25 | 1983-04-25 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59197140A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5394771A (en) * | 1977-01-29 | 1978-08-19 | Fujitsu Ltd | Forming method for thin film pattern |
-
1983
- 1983-04-25 JP JP7136283A patent/JPS59197140A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5394771A (en) * | 1977-01-29 | 1978-08-19 | Fujitsu Ltd | Forming method for thin film pattern |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59197140A (en) | 1984-11-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4505025A (en) | Method for manufacturing a semiconductor device | |
| US4007103A (en) | Planarizing insulative layers by resputtering | |
| JPH0569292B2 (en) | ||
| US3419956A (en) | Technique for obtaining isolated integrated circuits | |
| JP2822430B2 (en) | Method of forming interlayer insulating film | |
| US4775644A (en) | Zero bird-beak oxide isolation scheme for integrated circuits | |
| JPH0153500B2 (en) | ||
| US4178635A (en) | Planar and near planar magnetic bubble circuits | |
| JPH0336302B2 (en) | ||
| JPS5893270A (en) | Manufacture of semiconductor device | |
| JPS5871638A (en) | Etching method | |
| JPS5928358A (en) | Manufacture of semiconductor device | |
| JPH079930B2 (en) | Method for manufacturing semiconductor device | |
| US4280195A (en) | Planar and near planar magnetic bubble circuits | |
| JPH0194623A (en) | Manufacture of semiconductor device with multilayer interconnection | |
| JPH0194625A (en) | Manufacture of semiconductor integrated circuit | |
| JPS61244042A (en) | Formation of element isolation region | |
| JPH01143236A (en) | Manufacture of semiconductor device | |
| JPH0713958B2 (en) | Method for manufacturing semiconductor device | |
| JPS6218034A (en) | Manufacture of semiconductor device | |
| JPS58210168A (en) | Etching method of two-layered film | |
| JPS6189633A (en) | Manufacture of semiconductor device | |
| JPS6116545A (en) | Manufacture of semiconductor integrated device | |
| JPS62222658A (en) | Formation of conductor wiring | |
| JPS5864033A (en) | Manufacture of semiconductor device |