JPH0152776B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input/output control device particularly suitable for multiplexer channels.

A multiplexer channel is typically connected to multiple input/output devices. The multiplexer channel then receives interrupts from input/output devices, or
Each time a channel activation command is issued from the CPU (central processing unit), the input/output device is switched and data transfer control between the main memory and the input/output device is performed. FIG. 1 shows the conventional operating procedure of such a multiplexer channel. Interrupts from input/output devices
(A), or when the CPU executes a channel start command (B), the channel is interrupted by an interrupt from an input/output device (A).
If so, execute the microinstruction that imports the interrupt device number into the channel (C), and execute the channel control block (hereinafter referred to as
(referred to as CCB) and decipher it (D). Next, the channel executes a microinstruction for connecting the channel and the input/output device (E). This results in
The address FF of the corresponding input/output device is set.
(F), the above connection is terminated. and. Thereafter, the input/output bus control (data transfer control) by the channel will be performed on the above-mentioned connected input/output devices.

Next, the channel executes microinstructions to prepare for data transfer (G). That is, the channel sets the start address in the memory address register, sets the number of transferred bytes in the counter, and then sets data in the read data buffer. Next, the channel executes a microinstruction to import the status of the input/output device into the channel, and performs a status check (H). If the status is normal, the channel performs data transfer (transfer/reception) (I) and updates the CCB (J). By updating the CCB, the start address is increased by 1 and the number of transferred bytes is decreased by 1. When such an operation is repeatedly executed and the number of transferred bytes reaches "0", the channel interrupts the CPU via the DMA bus. This notifies the CPU that the operation specified by the CCB has ended.

As is clear from the above explanation, conventional multiplexer channels connect input/output devices (E), read status, check (F), and transfer data.
While various input/output bus control microinstructions such as (I) were being executed, other microinstructions could not be processed, and all processing operations were performed serially. Moreover,
Since input/output bus control operations such as connection (E) of input/output devices generally require time, it has been extremely difficult to improve processing efficiency (throughput) with conventional multiplexer channels.

The present invention has been made in view of the above circumstances, and its purpose is to be able to execute input/output bus control microinstructions and other microinstructions in parallel as necessary, thereby significantly improving processing efficiency. Its purpose is to provide an input/output control device.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram showing the configuration of an information processing system related to the present invention. In the figure, 111
is the CPU, 112 is the input/output bus, 113, 113
... is an input/output device (I/O). 114 is a main memory, and 115 is a memory control device. 116 is a multiplexer channel to which the present invention is applied, 1
17 is a DMA (Direct Memory Access) bus.

FIG. 3 shows the configuration of the multiplexer channel 116. In the figure, 201 is a high-speed bus driver/receiver circuit through which data on the high-speed DMA bus 117 passes, and 202 is a high-speed bus control circuit. 20
3 is a termination register that notifies the CPU 111 of the end of CCB operation. A read data register 204 holds read data from the memory. A write data register 205 holds write data to the memory 114. A memory address register 206 holds a memory address for data transfer. A CCB address register 207 holds the CCB start address notified to the channel by the channel activation command from the CPU 111. A device number register 208 holds the channel number and device number notified to the channel by the channel activation command from the CPU 111. 209 is internal bus A (A-BUS)
This is the bus through which data from each register, RAM, etc. passes. 210 is a read data buffer register that holds data to be sent to the input/output bus 112, and the microcomputer 220 controls each register,
It is also used as a register to hold data when importing data from RAM, etc. 211 is a write data buffer register that holds data from the input/output bus 112;
It is also used as a register to hold data from 20. 212 is a counter that holds the number of transferred bytes, and is decremented every time data is transferred with the input/output device 113. 213 is a RAM (random access memory) in which CCB, input/output data, etc. are stored. 214 is a CCW register, and RAM
The CCW stored in 213 is retained. 21
5 decodes the CCW and inputs the execution start address of the microprogram to the microphone program counter 217.
This is a decode ROM that informs the 216 is
This is a ROM address selector and a gate that selects a branch destination for the microprogram counter 217. A microprogram counter 217 holds the address of the next microprogram to be executed. This counter 217 is incremented by "1" each time the microprogram is executed, and in the case of a microinstruction that involves a branch,
Holds data from ROM address selector 216. 218 is a ROM in which the microprogram is stored, and 219 is a ROM data register that holds data read from the ROM 218, RD.
**1 is the output line from the ROM data register 219, 220 is the microcomputer, 221
is an input/output bus control circuit, 222 is an internal bus A20
An internal bus control circuit 223 controls a test condition determination circuit. 224 is an internal bus B (B-BUS) through which input/output data with the microcomputer 220, input/output data of the input/output bus 112, etc. are passed. 225 is input/output bus 11
This is an input/output bus driver/receiver circuit for exchanging data between the two. 226 is a register that holds the device number that caused the interrupt;
7 is an SIO stack that holds the device number activated by the channel activation command, and 228 is a stack register that holds the read data of the SIO stack 227. The outputs of the registers 226 and 228 become address information of the RAM 213. 22
Reference numeral 9 is an address register for holding the device number and sending it to the input/output bus 112.

FIG. 4 shows in detail the main part configuration of the input/output bus control circuit 221, and 301 is a register that holds the contents of the ROM data register 219. In this embodiment, when the content held in the ROM data register 219 is an input/output bus control microinstruction in the format shown in FIG. 5, this register 301 contains the mode part (3 bits) and 6-bit information in the register section (3 bits) is held. In Figure 5, OP is the instruction code, MODE is the mode section, and R
is a register part, and STP is a stop designation bit. Here, the instruction code OP indicates an input/output bus control microinstruction. When the input/output bus control microinstruction shown in FIG. 5 is held in the ROM data register 219, the instruction code OP
is decoded by a decoder (not shown), so that the signal CIIO1 becomes active (the number 1 at the end indicates that it is active with logic "1"). The mode section MODE is a field for specifying the type of input/output bus control operation, and the register section R is a field for specifying which register in the channel 116 is to be used during data transfer (transfer/reception). Furthermore, the stop bit STP determines whether to wait for the completion of the I/O bus control operation before proceeding to the next microinstruction, or to proceed to the next microinstruction without waiting for the completion of the I/O bus control operation; This field is used to specify whether or not to perform parallel processing with other microinstructions (hereinafter referred to as stop specification).

A decoder 302 outputs various control signals for input/output bus control operations to the input/output bus 112. The decoder 302 decodes the information of the mode part MODE of the input/output bus control microinstruction held in the register 301 and generates a corresponding control signal.

303 is a (response) signal sent from the input/output devices 113, 113, . . . through the input/output bus 112.
An inverter that receives OSYNL0 (the trailing 0 indicates that it is active at logic "0"), and 304 uses the signal CSYNL0 as the basic clock signal.
This is a D-type flip-flop for synchronization with CBCK11. The flip-flop 304 receives the output of the inverter 303 as a D input, and uses it as a basic clock signal.
CBCK11 is used as clock (CK) input, and signals FSYNL1 and FSYNL1 are output from output terminal Q, respectively.
Generates FSYNL0.

305 is an AND gate which receives the signal CIIO1 and the signal CLBSY0 as inputs. Signal CLBSY0
is a signal indicating whether an input/output operation is being performed between the channel 116 and the input/output device 113, that is, whether the input/output bus control circuit 221 is in operation, and indicates that one input/output operation has been completed. Until then, it remains at logic "0" (active). 3
06 is a JK flip-flop for specifying start/end of input/output control of the input/output bus control circuit 221. Flip-flop 306 receives the output of AND gate 305 as J input, and flip-flop 30
The Q output of 4, that is, the signal FSYNL1, is used as the K input, and the basic clock signal CBCK11 is used as the clock (CK) input, and the signals are output from the output terminal Q.
FIOCT1 and generates signal FIOCT0. this signal
FIOCT1 is input to the clock terminal CK of register 301.

307 is an AND gate which receives the signal FIOCT1 and the output of flip-flop 304, that is, signal FSYNL0, and 308 is a shift register for generating input/output bus control timing. The shift register 308 is an AND gate 30
7 output as data (D) input, basic clock signal
CBCK11 is used as a clock (CK) input, and the input data is sequentially shifted one bit at a time, and the signal is
RLSQ11, signal RLSQ21, and signal RLSQ
31 is generated. This signal RLSQ11 is used as a timing signal for sending the contents held in the register designated by the register section R of the input/output bus control microinstruction to the input/output bus 112. The contents held in the register are sent out while the signal RLSQ31 is active (logic "1"). 309 is an inverter that receives the signal RLSQ21 as an input. This inverter 309 is input to the enable terminal EN of the decoder 302.

310 is the signal RLSQ21 and the signal FSYNL0
It is a NAND gate whose input is . The output of this NAND gate 310 serves as the mode M input of the shift register 308. 311 is the signal
This is a NAND gate that receives FIOCT0 and signal FSYNL0 as inputs. The NAND gate 311 outputs a signal CLBSY indicating the input/output operation state when the NAND condition is not satisfied.
1 (active at logic “1”). 31
2 is an inverter that receives the signal CLBSY1 as an input. The inverter 312 inverts the level of the signal CLBSY1 and generates a signal CLBSY0 (active at logic "0").

313 is the signal CIIO1 and a signal described later.
NAND gate with CRCLK1 as input, 314
is a register that stores the operating state of the input/output bus control circuit 221. This register 314 includes three D-type flip-flops, and receives the signal RD121, the signal CLBSY1, and the signal CLBSY1, which will be described later.
The RLSQ11 is used as a D input, and the output of the NAND gate 313 is used as a clock (CK) input.
The register 314 receives the signal FSTP1 from the output terminal Q in response to the D input of the signal RD121.
1. Generate signal FSTP10. Further, the register 314 outputs the signal FSTP21 and the signal FSTP21 and the signal from the output terminal Q, respectively, corresponding to the D input of the signal CLBSY1.
Generates FSTP20. Similarly, register 314
correspond to the D input of the signal RLSQ11, and the signals FSTP31 and FSTP are output from the output terminal Q, respectively.
Generates 30. The above signal RD121 is ROM
This shows the logic state of the specific output line RD121 in the output line D**1 of the data register 219, and corresponds to the stop bit STP (bit 12) information in the input/output bus control microinstruction shown in FIG. .

315 is an AND gate which receives signals FSTP31 and FSTP11, and 316 is a D-type flip-flop. The flip-flop 316 uses the output of the AND gate 315 as the D input, the signal FIOCT0 as the clock (CK) input, and receives the signal from the output terminal.
Generates FSTP40. This signal FSTP40 is input to the clear input terminal CLR of flip-flop 314.

317 is three AND gates 317 ₁ to 317 ₃
It is an and-or inverter with AND gate 317 ₁ is signal FSTP11 and signal FSTP2
0 and signal FIOCT1 are input. Also,
AND gate 317 ₂ is the signal FSTP31 and the signal
FSTP11 is used as input. And the AND gate ₃₁₇₃ receives the signal FSTP10 and the signal FSTP2.
1, a signal CIIO1, and a signal FIOCT0 as inputs. 318 is the basic clock signal CBCK11
and the output of the AND-OR inverter 317 and the output of the flip-flop 316, i.e., the signal
This is an AND gate that takes FSTP40 as input.
AND gate 316 generates an active ROM clock signal CRCLK1 while the AND condition is satisfied. The fetch cycle for ROM 218 is determined by this ROM clock signal CRCLK1. That is, AND gate 316 determines whether or not to fetch the next microinstruction from ROM 218 to ROM data register 219.

Next, the operation of one embodiment of the present invention will be explained. First, in order to facilitate understanding of the present invention, an explanation will be given centering on the operation of the multiplexer channel 116. When the CPU 111 activates the channel 116, the CPU 111 activates the CCB as shown in FIG.
is stored in a designated area of main memory 114. 6 in the diagram
1 is a channel control word (COW), which is a word that specifies the type of operation (read, write, etc.), chain, etc. 62 is a transfer start address (start address) of the memory (main memory 114) to which data is to be transferred. 63 "Transfer byte count" specifies the data transfer amount (data transfer area), and "command" indicates the input/output device 113.
Specify the command data to be sent to the ``terminal character'' field, and the ``terminal character'' specifies that the data transfer will be terminated if it matches the data specified in this field. 64 is a column in which the channel number (channel address), device number (input/output device address), channel status, and device status are stored at the end of the CCB operation. Chain address 65 specifies chaining to a new CCB after the CCB completes its operation (COW
61), the memory (main memory 1
This field is used to specify the storage start address (CCB address) of the new CCB in 14).

After storing the CCB in the main memory 114, the CPU 111 issues a start I/O command (SIO command) shown in FIG. In the figure, OP is an instruction code, R1 is a general register specification section, and N is a subcode that specifies channel operation. and,
When the CPU 111 executes an SIO instruction, the CPU 111 specified by the general register specification part of the instruction
The contents of the internal R1 register and the contents of the R1+l register are transferred to channel 1 through the DMA bus 117.
16. FIG. 8a shows the contents of the R1 register, where the channel number and device number are specified. Further, FIG. 8b shows the contents of the R1+1 register, which specifies the termination queue number and the CCB storage start address (CCB address).

The subsequent channel operation will be explained with reference to FIG. The R1 register, R
The contents of the 1+l register are held in the device number register 208 and CCB address register 207 through the high-speed bus driver/receiver circuit 201. When the contents of the R1 and R1+l registers are held in the registers 208 and 207, the high-speed bus control circuit 202 transfers the contents to the internal bus control circuit 222.
The request is communicated to When the internal bus control circuit 222 permits the use of the internal bus A209, the data in the CCB address register 207 is transferred to the RAM 213.
Furthermore, the data in the device number register 208 is held in the SIO stack 227. This RAM
213, when the above data is stored in the SIO stack 227, an SIO acceptance signal is transmitted from the internal bus control circuit 222 to the TEST condition determination circuit 223. The TEST condition determination circuit 223 then reads out the SIO acceptance test & branch microprogram from the ROM 218 via the selector 216 and counter 217 and executes it. And then ROM21
By the microprogram read from 8
Start processing SIO command.

The processing of the SIO command will be explained below. ROM2
The microinstructions of the microprogram that processes the SIO instructions from 18 are sequentially read out, and first they are sent to the internal bus control circuit 2 via the ROM data register 219.
When an SIO stack retrieval command is issued to 22, the internal bus control circuit 222 transfers the device number from the SIO stack 227 to the stack register 228.
During this operation, the internal bus control circuit 222
It operates to select stack register 228 as the address of RAM 213. Next ROM218
From, extract the CCB address from RAM213,
A command to set the memory address register 206 is also output to the internal bus control circuit 222 and executed. Thereafter, a memory read command is issued from the ROM 218 to the high-speed bus control circuit 202. When a memory read command is issued, the high-speed bus control circuit 20
2 issues a bus use request to the memory control device 115, and when use of the bus 117 is permitted, the data in the memory address register 206 is sent to the memory control device 115.
Send to 15th. When the memory control device 115 operates to finish reading the memory from the main memory 114 and sends read data to the channel 116, the data is held in the read data register 204. Then, a store command is output from the ROM 218 to the internal bus control circuit 222 and the read data register 20
4 data is stored in the RAM 213. As a result, the CCR in main memory 114 becomes
The data is taken into the RAM 213 in 6. Then, when the above operation is repeated and the CCB is removed,
The internal bus control circuit 222 takes out the data into the CCW register 214 stored in the RAM 213 according to the microinstruction from the ROM 218. The output of the CCW register 214 becomes an address signal for the decode ROM 215, and the decode ROM 215 decodes the CCW, and the address of the next microprogram to be executed is input to the microprogram counter 217 via the ROM address selector 216. . Therefore, the microprogram branches,
The microinstructions of the microprogram that processes the CCB are sequentially read from the ROM 218.

The operation when a write (WRITE) mode command is issued in the CCW will be explained below with reference to the operation state diagram in FIG. First, the input/output device 113 and channel 116
In order to connect the be done. After sending the device number to the input/output bus 112, the input/output bus control circuit 221 sends an address signal CADRL0 (9--) in FIG. 9 indicating that the bus information is the device number.
1) to the input/output bus 112. In addition( )
The numbers inside indicate the correspondence with FIG. 9. The input/output device 113 connected to the input/output bus 112 is
The device number information sent on the input/output bus 112 is compared with a number unique to the device itself, and if a match is found, an address flip-flop (not shown) is set. Although not described in detail, input/output devices generally have a comparison circuit that compares whether the device number information sent from the channel matches a number unique to the device itself, and an address flip-flop that is set when a match occurs. It is well known that it is equipped with a Then, select the input/output device (I/O device) with the matching device number.
When the signal CSYNL0 (9-2) is returned from O), the input/output bus control circuit 221 receives the device number and signal.
Stop sending CADRL0 (9-1).

When the transmission of signal CADRL0 (9-1) is stopped, that is, when signal CADRL0 (9-1) changes from an active state to an inactive state, the signal CSYNL0 (9-2) changes to an inactive state on the input/output device side. be done.

By the way, when the address flip-flop is set to the above-mentioned signal state, subsequent data transfer (transfer/reception) is performed only with the input/output device to which the address flip-flop is set. That is, by setting the address flip-flop, a connection between a channel and an input/output device (hereinafter referred to as an input/output device connection) is established. In other words, connecting an I/O device means setting an address flip-flop in the I/O device. Once the input/output device connection is complete
In response to a microinstruction read from ROM 218, internal bus control circuit 222 sets start address 62 stored in RAM 213 in memory address register 206. Next, the number of bytes transferred is 6.
3 in the counter 212, and then the RAM
213 is set in the read data buffer register 210. This completes the data transfer preparation. The input/output bus control circuit 221 then decodes the microinstruction output from the ROM 218, sends a status request signal CSRQL0 (9-3) to the input/output bus 112, and sends the status request signal CSRQL0 (9-3) to the input/output device 113 in the connected state. take in. Input/output bus control circuit 22
1 checks the status and, if there is no abnormality, transfers the data from the read data buffer 210 to the input/output bus 1.
12 to the input/output device 113. Next, signal CSYNL0 (9) indicates that the input/output bus control circuit 221 has received data from the input/output device 113.
-2), the counter 212 is decremented by "1" by the internal bus control circuit 222, the memory address register 206 is incremented by "1", and the data is stored in the RAM 213 again. Normally high speed
Since the DMA bus 117 has a data width n times the data width of the input/output bus 112, the number of transfer bytes 63 is read from the memory 114 every integral multiple of n and stored in the RAM 213.

When the input/output device 113 finishes its output operation, an interrupt is applied to the channel 116. When an interrupt is accepted, an acknowledge signal CACKL0 (9-6) is sent from the input/output bus control circuit 221 to the input/output device 113 that generated the interrupt via the input/output bus 112. Then, the interrupt device number is set from the input/output device 113 to the interrupt device number register 226 via the input/output bus 112, the input/output bus driver, and the receiver circuit 225. When the input/output bus control circuit 221 outputs the signal CACKL0 (9-6), the interrupt device number register 226 is selected as the subsequent address of the RAM 213. As with the SIO instruction, the CCW of the RAM 213 is read to the CCW register 214, and thereafter data transfer is performed in the same sequence. Note that data is set in the address register 229 when the CCW is taken out from the RAM 213. Thereafter, the same operation is performed every time there is an interrupt from the input/output device 113, and the counter 2
When the contents of 12 become "0", the end state of the operation, that is, the memory address 62, the number of transferred bytes 63, the channel status, the device status 64, etc. at the time of the end of the transfer are stored in the memory 114.

In the operation between the channel and the input/output device, when transferring data from the channel 116 to the input/output device 113, after the input/output bus control circuit 221 sends data to the input/output bus 112, it sends a control signal indicating the meaning of the data. Make it active (logic “0”). As shown in FIG. 9, the data available signal CDAVL0 (9-4) means transfer data to be output to the input/output device (I/O), and the command signal CCMDL0 (9-4)
7) means command data. In addition, the input/output device 113 is connected to the input/output device 113.
When requesting transfer from the I/O to the channel 116, the input/output bus control circuit 221 activates the control signal, and then the requested data is sent from the I/O and the signal CSYNL0 (9
-2) is returned, the input/output bus control circuit 22
1 makes the control signal inactive (logic "1"). As shown in FIG. 9, the status request signal CSRQL0 (9-3) means a request for status data, the data request signal CDRQL0 (9-5) means an input data request, and (interrupt) acknowledgement. Signal CACKL0 (9-
6) means a request to send interrupt device number information.

The above explanation of the operation was made in order to understand the functions centered on the multiplexer channel 116 as described above, and the operation is performed when no other microinstruction is executed while the input/output bus control microinstruction is being executed. This describes the procedure. In other words, the above-mentioned operation is a case where, as shown in the conventional example, after the execution of the input/output bus control microinstruction for connecting the input/output device is completed, the process proceeds to the microinstruction for data transfer preparation.

Next, the operation when another microinstruction is executed in parallel while the input/output bus control microinstruction is being executed, which is directly related to the present invention, will be described with reference to the timing chart shown in FIG. For example, now
It is assumed that the input bus control microinstruction (see FIG. 5) is read from the ROM 218 by the ROM clock signal CRCLK1 (FIG. 10b) and held in the ROM data register 219. It is assumed that this input/output bus control microinstruction is an instruction for connecting an input/output device, and there is no stop specification by the stop bit STP.

When the input/output bus control microinstruction is held in the ROM data register 219, its OP part is decoded by a decoder (not shown), and the signal CIIO1 becomes active (logic "1"). At this time, as shown in Figure 10, the signal
When CLBSY0 is in an inactive state (logic "1"), that is, when the input/output bus control circuit 221 is not operating, the AND condition of the AND gate 305 is satisfied. As a result, the flip-flop 306 enters the set state at the falling timing of the basic clock signal CBCK11 (FIG. 10A), and generates the signal FIOCT1 (logic "1") as shown in FIG. 10C. At this time, the signal FIOCT0 changes from logic "1" to logic "0" state. And the signal
By generating FIOCT1, input/output bus control of the input/output bus control circuit 221 is started. That is, at the timing of the rise of this signal FIOCT1, the 3 bits (bits 5 to 7) of the mode part MODE of the input/output bus control microinstruction held in the ROM data register 219,
Similarly, the 6-bit information of the 3 bits (bits 9 to 11) of the register section R is sent to the input/output bus control circuit 2 via the corresponding output data line RD**1.
The data is taken into the register 301 in 21. Therefore, the input/output bus control microinstructions are stored in the ROM21.
8 to the ROM data register 219, the signal CLBSY0 is in the active state (logic "0"), that is, the input/output bus control circuit 2
21 is operating, the signal FIOCT1 is not generated from the flip-flop 306 (the AND condition of the AND gate 305 is not satisfied), so the microinstruction is not taken into the register 301, and the new input/output bus control is changed to the input/output bus control. This waits until the circuit 221 becomes inactive.

On the other hand, the flip-flop 306 sets the NAND gate 311 so that the signal FIOCT0 becomes logic "1".
The signal at the timing when it changes from to logic “0”
Make CLBSY1 active (logic “1”).
This results in a signal as shown in Figure 10.
CLBSY0 also becomes active (logic “0”),
This indicates that the input/output bus control circuit 221 is in operation.

By the way, as described above, when the signal CIIO1 becomes active, the output of the NAND gate 313 becomes logic "0". Then, the operating state of the input/output bus control circuit 221 (signal RLSQ11, signal OLBSY1, signal RD1
21) is stored in register 314. At this point, the signal CLBSY1 is still at logic “0”;
Furthermore, since there is no stop designation, the signal RD121 is at logic "0" (inactive). Therefore,
FSTP11="0", FSTP21="0",
The AND conditions of the AND gates 317 ₁ to 317 ₃ are all not satisfied. Therefore, the output of the AND-OR inverter 317 becomes logic "1", and the AND gate 318 outputs the basic clock CBCK1.
1, a ROM clock signal CRCLK1 is generated. And this ROM clock signal
The next microinstruction is transferred to ROM2 by CRCLK1.
18 to the ROM data register 219. This microinstruction is an instruction to prepare for data transfer. That is, according to this embodiment, a microinstruction for data transfer preparation is fetched when an input/output bus control microinstruction for connecting an input/output device is executed. This microinstruction is taken into internal bus control circuit 222. Then, as described above, the internal bus control circuit 222 sets the start address 42 stored in the RAM 213 in the memory address register 206 via the internal bus A209. Similarly, the internal bus control circuit 222 receives the next ROM clock signal.
According to the new microinstruction fetched by CRCLK1, the number of bytes transferred is 63 as described above.
is set in the counter 212, and then the RAM
213 is set in the read data buffer register 210. This completes the data transfer preparation. As described above, according to this embodiment, parallel processing of the input/output bus control microinstructions for connecting input/output devices and various microinstructions for data transfer preparation is possible, and processing efficiency is improved.

Next, the execution operation of an input/output bus control microinstruction for connecting an input/output device will be explained. As mentioned above, the operation of the input/output bus control circuit 221 is based on the signal
It is initiated by the occurrence of FIOCT1. and,
The signal FIOCT1 is sequentially shifted into the shift register 308 at the timing of the basic clock signal CBCK11. This allows the shift register 308
is the signal as shown in Figure 10 D, E and F.
RLSQ11, signal RLSQ21, and signal RLSQ31 are made active (logical "1") in sequence at timings shifted by one clock. When the signal RLSQ11 rises, the contents (device number in this case) held in the register (in this case the address register 229) specified by the 3-bit information of the register section R held in the flip-flop 301 are sent onto the internal bus B224. Ru. The input/output bus control circuit 221 sends the device number information on the internal bus B224 to the signal RLSQ31 via the input/output bus driver receiver circuit 225.
While it is in the active state, it is sent to the data bus (not shown) of the input/output bus 112.

When the signal RLSQ21 becomes active, the decoder 302 becomes enabled. As a result, the decoder 302 decodes the 3-bit information of the mode part MODE of the input/output bus control microinstruction held in the flip-flop 301, and outputs the corresponding control signal (in this case, the address signal CADRL0) as shown in FIG. ) occurs. This control signal (address signal
CADRL0) is sent to an unillustrated control signal line (address signal line) of the input/output bus 112.

As mentioned above, the input/output device is the input/output bus 11.
The device number information sent on 2 is compared with the unique number of the own device, and if they match, the address flip-flop is set and the signal CSYNL is
Returns 0. Then, when signal CSYNL0 is returned, flip-flop 304 outputs the basic clock signal.
It is set at the timing of CBCK11, and this signal
A signal FSYNL1 synchronized with CBCK11 is generated from output terminal Q. As a result, flip-flop 3
The K input of 06 becomes K="1". At this point,
As described above, the contents of the ROM data register 219 are microinstructions for data transfer preparation, and therefore the signal CIIO1 is inactive (logic "0"). Therefore, the J input of the flip-flop 306 is J="0", and the flip-flop 306 receives the basic clock signal.
It is reset at the falling edge of CBCK11. As a result, the signal FIOCT1 becomes inactive (logic "0") as shown in FIG. 10C.

The shift register 308 stops the shift operation in response to the output (logic "0") of the NAND gate 310 when the signal RLSQ21 (FIG. 10(e)) becomes active. This NAND gate 310 is
Signal CSYNL0 is returned and flip-flop 3
Since the signal FSYNL0 becomes logic "0" at the time when 04 is set (NAND condition is not satisfied),
Generates a logic "1" signal. As a result, the shift register 308 enters the shift mode again and starts the shift operation from the timing of the next basic clock signal CBCK11. At this time, and gate 3
The AND condition of 07 is not satisfied due to the signal FSYNL0 (logic "0"). For this reason,
“0” data (output of the AND gate 307) is shifted into the shift register 308, which causes the signal RLSQ11, the signal RLSQ21, and the signal
The RLSQ 31 sequentially becomes inactive (logical "0") as shown in FIG. 10 D, E, and F.
When the signal RLSQ21 becomes inactive, the decoder 302 outputs a control signal (address signal) as shown in FIG.
CADRL0) will stop occurring.

Then, when the transmission of the signal CADRL0 is stopped, the input/output device 113
The transmission of the signal CSYNL0 is stopped on the side (FIG. 10-1). In response to the stop of sending the signal CSYNL0, the flip-flop 304 is reset and the signal CSYNL0 is stopped.
FSYNL1 becomes inactive (logic "0") as shown in FIG. On the other hand, the signal
FSYNL0 becomes logic “1”, and as a result, the NAND condition of the NAND gate 311 is satisfied and the signal
CLBSY0 becomes inactive (logic "1").
This indicates that the input/output bus control circuit 221 has completed one input/output operation and has entered a non-operating state.

Next, the ROM clock signal in Figure 10 (b)
A case will be described in which an input/output bus control microinstruction for status reading and checking (following a microinstruction for data transfer preparation) is read by the n-point clock of CRCLK1. It is assumed that this input/output bus control microinstruction has a stop designation. Then, the operating state of the input/output bus control circuit 221 at the time when the microinstruction is taken in (RLQ11="1", CLBSY="1",
RD121="1") is stored in the register 314. As a result, FSTP11="1", FSTP31="
It becomes "1", and the AND condition of AND gate ₃₁₇₂ is satisfied. As a result, the output of the AND-OR inverter 317 becomes logic "0", and the output of the ROM clock signal CRCLK1 is prohibited. This prohibits fetching new microinstructions.

On the other hand, the read input/output bus control microinstruction is processed by a signal as shown in FIG. 10C.
Since FIOCT1 does not rise, it is not held in the register 301. Therefore, even if another input/output bus control microinstruction is fetched into the ROM data register 219 during the execution period of the input/output bus control microinstruction for connecting an input/output device as described above, the instruction is Since this is not executed, there is no risk of malfunction.

As previously mentioned, flip-flop 306 is reset in response to signal FSYNL1, and signal
When FIOCT1 falls and signal FIOCT0 rises, flip-flop 316 operates and holds the output of AND gate 315. in this case,
Since FSTP31="1" and FSTP11="1", the output of AND gate 315 is logic "1", and therefore flip-flop 316 is set. As a result, the Q output of flip-flop 316, ie, signal FSTP40, becomes logic "0". Then, in response to the falling of the signal FSTP40,
Flip-flop 314 is reset and the FSTP
11=FSTP21=FSTP31="0", FSTP1
0=FSTP20=FSTP30="1". As a result, the AND gate conditions of AND gates 317 ₁ to 317 ₃ all fail, and the AND OR
The output of inverter 317 becomes logic "1". Therefore, if signal FIOCT0 rises anew and flip-flop 316 is reset, ROM clock signal CRCLK1 by AND 318 is reset.
The output prohibition will be lifted.

All input/output bus control microinstructions for connecting input/output devices have been executed, and the signals are
When CLBSY0 becomes inactive (logic "1"), flip-flop 306 is set again at the timing of basic clock signal CRCK11. As a result, the signal FIOCT1 becomes active (logic "1"), and the input/output bus control circuit 221 starts controlling the input/output bus again. As a result, input/output operations for status reading and checking are performed in the same manner as in the case of device connection described above. In this case, unlike when the input/output device is connected, the output of the ROM clock signal CRCLK1 is prohibited by the flip-flop 316 (signal FSTP40 of logic "0"), and the next microinstruction is not fetched. Eventually, flip-flop 306 is reset, and when signal FIOCTO rises, flip-flop 316 is reset. This causes the signal FSTP40 to rise, and the next basic clock signal
From ANDGATE 318 in synchronization with CBCK11
ROM clock signal CRCLK1 is output. That is, since the next microinstruction is not fetched until the flip-flop 316 is reset and the operation of the input/output bus control circuit 221 is designated to end, there is no possibility that the input/output bus control microinstructions will be executed in parallel.

This means that when the input/output bus control circuit 221 is in an inactive state, an input/output bus control microinstruction with a stop instruction is sent to the ROM data register 219.
The same applies to the case where it is taken out. That is, at this point, the register 314 contains RD12.
1="1", CLBSY="0", and RLSQ11="0" are stored. As a result, FSTP11=FSTP20
= “1”. And input/output bus control circuit 2
21 starts operating (FIOCT1="1"), the AND condition of AND gate ₃₁₇₁ is satisfied, and the output of AND-OR inverter 317 becomes logic "0".
becomes. As a result, by AND gate 318
Output of ROM clock signal CRCLK1 is prohibited. Thereby, there is no fear that the next microinstruction will be fetched, and input/output bus control microinstructions will not be executed in parallel, causing malfunctions. Note that the inhibition of the output of the ROM clock signal CRCLK1 is canceled only when the signal
When FIOCT1 falls, the input/output bus control circuit 221
The point at which the end of the operation is specified (at this time,
AND gate 317 ₁ according to FIOCT1="0"
The AND condition is satisfied). As can be understood from the above, and or inverter 317
When the AND gate ₃₁₇₁ attempts to execute an input/output bus control microinstruction with a stop specification (FSTP11="1"), the input/output bus control circuit 221 is inactive (FSTP20="1"). This indicates the prohibition conditions when Further, AND gate ₃₁₇₂ and flip-flop 316 indicate a prohibition condition when flip-flop 306 is set (FIOCT0="0") when an attempt is made to execute an input/output bus control microinstruction specifying a stop. Also, and gate 31
7 ₃ is when an attempt is made to execute an input/output bus control microinstruction without a stop specification (FSTP10=
“1”) indicates a prohibition condition when the input/output bus control circuit 221 is in operation (FSTP21="1").

As described in detail above, according to the input/output control device of the present invention, the input/output bus control microinstructions and other microinstructions can be executed in parallel as necessary, so that processing efficiency can be significantly improved.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining a conventional data transfer procedure between a multiplexer channel and an input/output device.
FIG. 2 is a block diagram showing an embodiment of an information processing system related to the present invention, FIG. 3 is a block diagram showing the configuration of a multiplexer channel to which the present invention is applied in the above embodiment, and FIG. 4 is a block diagram showing the configuration of the multiplexer channel described above. FIG. 5 is a detailed circuit configuration diagram of the main part of the input/output bus control circuit in the channel, FIG. 5 is a format diagram of the input/output bus control microinstruction in the above embodiment, and FIG. 6 is a configuration example of the channel control block (CCB). Figure 7 is a format diagram of the start I/O (SIO) command, Figure 8 a,
b is a diagram showing the contents of the register indicated by the start I/O command, FIG. 9 is a diagram showing an example of the operating state between the channel and the input/output device, and FIG. 10 is a diagram explaining the operation directly related to the present invention. This is a timing chart for. 111...Central processing unit (CPU), 112...
Input/output bus, 113... Input/output device, 114...
Main memory, 116... multiplexer channel,
117...DMA bus, 209...internal bus A,
213...RAM, 218...ROM, 219...
...ROM data register, 220...Microcomputer, 221...I/O bus control circuit, 2
22...Internal bus control circuit, 234...Internal bus B, 229...Address register, 301, 31
4...Register, 304, 316...D-type flip-flop, 302...Decoder, 305, 30
7,315,318...and gate, 306...
...J-K flip-flop, 308...shift register, 317...and-or inverter.

Claims (1)

[Scope of Claims] 1. A control storage section in which a microprogram for controlling the inside of a channel is stored, and when an input/output bus control microinstruction is read from this control storage section, the microinstruction is taken in and the channel and input/output device are an input/output bus control circuit for controlling the connection between the two; a storage device for storing the channel control word read from the main memory under the control of a microprogram that executes a channel activation command; means for reading the contents of the channel control word from the device and setting it in a predetermined register to prepare for data transfer between the main memory and the channel; and means for determining whether or not to read a next microinstruction from the control storage section based on the state and specific bits of the input/output bus control microinstruction, and the control storage section is configured to read out the control storage section while the input/output bus control circuit is in operation. An input/output control device characterized in that data transfer preparation operations are processed in parallel by the data transfer preparation microinstructions from the data transfer preparation section. 2. If the input/output bus control circuit is in operation when the input/output bus control microinstruction is read, the input/output bus control microinstruction is not taken into the input/output bus control circuit. An input/output control device according to claim 1. 3. If the specific bit is set and the input/output bus control circuit is in operation, the determination means prohibits reading of the next microinstruction from the control storage section. The input/output control device according to scope 1.