JPS63187944A - Communication control equipment - Google Patents

Abstract

PURPOSE:To prevent danger of occurrence of a reception overrunning error and to shorten a reception interruption processing time by executing interruption processing by means of DMA write byte counters provided in correspondence with a line connection part in a communication processing part. CONSTITUTION:Data is transferred by DMA transfer at every character between the line connection part 3 of a pacing system or a synchronous system and the communication processing part 2, and the interruption request of reception data transfer is generated from the line connection part 3 to the communication processing part 2 at every character. A write byte counter 26 group for communication lines is provided in the line connection part 3 in correspondence with a DMA request from respective line connection parts 3, and the DMA write byte counters 26 execute the interruption processing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a communication control device comprising a communication processing section and a line connection section. In particular, the present invention relates to means for transferring received data between an asynchronous or synchronous line connection section and a communication processing section.

〔overview〕

The present invention provides a communication processing device equipped with a communication processing unit having a means for giving priority to a line connection unit that has received a reception end character and prohibiting a reception operation, in which data transfer between the line connection unit and the communication processing unit is performed. DMA transfer is performed for each character, and interrupt requests for reception data transfer are sent to the line connection unit for each character (generated in the 3 processing units, thereby reducing reception interrupt processing time and processing by the communication control device. This allows you to improve your abilities.

[Conventional technology]

In the start-stop and synchronous communication procedures, the data transmitted over the communication line is a character code, and generally the number of characters to be transmitted cannot be determined, so the communication control device on the receiving side does not recognize the received characters. The reception operation is ended when a character such as a block end character or the like for which the reception operation should be ended, that is, a reception end character is detected by analyzing each character.

Therefore, in a communication control device having a start-stop type or synchronous type line connection unit, for reception operation, the line connection unit normally generates an interrupt request to the communication processing unit every time it receives one character of data from the communication line, and When the microprocessor in the processing section accepts the interrupt request, the microprogram inputs the received data from the line connection section as an interrupt process, analyzes whether it is a reception end character, and if it is a reception end character. The receiving operation of the line connection section is stopped.

Generally, this method is called the microprogram transfer method.

In addition, as a method different from the microprogram transfer method, the line connection unit analyzes whether the received character is a reception end character, and the received data is transferred from the line connection unit to the communication processing unit using DMA (DMA) without going through the microprogram. There is also a method in which the data is transferred to the receive data buffer in the communication processing section using direct memory access), and when the line connection section detects the end of reception character, the reception operation is stopped and the communication processing section is notified of the end of reception by an interrupt. be. Generally, this method is called a DMA transfer method.

[Problem that the invention seeks to solve]

In this type of microprogram transfer method, data is received one after another from the communication line, so the number of receive buffer registers that store received characters in the line connection section is limited to one.
In this case, after the line connection unit generates an interrupt request due to character reception until the next character is received, the communication processing unit accepts the interrupt request and executes the interrupt processing routine of the microprogram. If you do not enter the received characters in , the received characters will be lost. This loss of received characters is generally called a reception overrun error. Therefore, in a communication control device using the microprogram transfer method, the processing capacity of the communication control device is determined by the time required for interrupt processing of the microprogram. For example, when the line speed of a communication line is 9600 bits/second, 1 bit is approximately 104n, and if one character on the communication line is 8 bits, a received character is received every 833 μs, so the microprogram is If the data interrupt processing time is 200 .mu.s, then four 9600 bit/second lines can be processed at the same time in terms of received data processing.

In addition, the interrupt processing time for received characters is generally long for special received characters such as the reception end character, and short for normal data characters, and because of this variation, the reception buffer register In order to prevent the occurrence of a reception overrun error in the case of one stage, the processing capacity of the communication control device depends on the longest interrupt processing time, and the processing time for normal data characters has almost no relation to the processing capacity.

On the other hand, if we make the receive buffer register in FIFO (first in first out) format and have multiple stages, we can solve the problem of communication system. The processing capacity of the III device is FI
The number of columns in the FO is determined by the average processing time for the number of received characters, which approaches the value based on the processing time for normal data characters, but it is still determined based on the interrupt processing time of the microprogram. do not have.

In this way, with the microprogram transfer method, by using a high-speed microprocessor, reducing the number of execution steps of the microprogram in the interrupt processing routine, and increasing the interrupt priority of received data, the processing capacity of the communication control device can be increased. However, these measures also have limitations and have the drawback that a communication control device with high processing capacity cannot be expected.

On the other hand, in the case of the DMA transfer method, since the microprocessor is not involved in the transfer of received characters, the processing capacity is dramatically improved compared to the microprogram transfer method. It is impractical to have a microprocessor in the system from the viewpoint of implementation space and cost, and most of the interrupt processing functions for received characters in the microprogram transfer method must be implemented in the hardware of the line connection section. First, it had the disadvantage that it was almost impossible to implement due to constraints such as mounting.

The present invention aims to eliminate such drawbacks and to provide a communication control device that can improve its own processing capacity.

゛ [Means for solving the problem] The present invention provides a method for connecting a plurality of line connection units that receive data including a reception end character indicating the end of data transfer, and one of the line connection units that received the reception end character. In the communication control device, the communication control unit includes a DMA write/byte counter corresponding to each line connection unit, and the communication control unit includes a DMA write/byte counter corresponding to each line connection unit. The communication processing unit includes means for updating the contents of the DMA write byte counter for each character of the received data and means for issuing a reception interrupt request. The present invention is characterized by comprising means for reading the contents of the DMA write byte counter and means for activating the control means when the read contents are a reception end character.

[Effect]

Conventionally, detection of a reception end character, which causes the end of a reception operation, has been performed using a microprogram transfer method or a DMA transfer method. In the microprogram transfer method, the data character processing time is determined by the length of the microprogram's interrupt processing time, and the DMA transfer method is not practical in terms of cost.

In the first invention, instead of interrupt processing by the microprocessor, DMA is used for the line connection section provided in the communication processing section.
Processing is performed using a write byte counter, which prevents the risk of reception overrun errors and reduces reception interrupt processing time.

〔Example〕

The figure is a block diagram showing an embodiment of the present invention. Next, the present invention will be explained with reference to the figures.

The communication control device 1 has an address bus 201 and a data bus 20.
The communication processing section 2 is composed of a communication processing section 2 and a line connection section 3, which are connected through a communication processing section 2 and a line connection section 3. The line connection unit 3 is an asynchronous or synchronous line connection unit, and although one line connection unit is shown in this embodiment, the address bus 201 and data bus 202 include a plurality of line connection units. can be connected. The communication processing unit 2 includes a microprocessor 2L memory 2
2. It is composed of a DMA control circuit 23, an interrupt control circuit 24, and one set of DMA write address counter 25 and DMA write byte counter 26 for each line connection unit. A part of the memory 22 is a program memory 22A.
and is used as a data buffer memory 22B.

The line connection section 3 includes a reception control circuit 31 and a transmission control circuit 32.
It consists of

Now, the microprocessor 21 is the program memory 22
A microprogram stored in A is executed to perform communication processing. Before causing the line connection unit 3 to perform a reception operation, the microprogram secures a reception data buffer in the data buffer memory 22B, and stores the start memory address in the DMA write address counter 25 corresponding to the line connection unit 3 and also stores the byte. After setting the number in the DMA write byte counter 26 and memorizing it, the operation of the reception control circuit 31 is permitted. The operation of the reception control circuit 31 is permitted or prohibited by the microprogram.

The reception control circuit 31 receives the serial reception data signal 301 from the communication line in an asynchronous or synchronous manner, assembles it into parallel reception characters, and sends it to the DMA control circuit via the reception DMA interface line 311 for each character reception δ. 23, and also issues an interrupt request to the interrupt control circuit 24 via the reception interrupt request signal 312. The DMA control circuit 23 determines the priority order between this DMA request and DMA requests from other line connections, and
When the A request is accepted, the received character is read from the reception control circuit 31 and written to the received data buffer in the data buffer memory 22B according to the contents of the DMA write address counter 25 using DMA, and the contents of the DMA write address counter 25 are written. is incremented by 1, and the contents of the DMA write/byte counter 26 are decremented by 1 to prepare for reception of the next character. The reception control circuit 31 uses DMA when a received character is read.
Reset the request. On the other hand, the interrupt control circuit 24 issues an interrupt to the microprocessor 21 based on the interrupt request by the received interrupt request signal 312. microprocessor 21
accepts the interrupt if it is in a state where the interrupt can be accepted, and if the interrupt request by the received interrupt request signal 312 has the highest priority among the line connections generating the interrupt request at that time. Then, the interrupt processing routine of the microprogram starts processing for the reception control circuit 31. The interrupt control circuit 24 prioritizes interrupt requests from each line connection section.

In the interrupt processing routine for the reception control circuit 31, the DMA
Input the value of the write/hide counter 26 and write 4g. For the first reception interrupt, the value set in the DMA write byte counter 26 before the start of the reception operation,
Also, from the second time onward, the difference between the value input manually last time and the value input this time is calculated to know the number of received characters to be processed for the current interrupt. The received character to be processed in this interrupt is DMA.
The transferred address on the reception buffer is the address set in the DMA write address counter 25 before starting the reception operation for the first interrupt, and from the second interrupt onward, the address on the reception buffer that has been transferred is the address set in the DMA write address counter 25 before the start of the reception operation, and from the second interrupt onward, the received address processed up to the previous time is used as the initial address. The address is the sum of the total number of characters. In this way, if the reception and processing of a microprogram receive interrupt is delayed by more than one character time on the communication line, there will be multiple errors between the microprogram's previous interrupt processing and the current interrupt processing. The received characters are transferred by DMA, but since the interrupt processing routine can know which received characters should be processed by the current interrupt, it is possible to sequentially read the received characters from the received data buffer and analyze them. When the end character is detected, the microprogram can stop the reception operation of the reception control circuit 31 including DMA transfer.

〔Effect of the invention〕

As explained above, the present invention transfers data between an asynchronous or synchronous line connection unit and a communication processing unit by DMA transfer character by character, and also transmits an interrupt request for transfer of received data to the line for each character. It is configured so that DM is generated from the connection part to the communication processing part, and the DM from each circuit connection part is generated in the line connection part.
Since there is a DMA write/byte counter group in the communication line in response to the A request, it is possible to almost eliminate the risk of reception overrun errors occurring during reception data transfer, and it is also possible to handle reception interrupt processing within the communication processing unit. Even if the priority is low, if you can process the received character that was finally transferred by DMA, you can detect the reception end character and stop the reception operation, and you can receive multiple receptions with one reception interrupt process. It is possible to process characters, thereby shortening the reception interrupt processing time, and as a result, there is an effect that the processing capacity of the communication control device can be greatly improved.

[Brief explanation of the drawing]

The figure is a block diagram showing an embodiment of the present invention. 1... Communication control device, 2... Communication processing unit, 3...
Line connection section, 21... Microprocessor, 22...
・Memory, 22A...Program memory, 22B...
・Data buffer memory, 23...DMA control circuit,
24... Interrupt control circuit, 25... DMA write/address counter, 26... DMA write/hide counter, 31... Reception control circuit, 32... Transmission control circuit, 201... Address Bus, 202...Data bus, 301...Serial reception data signal, 311...Reception DMA interface line, 312...Reception interrupt request signal.

Claims (1)

[Claims] (1) Priority is given to multiple line connections (3) that receive data including a reception end character indicating the end of data transfer, and one of the line connections that received the reception end character is prohibited from receiving data. A communication control device comprising a communication processing unit (2) having a control means, wherein the communication control unit includes a DMA write/byte counter (26) corresponding to each line connection unit, and the line connection unit includes: The communication processing unit includes means for updating the contents of the DMA write byte counter for each character of received data and means for issuing a reception interrupt request. - A communication control device comprising means for reading the contents of a byte counter and means for activating the control means when the read contents are a reception end character.