JPH0147020B2 - - Google Patents

Info

Publication number
JPH0147020B2
JPH0147020B2 JP56103454A JP10345481A JPH0147020B2 JP H0147020 B2 JPH0147020 B2 JP H0147020B2 JP 56103454 A JP56103454 A JP 56103454A JP 10345481 A JP10345481 A JP 10345481A JP H0147020 B2 JPH0147020 B2 JP H0147020B2
Authority
JP
Japan
Prior art keywords
layer
silicon dioxide
contact
substrate
polysilicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56103454A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5750441A (en
Inventor
Chaaruzu Dotsukaatei Robaato
Ruisu Gaabarino Hooru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS5750441A publication Critical patent/JPS5750441A/ja
Publication of JPH0147020B2 publication Critical patent/JPH0147020B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H10W20/069—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10P95/00—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/981—Utilizing varying dielectric thickness

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
JP56103454A 1980-08-29 1981-07-03 Method of forming electric contact Granted JPS5750441A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/182,722 US4409722A (en) 1980-08-29 1980-08-29 Borderless diffusion contact process and structure

Publications (2)

Publication Number Publication Date
JPS5750441A JPS5750441A (en) 1982-03-24
JPH0147020B2 true JPH0147020B2 (enExample) 1989-10-12

Family

ID=22669728

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56103454A Granted JPS5750441A (en) 1980-08-29 1981-07-03 Method of forming electric contact

Country Status (4)

Country Link
US (1) US4409722A (enExample)
EP (1) EP0046857B1 (enExample)
JP (1) JPS5750441A (enExample)
DE (1) DE3168886D1 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58209156A (ja) * 1982-05-31 1983-12-06 Nippon Telegr & Teleph Corp <Ntt> 半導体装置の製造方法
US4488348A (en) * 1983-06-15 1984-12-18 Hewlett-Packard Company Method for making a self-aligned vertically stacked gate MOS device
JP2503621B2 (ja) * 1989-01-23 1996-06-05 日本電気株式会社 半導体装置の製造方法
US5541427A (en) * 1993-12-03 1996-07-30 International Business Machines Corporation SRAM cell with capacitor
JP3396286B2 (ja) * 1994-02-28 2003-04-14 三菱電機株式会社 半導体集積回路装置およびその製造方法
US5641708A (en) * 1994-06-07 1997-06-24 Sgs-Thomson Microelectronics, Inc. Method for fabricating conductive structures in integrated circuits
JP2616706B2 (ja) * 1994-08-04 1997-06-04 日本電気株式会社 半導体装置およびその製造方法
US5960318A (en) * 1995-10-27 1999-09-28 Siemens Aktiengesellschaft Borderless contact etch process with sidewall spacer and selective isotropic etch process
US5792703A (en) * 1996-03-20 1998-08-11 International Business Machines Corporation Self-aligned contact wiring process for SI devices
US5804485A (en) * 1997-02-25 1998-09-08 Miracle Technology Co Ltd High density metal gate MOS fabrication process
US5970340A (en) * 1997-06-24 1999-10-19 Micron Technology, Inc. Method for making semiconductor device incorporating an electrical contact to an internal conductive layer
JP5339972B2 (ja) * 2009-03-10 2013-11-13 株式会社ジャパンディスプレイ 画像表示装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3387286A (en) * 1967-07-14 1968-06-04 Ibm Field-effect transistor memory
US3967981A (en) * 1971-01-14 1976-07-06 Shumpei Yamazaki Method for manufacturing a semiconductor field effort transistor
US4074304A (en) * 1974-10-04 1978-02-14 Nippon Electric Company, Ltd. Semiconductor device having a miniature junction area and process for fabricating same
JPS543480A (en) * 1977-06-09 1979-01-11 Fujitsu Ltd Manufacture of semiconductor device
US4160991A (en) * 1977-10-25 1979-07-10 International Business Machines Corporation High performance bipolar device and method for making same
US4251571A (en) * 1978-05-02 1981-02-17 International Business Machines Corporation Method for forming semiconductor structure with improved isolation between two layers of polycrystalline silicon
US4157269A (en) * 1978-06-06 1979-06-05 International Business Machines Corporation Utilizing polysilicon diffusion sources and special masking techniques
US4234362A (en) * 1978-11-03 1980-11-18 International Business Machines Corporation Method for forming an insulator between layers of conductive material
US4240196A (en) * 1978-12-29 1980-12-23 Bell Telephone Laboratories, Incorporated Fabrication of two-level polysilicon devices
CA1131796A (en) * 1979-01-08 1982-09-14 Tarsaim L. Batra Method for fabricating mos device with self-aligned contacts
JPS6055988B2 (ja) * 1979-01-26 1985-12-07 株式会社日立製作所 半導体装置の製法
JPS5650532A (en) * 1979-10-01 1981-05-07 Hitachi Ltd Manufacture of semiconductor device

Also Published As

Publication number Publication date
EP0046857A3 (en) 1982-09-08
US4409722A (en) 1983-10-18
EP0046857B1 (en) 1985-02-13
DE3168886D1 (en) 1985-03-28
EP0046857A2 (en) 1982-03-10
JPS5750441A (en) 1982-03-24

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