JPH0140500B2 - - Google Patents

Info

Publication number
JPH0140500B2
JPH0140500B2 JP12265981A JP12265981A JPH0140500B2 JP H0140500 B2 JPH0140500 B2 JP H0140500B2 JP 12265981 A JP12265981 A JP 12265981A JP 12265981 A JP12265981 A JP 12265981A JP H0140500 B2 JPH0140500 B2 JP H0140500B2
Authority
JP
Japan
Prior art keywords
insulating film
wiring
fuse
thickness
fuse part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP12265981A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5823475A (ja
Inventor
Nobuo Sasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56122659A priority Critical patent/JPS5823475A/ja
Publication of JPS5823475A publication Critical patent/JPS5823475A/ja
Publication of JPH0140500B2 publication Critical patent/JPH0140500B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H01L23/5258Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Read Only Memory (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
JP56122659A 1981-08-05 1981-08-05 半導体装置及び製造方法 Granted JPS5823475A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56122659A JPS5823475A (ja) 1981-08-05 1981-08-05 半導体装置及び製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56122659A JPS5823475A (ja) 1981-08-05 1981-08-05 半導体装置及び製造方法

Publications (2)

Publication Number Publication Date
JPS5823475A JPS5823475A (ja) 1983-02-12
JPH0140500B2 true JPH0140500B2 (enrdf_load_stackoverflow) 1989-08-29

Family

ID=14841447

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56122659A Granted JPS5823475A (ja) 1981-08-05 1981-08-05 半導体装置及び製造方法

Country Status (1)

Country Link
JP (1) JPS5823475A (enrdf_load_stackoverflow)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58115687A (ja) * 1981-12-28 1983-07-09 Fujitsu Ltd 読出し専用メモリ−の書込み方法
US4853758A (en) * 1987-08-12 1989-08-01 American Telephone And Telegraph Company, At&T Bell Laboratories Laser-blown links
US5070392A (en) * 1988-03-18 1991-12-03 Digital Equipment Corporation Integrated circuit having laser-alterable metallization layer
US5521116A (en) * 1995-04-24 1996-05-28 Texas Instruments Incorporated Sidewall formation process for a top lead fuse
US6372522B1 (en) 1999-10-05 2002-04-16 Vlsi Technology, Inc. Use of optimized film stacks for increasing absorption for laser repair of fuse links
US6306746B1 (en) 1999-12-30 2001-10-23 Koninklijke Philips Electronics Backend process for fuse link opening

Also Published As

Publication number Publication date
JPS5823475A (ja) 1983-02-12

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