JPH01321665A - Manufacture of resin sealed semiconductor device - Google Patents
Manufacture of resin sealed semiconductor deviceInfo
- Publication number
- JPH01321665A JPH01321665A JP15462388A JP15462388A JPH01321665A JP H01321665 A JPH01321665 A JP H01321665A JP 15462388 A JP15462388 A JP 15462388A JP 15462388 A JP15462388 A JP 15462388A JP H01321665 A JPH01321665 A JP H01321665A
- Authority
- JP
- Japan
- Prior art keywords
- dam
- leads
- sealing resin
- sealing
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000011347 resin Substances 0.000 title claims abstract description 39
- 229920005989 resin Polymers 0.000 title claims abstract description 39
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000000034 method Methods 0.000 claims abstract description 71
- 238000007789 sealing Methods 0.000 claims abstract description 33
- 238000004080 punching Methods 0.000 claims abstract description 6
- 239000002184 metal Substances 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 238000001721 transfer moulding Methods 0.000 abstract description 4
- 230000006835 compression Effects 0.000 abstract 1
- 238000007906 compression Methods 0.000 abstract 1
- 238000005520 cutting process Methods 0.000 description 4
- 238000003825 pressing Methods 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000368 destabilizing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
(産業上の利用分野)
本発明は、リードフレームにマウントした半導体素子を
含めて行う樹脂封止工程により発生するパリを防止する
技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a technique for preventing paris generated in a resin encapsulation process including a semiconductor element mounted on a lead frame.
(従来の技術)
半導体基板に回路やデバイスを造込んだ半導体素子の組
立工程には通常リードフレームを利用して組立て、更に
樹脂による封止工程により外部雰囲気から保護している
。ところでDIP、 SIP及び両者の混合型のリード
フレームの製造手段として知られている食刻工程とプレ
ス工程のうち現在では後者が専ら利用されており、集積
回路等のように集積度の大きい多ビン構造素子ではアウ
ターリード間のピッチを小さくせざるを得ないのが実状
である。(Prior Art) In the assembly process of semiconductor elements in which circuits and devices are built into a semiconductor substrate, a lead frame is usually used to assemble the semiconductor element, and the semiconductor element is further protected from the external atmosphere by a resin sealing process. By the way, among the etching process and pressing process, which are known as manufacturing methods for lead frames of DIP, SIP, and a combination of both, the latter is currently exclusively used, and is used for manufacturing highly integrated multi-bins such as integrated circuits. In reality, the pitch between outer leads of structural elements has to be reduced.
このような集積度の大きい半導体素子のマウントに主と
して利用するDIP用ならびに混合型リードフレームの
概要を説明すると1周囲を金ス製枠体で構成する複数の
単位体を連続して形成し、この数により長尺物か短尺物
に分類する。一方、金gt製枠体にはここを起点とする
リードを単位体の中心方向に向けて形成し、その中心付
近の一対のリード間にはベッド部を接続して半導体素子
を造込んだ半導体基板をマンウドできるようにする。An overview of DIP and mixed type lead frames, which are mainly used to mount semiconductor devices with a large degree of integration, is that a plurality of unit bodies each having a frame made of gold steel are successively formed. Depending on the number, they are classified as long or short. On the other hand, a lead starting from this point is formed in the gold GT frame toward the center of the unit, and a bed is connected between a pair of leads near the center to form a semiconductor element. Make it possible to manage the board.
この半導体基板に近い場所のリード端はフリー状態とし
て、更に、金R製枠体には透孔を単位体毎に形成して搬
送に役立たせると共に自動化に対応させている。The lead end near the semiconductor substrate is left in a free state, and a through hole is formed in each unit in the frame made of gold R to facilitate transportation and make it compatible with automation.
このようにベッド部とリード端子を備えたリードフレー
ムには、両部品の機械的強度を増すと共に樹脂封止工程
の土手として機能する連結細条即ちダムを形成するが、
その位置は枠体に比較的近いリードに交差する方向に延
長して形成する。In this way, the lead frame equipped with the bed portion and lead terminals is formed with connecting strips or dams that increase the mechanical strength of both components and function as banks in the resin sealing process.
The position thereof is formed so as to extend in a direction intersecting the lead relatively close to the frame.
そして半導体素子に形成した電極とリード間の電気的接
続を図る金属細線による熱圧着工程と樹脂封止工程に続
くカットムベンド工程によってダム付近を切断してマウ
ント部分とそれ以外に切離す。Then, a thermocompression bonding process using thin metal wires for electrical connection between electrodes and leads formed on the semiconductor element and a resin sealing process are followed by a cut-to-bend process to cut the dam area and separate the mount part from the rest.
この結果、はぼ直方体に形成した封止樹脂層の厚さ方向
即ち側部から所定の形状に成形されたリード即ちアウタ
ーリードを導出した集積回路が形成される。なおリード
フレームに形成するリードは半導体素子に形成した電極
とリード端子間の熱圧着工程前後によってインナーリー
ドからアウターリードに呼名が変更される。As a result, an integrated circuit is formed in which leads, that is, outer leads formed in a predetermined shape are led out from the thickness direction, that is, from the sides, of the sealing resin layer formed in the shape of a rectangular parallelepiped. Note that the name of the leads formed on the lead frame is changed from inner leads to outer leads depending on before and after the thermocompression bonding process between the electrodes formed on the semiconductor element and the lead terminals.
ところでトランスファモールド法を利用する樹脂封止工
程では、専用マシンに配置された一対の金型間にリード
フレームを配置し、更に金型に形成するカル及びランナ
ーを介してキャビティ内に溶融樹脂を導入し、更に所定
の温度下でエージング処理を行って完了とする。この結
果、前述のようにほぼ直方体に形成された封止樹脂M側
部からアウターリードが導出した半導体装置が製造され
る。By the way, in the resin sealing process using the transfer molding method, a lead frame is placed between a pair of molds placed in a special machine, and molten resin is introduced into the cavity through the cull and runner formed in the mold. Then, an aging treatment is performed at a predetermined temperature to complete the process. As a result, a semiconductor device is manufactured in which the outer leads are led out from the side portion of the sealing resin M, which is formed into a substantially rectangular parallelepiped shape as described above.
この半導体装置は電子機器等のキットに挿入して電気回
路を構成したり、半導体素子の検査工程に投入されるの
で接触不良やソケット詰まりを防止するために規格通り
に形成することが必要である。Since this semiconductor device is inserted into a kit for electronic equipment to form an electric circuit or used in the testing process of semiconductor elements, it is necessary to form it according to specifications to prevent poor connections and socket clogging. .
ところで、トランスファモールド法により成形され封止
樹脂層を備えた製品のアウターリードにはいわゆるパリ
が発生する頻度が大きく、対策として多くの提案が発表
されると共にその除去に鋭意努力が払われてきた。By the way, so-called pars often occur on the outer leads of products molded by the transfer molding method and equipped with a sealing resin layer, and many proposals have been announced as countermeasures and efforts have been made to eliminate them. .
前述のように樹脂封止工程に使用する一対の金型は精密
加工により製造するが微視的には隙間の存在が否定でき
ず、樹脂封止工程時には封止樹脂が流出するのが不可避
である。As mentioned above, the pair of molds used in the resin sealing process are manufactured through precision machining, but the existence of microscopic gaps cannot be denied, and it is inevitable that the sealing resin will flow out during the resin sealing process. be.
封止樹脂によるパリ、の発生を防止する方法について第
3図を参照して説明する。前述のように、直方体状に形
成した一対の金属部材の表面に沿って形成したカルから
分岐して金属部材の端部方向に向かうランナ部を設け、
更にその端末部にはゲート部につながった複数のキャビ
ティ部を設ける。A method for preventing the occurrence of paris due to the sealing resin will be described with reference to FIG. 3. As described above, a runner section is provided that branches from a cull formed along the surfaces of a pair of rectangular parallelepiped metal members and extends toward the ends of the metal members,
Further, a plurality of cavities connected to the gate portion are provided at the terminal portion.
第3図に示すように金属製枠体(図示せず)に設置する
リード端子21・・・にはその軸方向に交差するダム部
22を設けるが、樹脂封止工程により封止樹脂層23と
ダム部22にできる空隙24にも封止樹脂層23が充填
されることになる。As shown in FIG. 3, lead terminals 21 installed in a metal frame (not shown) are provided with dam portions 22 that intersect in the axial direction. The void 24 formed in the dam portion 22 is also filled with the sealing resin layer 23.
(発明が解決しようとする課題)
この空隙24に充填される封止樹脂層を除去しても一部
が残留していわゆる格子パリが発生する。(Problem to be Solved by the Invention) Even if the sealing resin layer filled in the void 24 is removed, a portion remains and so-called lattice cracks occur.
このためにリードピッチが大きい半導体素子用り 1
−ドフレームではa、コマをわざわざ設置する方法や、
b、この部分に対応する金型に凸状部を形成する方法、
更にC0このコマを化学的食刻工程により設置する手法
等が知られている。しかし、aならびにbの方法ではり
−ド21・・・どの間には50μm程度、 Cの方法で
はリードフレームの肉厚程度の隙間が形成されるのは避
けられないので、封止樹脂層が隙間に流れこんで格子パ
リが形成される。一方リードピッチが小さいリードフレ
ームではこのようなコマを形成したりする対策が取難い
。For this reason, it is used for semiconductor devices with a large lead pitch.
- In the de-frame, a, how to take the trouble to set up the pieces,
b. A method of forming a convex part on the mold corresponding to this part,
Furthermore, a method is known in which the C0 frame is installed using a chemical etching process. However, in methods a and b, it is unavoidable that a gap of about 50 μm is formed between the leads 21, and in method C, a gap of about the thickness of the lead frame is formed, so the sealing resin layer is It flows into the gaps and forms a grid. On the other hand, in a lead frame with a small lead pitch, it is difficult to take measures to prevent the formation of such frames.
いずれにしても格子パリの除去には高価なパリ取り機械
が入用になったり、あるいは多くの時間を費やしても完
全でなかった。このために、検査工程等で挿入に難点が
起きたり、後続のカットムベンド工程のプレス工程用精
密金型を破損する等の欠点があった。In any case, removing the lattice particles requires an expensive deburring machine, or takes a lot of time, but the process is not complete. For this reason, there are drawbacks such as difficulty in insertion during the inspection process, etc., and damage to the precision mold for the press process in the subsequent cut-and-bend process.
本発明は上記難点を除去する新規な樹脂封止型半導体装
置の製造方法を提供し、特に格子パリの発生を抑制する
ことを目的とするものである。The present invention provides a novel method for manufacturing a resin-sealed semiconductor device that eliminates the above-mentioned drawbacks, and particularly aims to suppress the occurrence of lattice flashes.
(課題を解決するための手段)
この目的を達成するのに本発明では、金属製の枠体から
延長して形成するリード端子に交差して設置するダム部
と封止樹脂層間のリードフレームを連続状態とし、この
リード、ダム部及び封止樹脂層により囲まれたリードフ
レーム部分をハーフパンチする手法を採用する。(Means for Solving the Problems) In order to achieve this object, the present invention uses a lead frame between a dam part and a sealing resin layer, which is installed to intersect with a lead terminal extending from a metal frame. A method is adopted in which the lead frame portion surrounded by the lead, the dam portion, and the sealing resin layer is half punched in a continuous state.
(作 用)
このように本発明に係わる樹脂封止型半導体装置の製造
方法に使用するリードフレームでは、前述の連続状態の
リードフレーム部分にはハーフパンチによりほぼ半分を
切断し残りの半分は連続状態とした平坦状態になってい
るので、ダム部と封止用樹脂間の隙間に充填されるのが
防止されてパリの発生が抑制されることになる。(Function) As described above, in the lead frame used in the method for manufacturing a resin-sealed semiconductor device according to the present invention, approximately half of the continuous lead frame portion is cut by a half punch, and the remaining half is continuous. Since it is in a flat state, the gap between the dam part and the sealing resin is prevented from being filled, and the occurrence of paris is suppressed.
このハーフパンチとは切断面が斜めに設置されたポンチ
を使用する工程であって、リードフレームの厚みの半分
程度は切断され、ポンチが接触しない残部はプレス工程
以前の状態のまま残すものである。この工程によりぶら
ぶらの状態となるが、全体は連続状態のリードフレーム
と同じく平坦な形状となるが、もし切断部分が遊離して
平坦とならない時には平坦な状態に修復してから切断工
程に移行する。This half-punch is a process that uses a punch with a diagonal cutting surface, which cuts about half the thickness of the lead frame, leaving the remaining part that the punch does not touch as it was before the pressing process. . This process leaves the lead frame in a dangling state, but the overall shape is flat like a continuous lead frame. However, if the cut part comes loose and is not flat, it is restored to a flat state before moving on to the cutting process. .
即ちこのプレス工程に続く金属細線による熱圧着工程、
樹脂封止工程等を終えてからダム部の切断工程即ちカッ
トムベンド工程により切断されてパリが殆どないアウタ
ーリードを備えた半導体装置が得られ、ソケットを詰ま
らせたりプレス工程用精密金型の破損等の難点が防止で
きる。That is, a thermocompression bonding process using thin metal wires following this pressing process,
After finishing the resin sealing process, etc., the dam part is cut by a cutting process, that is, a cut-to-bend process, and a semiconductor device with an outer lead with almost no paris is obtained, which may clog the socket or damage the precision mold for the press process. This problem can be avoided.
(実施例)
第1図a、b及び第2図を参照して本発明の詳細な説明
するが、従来技術側と重複する部品には同一番号を付け
る。第1図aは本発明方法を適用するリードフレームの
形状を示す斜視図、第1図すはその上面図であり、第2
図はこの方法により完成した半導体装置の上面図である
。(Example) The present invention will be described in detail with reference to FIGS. 1a and 1b and FIG. 2, and parts that overlap with those in the prior art are given the same numbers. FIG. 1a is a perspective view showing the shape of a lead frame to which the method of the present invention is applied, FIG. 1 is a top view thereof, and FIG.
The figure is a top view of a semiconductor device completed by this method.
第1図a、bに明らかにした本発明に使用するリードフ
レームは、多ビンの集積回路素子用のピッチが狭いDI
P用であって、その構造は従来技術側と同様なので詳細
な説明は省略する。即ち、金属製枠体(図示せず)に形
成したり−ドト・・には、その長手方向に交差して延長
するダム2を設置し、キャビティ内で封止される封止樹
脂層3の端部間は図のように連続状態とする。言いかえ
るとダム2と同じ厚さの板状としておく。The lead frame used in the present invention as shown in FIGS. 1a and b is a narrow pitch DI for multi-bin integrated circuit devices.
This is for P, and its structure is similar to that of the prior art, so a detailed explanation will be omitted. That is, in a metal frame (not shown), a dam 2 extending across the longitudinal direction of the metal frame (not shown) is installed, and a sealing resin layer 3 sealed in the cavity is installed. The end portions shall be continuous as shown in the figure. In other words, it is made into a plate with the same thickness as Dam 2.
そして予定される封止樹脂層3の端面4.これに対向す
るダム2部分更に隣接するリード1,1の側面5,5の
延長線ならびにダム2部分により区分された場所6にハ
ーフパンチ工程を行う。And the planned end face 4 of the sealing resin layer 3. A half-punching process is performed on the dam 2 portion facing this, and on the extension line of the side surfaces 5, 5 of the adjacent leads 1, 1, and on a location 6 divided by the dam 2 portion.
このハーフパンチ工程については作用欄で説明したが簡
単に触れると、図にあるように斜め方向の切断面を取付
けた図示しないポンチで区分された場所6を押圧してダ
ム2部分に隣接する場所を含めた半分程度を切断し残部
を連続状態即ち切断前の状態のままとする。このハーフ
パンチ工程を行った部分はぶらぶらの状態となり、もし
平坦になっていない時にはプレス機械を利用して修正す
る。This half-punching process was explained in the action column, but to briefly touch on it, as shown in the figure, a punch (not shown) with a diagonal cut surface is used to press the divided area 6 and place adjacent to the dam 2 part. Cut about half of the paper, including the remaining part, and leave the remaining part in a continuous state, that is, in the state before cutting. The part where this half-punch process was performed will be in a dangling state, and if it is not flat, it will be corrected using a press machine.
次にこのリードフレームに形成するベッド部(図示せず
)には所定の半導体集積回路素子を常法によりマウント
、熱圧着工程、更にトランスファモールド法により樹脂
封止工程を行って封止樹脂層3を形成し、更にハーフパ
ンチ工程を第1図a。Next, a predetermined semiconductor integrated circuit element is mounted on a bed portion (not shown) formed on this lead frame by a conventional method, and a thermocompression bonding process and a resin sealing process are performed using a transfer molding method to form a sealing resin layer 3. 1a.
bにあるように行う。Proceed as in b.
次に公知の二−ジング工程、カット&ベンド工程、外装
工程を経て第2図にあるような樹脂封止型半導体装置を
作製する。このような製造方法では樹脂封止工程中溶融
樹脂層がダム2部分に流出されないので5パリが殆どな
いアウターリードト・・が封止樹脂層から導出される。Next, a resin-sealed semiconductor device as shown in FIG. 2 is fabricated through a known destabilizing process, cut-and-bend process, and packaging process. In such a manufacturing method, the molten resin layer is not flowed out to the dam 2 portion during the resin sealing process, so that an outer lead with almost no 5 holes is drawn out from the sealing resin layer.
従ってソケットへの挿入は円滑にでき、更にプレス工程
では精密金型を損傷する恐れは全くない。Therefore, it can be smoothly inserted into the socket, and there is no risk of damaging the precision mold during the pressing process.
このように本発明方法では、格子パリが全く残らないの
で、従来行わざるを得なかったパリ取り工程が簡素化さ
れ、残った格子パリにもとずくトラブルが解消され、生
産性の向上がもたらされる。As described above, in the method of the present invention, since no lattice chips remain, the deburring process that had to be performed in the past is simplified, and troubles caused by the remaining lattice chips are eliminated, leading to improved productivity. It will be done.
第1図aは本発明に係わる本発明方法を適用するリード
フレームの形状を示す上面図、第1図bはその断面図、
第2図は本発明方法で完成した樹脂封止型半導体装置の
斜視図、第3図は従来方法を適用するリードフレームの
形状を示す上面図である。
代理人 弁理士 大 胡 典 夫
第1図
第 2111FIG. 1a is a top view showing the shape of a lead frame to which the method of the present invention is applied, FIG. 1b is a cross-sectional view thereof,
FIG. 2 is a perspective view of a resin-sealed semiconductor device completed using the method of the present invention, and FIG. 3 is a top view showing the shape of a lead frame to which the conventional method is applied. Agent Patent Attorney Norio Ogo Figure 1 2111
Claims (1)
に向けてリードを形成する工程と、このリードに交差す
るダム部を設置する工程と、この中心付近に位置するリ
ード間にベッド部を形成する工程と、このベット部に設
置する半導体素子を封止樹脂層で被覆する工程と、前記
ダム部と封止樹脂層間のリードフレームを連続状態とし
、リード、ダム部及び封止樹脂層により囲まれたリード
フレーム部分をハーフパンチする工程とを具備すること
を特徴とする樹脂封止型半導体装置の製造方法。A process of preparing a metal frame body, a process of forming a lead from this frame towards the center, a process of installing a dam part that intersects this lead, and a process of forming a bed between the leads located near the center. a process of forming a semiconductor element in the bed part, a process of covering the semiconductor element to be installed in the bed part with a sealing resin layer, and a process of forming a continuous state of the lead frame between the dam part and the sealing resin layer; 1. A method for manufacturing a resin-sealed semiconductor device, comprising the step of half-punching a lead frame portion surrounded by layers.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63154623A JP2714002B2 (en) | 1988-06-24 | 1988-06-24 | Method for manufacturing resin-encapsulated semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63154623A JP2714002B2 (en) | 1988-06-24 | 1988-06-24 | Method for manufacturing resin-encapsulated semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH01321665A true JPH01321665A (en) | 1989-12-27 |
JP2714002B2 JP2714002B2 (en) | 1998-02-16 |
Family
ID=15588230
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63154623A Expired - Fee Related JP2714002B2 (en) | 1988-06-24 | 1988-06-24 | Method for manufacturing resin-encapsulated semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2714002B2 (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62147358U (en) * | 1986-03-12 | 1987-09-17 |
-
1988
- 1988-06-24 JP JP63154623A patent/JP2714002B2/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62147358U (en) * | 1986-03-12 | 1987-09-17 |
Also Published As
Publication number | Publication date |
---|---|
JP2714002B2 (en) | 1998-02-16 |
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