JPH01300565A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make it hard for an impurity to pierce a gate electrode and restrain deterioration of switching speed by removing a mask for source-drain region formation and selectively forming a high melting point metallic layer so as to form the gate electrode. CONSTITUTION:Gate insulating films 2-6 and a mask 7 for source-drain region formation are formed on a substrate 1, and using the mask 7 impurity is introduced into the substrate so as to form a source region 8a and a drain region 8b, and then an interlayer insulating film 9 is so formed as to cover the mask 7. Next, the interlayer insulating film 9 is selectively etched so as to expose the mask 7, and with the interlayer insulating film 9 as a mask the mask 7 is removed to form an opening 11, and then a high melting point metallic layer 12 is selectively formed in the opening. Accordingly, the mask for forming source and drain regions can be formed fully thick, and the high melting point metallic layer formed inside the opening can used for a gate electrode. Hereby, it becomes possible to make it hard for the impurity to pierce the gate electrode, besides the deterioration of switching speed can be nearly restrained.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a semiconductor device, it is possible to make it difficult for impurities to punch out a gate electrode, and also to suppress deterioration of switching speed to a large extent, allowing for good device miniaturization. The purpose of the present invention is to provide a method for manufacturing a semiconductor device that can be manufactured by forming a gate insulating film and a mask for forming a source/drain region on a substrate, and using the mask for forming a source/drain region on the substrate. forming a source region and a drain region by introducing impurities;
forming an interlayer insulating film to cover the mask for forming the source/drain region; selectively etching the interlayer insulating film to expose the mask for forming the source/drain region; using an insulating film as a mask, removing the mask for forming the source/drain region to form an opening, and selectively forming a high melting point metal layer in the opening to form a gate electrode. It is configured to include.

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device that can effectively miniaturize elements.

In recent years, with the miniaturization of LSIs and the like, the number of transistors and the like integrated within a chip has been increasing, and there is a demand for making the transistors themselves smaller. For example, MOS
In an FET, the depth of the source/drain in the substrate direction must be made shallow, the gate electrode width (channel length) must be made small, and the gate electrode thickness, gate oxide film thickness, etc. must be made thin. Here, the reason why the depth of the source/drain in the substrate direction is made shallow is to alleviate the short channel effect, and this is because the depletion layer formed from the source side and the depletion layer formed from the drain side are connected. This is to alleviate the problem of putting things away. The reason for reducing the gate oxide film thickness is to improve the subthreshold characteristics.The reason for reducing the gate electrode thickness is to reduce the thickness of the gate electrode because if it is formed thickly, the steps will become large, so it is difficult to form the next layer, especially a wiring layer made of, for example, Al. This is to reduce the tendency for the wiring layer to become disconnected due to the step difference, and to flatten the wiring layer.

[Conventional technology]

Conventionally, polySt was used for the gate electrode.

A manufacturing method using poly-Si for the gate electrode will be described below.

FIGS. 2(a) to 2(c) are diagrams for explaining an example of a conventional method for manufacturing a semiconductor device. The illustrated manufacturing method can be applied to, for example, a silicon gate FET.

In these figures, 21 is a substrate made of, for example, St;
22 is a gate oxide film made of, for example, a silicon oxide film (eg, 5iO2), 23 is a polysilicon film, and 23a is a gate electrode, which is the portion remaining after the polysilicon film 23 has been selectively etched. 24a is a source region, and 24b is a drain region.

Next, the manufacturing process will be briefly explained.

First, as shown in FIG. 2(a), a gate oxide film 22 is formed on a substrate 21 by, for example, a thermal oxidation method, and then poly-Si is deposited on the gate oxide film 22 by, for example, a CVD method to form a polysilicon film. form 23.

At this time, the polysilicon film 23 is doped with impurities such as P.
(phosphorus) is doped.

Next, as shown in FIG. 2(b), the polysilicon film 23 and gate oxide film 22 are selectively etched by, for example, the RIE method. At this time, gate electrode 23a is formed.

Then, using the gate electrode 23a as a mask, impurities are selectively introduced into the substrate 21 as shown in FIG.
), a source region 24a and a drain region 24b as shown in FIG.
can be obtained self-consistently.

[Problem to be solved by the invention]

However, in the conventional manufacturing method of semiconductor devices, impurities are introduced (ion implantation) using the gate electrode 23a made of poly-Si as a mask, but as the miniaturization of devices progresses, source area 2
4a1 Not only does the drain region 24b become shallower, but also the gate electrode 23a becomes thinner, so when impurities are implanted, the impurities punch through the gate electrode 23a and reach the substrate 21, reducing the breakdown voltage of the gate oxide film 22. Specifically, for example, if the thickness of the gate electrode 23a is set to 1,000, and the thickness of the source region 24 is
a. If the depth of the drain region 24b in the direction of the substrate 21 is set to, for example, 1,000 to 1,500, and the impurity is introduced, the gate electrode 23a will be punched out and the impurity will reach the substrate 21, and the channels of the source 5Ibi 24a and the drain region 24b will be connected. It loses its function as a transistor and becomes a resistive element. Here, the reason for reducing the thickness of the gate electrode 23a is to alleviate the negative effects (broken wires, shape deterioration, etc.) on the wiring formed as the next layer due to the difference in level, and to flatten the source region. The purpose of making the drain regions 24a and 24b shallow is to alleviate the short channel effect.

Further, the thinning of the gate electrode 23a is achieved by reducing the thickness of the gate electrode 23a.
In addition to punching out ions, there was also the problem of decreasing the switching speed of the transistor due to the increase in resistance. One way to solve this problem of reducing the switching speed is to use a high melting point metal such as W, but this high melting point metal undergoes an indispensable annealing process (activation) after introducing impurities. In addition to defect recovery, this is necessary for functioning as a conductive layer.)
It has the disadvantage that it is difficult to use because it is sensitive to heat treatment (usually 800 to 1000°C) and easily deteriorates.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device that can make it difficult for impurities to punch out a gate electrode, can almost suppress deterioration of switching speed, and can favorably miniaturize elements. It is said that

[Means to solve the problem]

In order to achieve the above object, the method for manufacturing a semiconductor device according to the present invention includes a step of forming a gate insulating film and a mask for forming a source/drain region on a substrate, and a step of forming a mask for forming a gate insulating film and a source/drain region on the substrate. a step of forming a source region and a drain region by introducing impurities into the etching layer; a step of forming an interlayer insulating film to cover the mask for forming the source/drain region; and a step of selectively etching the interlayer insulating film. exposing the mask for forming the source/drain region using the interlayer insulating film as a mask, removing the mask for forming the source/drain region to form an opening, and forming an opening in the opening. The method includes a step of selectively forming a high melting point metal layer to form a gate electrode.

[Effect]

In the present invention, a mask for forming a gate insulating film and a source/drain region is formed on a substrate, a mask for forming a source/drain region is used, and a source region and a drain region are formed by introducing impurities into the substrate. After that, a glabellar insulating film is formed to cover the mask for forming the source/drain regions. Next, the mask for forming the source/drain regions was exposed by selective etching of the glabellar insulating film, the glabellar insulating film was used as a mask, and the mask for forming the source/drain regions was removed to form openings. Thereafter, a gate electrode is formed by selectively forming a high melting point metal layer within the opening.

Therefore, since the mask for forming the source/drain region can be formed sufficiently thick in advance, it is possible to prevent the impurity from penetrating the mask for forming the source/drain region when introducing the impurity, and to selectively fill the opening. Since the formed high melting point metal layer can be used for the gate electrode, it becomes possible to prevent an increase in wiring resistance due to thinning of the electrode.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

FIGS. 1(a) to 1(m) are diagrams illustrating an embodiment of a method for manufacturing a semiconductor device according to the present invention. The illustrated example manufacturing method is applied to a MOS FET.

In these figures, 1 is a substrate made of Si, for example.
This corresponds to the substrate according to the present invention. 2 is a silicon oxide film made of, for example, Sin, 3 is a silicon nitride film made of, for example, 5iiN, 4 is a channel stopper, and 5 is made of, for example, Si.
A field oxide film made of O□, and 6 a gate oxide film made of, for example, Sin, correspond to the gate insulating film according to the present invention.

Reference numeral 7 denotes a temporary electrode made of, for example, polySt, which corresponds to a mask for forming source/drain regions according to the present invention. 8a is a source region, which corresponds to the source region according to the present invention. 8
b is a drain region, which corresponds to the drain region according to the present invention. 9.9a is an interlayer insulating film made of, for example, SiO, and the glabellar insulating film 9 corresponds to the glabellar insulating film according to the present invention. 10.10a is a resist, and 11 is an opening, which corresponds to the opening according to the present invention. 12 is a high melting point metal layer made of W, for example, and corresponds to the high melting point metal layer according to the present invention. 1
2a is a gate electrode, which corresponds to the gate electrode according to the present invention. 13 is a contact hole, 14a is a source electrode, 1
4b is a drain electrode.

Next, the manufacturing process will be explained.

First, as shown in FIG. 1(a), a silicon oxide film 2 having a thickness of, for example, 200 to 300 layers is formed on a substrate 1 by, for example, a thermal oxidation method. 5t3N4 is deposited to a film thickness of, for example, 100 mm.
A silicon nitride film 3 of 0 to 1500 layers is formed.

Next, as shown in FIG. 1(b), after selectively etching (patterning) the silicon nitride film 3 by, for example, RIE, impurities are introduced to form a channel stopper 4 using the silicon nitride film 3 as a mask. Form. The impurity is, for example, B' when the substrate 1 is of the p-type, and is, for example, P' when the substrate 1 is of the n-type.

Next, as shown in FIG. 1C, a field oxide film 5 is formed by field oxidation using the silicon nitride film 3 as a mask.
form.

Next, as shown in FIG. 1(d), after the silicon oxide film 2 and silicon nitride film 3 are selectively etched by, for example, RIE, impurities for VTN control are introduced into the substrate 1.

Next, as shown in FIG. 1(e), a gate oxide film 6 having a thickness of, for example, 150 mm is formed by, for example, a thermal oxidation method, and poly-Si is deposited to a thickness of, for example, 4000 mm by, for example, a CVD method. After that, the temporary electrode 7 is formed by selectively etching the poly-Si by, for example, RIE method. This corresponds to the step of forming a mask for forming a gate insulating film and source/drain regions on a substrate according to the present invention. Etching during the formation of the temporary electrode 7 is performed after the temporary electrode 7 is doped with P (phosphorus) in advance by, for example, an ion implantation method (or a vapor phase doping method) to facilitate processing of the temporary electrode 7. be exposed. The temporary electrode 7 is appropriately formed in advance to be sufficiently thick so as not to penetrate through impurity introduction (ion implantation) in the next step.

Then, after introducing impurities using the temporary electrode 7 as a mask,
Annealed source region 8as drain region 8
form b.

Annealing treatment is usually performed at about 800 to 900°C. This is achieved by introducing impurities into the substrate using a source/drain region mask according to the present invention.
This corresponds to the step of forming a drain region.

Next, as shown in FIG. 1(f), an interlayer insulating film 9 is formed by depositing SiO to cover the temporary electrode 7 by, for example, the CVD method. A resist 10 is formed on the interlayer insulating film 9 as shown in FIG.

Next, as shown in FIG. 1(h), the interlayer insulating film 9 is selectively etched back by, for example, RIE to expose the surface of the temporary electrode 7. For etching at this time, register l
An etchant is used such that the etching rate ratio of -10 to the interlayer insulating film 9 is, for example, 1:1. This corresponds to the step of selectively etching the interlayer insulating film to expose the mask for forming the source/drain regions of the present invention.

Next, as shown in FIG. 1(i), the temporary electrode 7 is selectively etched, for example, by wet etching to form an opening 11. This corresponds to the step of the present invention in which the interlayer insulating film is used as a mask and the mask for forming source/drain regions is removed to form an opening.

Next, as shown in FIG. 1(j), a high melting point metal layer 12 is formed by depositing W so as to cover the opening 11 by, for example, a spuck method, and then a resist 10 is deposited on the high melting point metal layer 12.
form a.

Next, as shown in FIG. 1(k), the interlayer insulating film 9 is selectively etched back by, for example, the RIE method to form the gate electrode 12a. For etching, the etching rate ratio of the resist 10a and the high melting point metal layer 12 is, for example, 1:1.
An etchant is used that gives Figure 1 (j)
1(k) corresponds to the step of the present invention in which a high melting point metal layer is selectively formed within the opening to form a gate electrode.

Next, as shown in FIG. 1N'), 5iOz is deposited on the entire surface so as to cover the gate electrode 12a by, for example, the CVD method to form a glabellar insulating film 9a having a thickness of, for example, 6000.

After forming the contact hole 13, a source electrode 14a and a drain electrode 14b are formed to make contact with the source region 8a and drain region 8b, respectively, thereby obtaining a semiconductor device having a structure as shown in FIG. 1(m). is completed.

That is, in the above embodiment, the temporary electrode 7 is used as a mask for forming the source/drain regions, and after the source region 8a and the drain region 8b are formed by introducing impurities into the substrate 1, the temporary electrode 7 is removed. A high melting point metal layer 12 is selectively formed in the formed opening 11 to form a gate electrode 12.
Since the formation of the transistor a makes it possible to prevent impurities from penetrating when introducing impurities, it is possible to prevent an increase in wiring resistance due to thinning of the electrode film, and to suppress deterioration of the switching speed of the transistor. Specifically, the impurity penetration can be prevented because the temporary electrode 7 can be appropriately formed in advance to be sufficiently thick to prevent impurities from penetrating. The reason why the resistance of the wiring can be prevented from increasing due to thinning of the electrode is that the high melting point metal N12 can be used for the gate electrode 12a.

〔effect〕

According to the present invention, it is possible to make it difficult for impurities to hit the gate electrode, and the deterioration of switching speed can be almost suppressed, so that element miniaturization can be carried out favorably.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining an embodiment of a method for manufacturing a semiconductor device according to the present invention, and FIG. 2 is a diagram for explaining an example of a conventional method for manufacturing a semiconductor device. 1...Substrate, 2...Silicon oxide film, 3...Silicon nitride film, 4...Channel stopper, 5...Field oxidation Film, 6...Gate oxide film, 7...Temporary electrode, 8a...Source region, 8b...Drain region, 9.9a... ...Interlayer insulating film, 10.10a...Resist, 11...Opening, 12...High melting point metal layer, 12a...Gate electrode, 13 ...Contact hole, 14a...Source electrode, 14b...Drain electrode. Figure 1-, IL score-Example 1 Pure manufacturing process proof explanation diagram 1 Figure 1 Isa example of the Tai Liao craftsman group Figure 1-L#-Example Explanation, Figure 1 of Meiben, An example of an unpublished example of a story about a daughter who was killed, Figure 2 of Meiben.

Claims (1)

[Scope of Claims] A step of forming a gate insulating film and a mask for forming a source/drain region on a substrate, and using the mask for forming the source/drain region, introducing an impurity into the substrate to form a source region. , a step of forming a drain region; a step of forming an interlayer insulating film to cover the mask for forming the source/drain region; and a step of selectively etching the interlayer insulating film to form the source/drain region.
a step of exposing a mask for forming a drain region; a step of using the interlayer insulating film as a mask and removing the mask for forming the source/drain region to form an opening; and forming a high melting point metal layer in the opening. A method for manufacturing a semiconductor device, comprising the step of selectively forming a gate electrode.