JPH01292859A - Method of driving charge transfer device - Google Patents

Abstract

PURPOSE:To prevent advanced feed of signal output by providing a means to change a gate clock of the preceding stage of the final gate clock from a high level to a low level after the final gate clock attains to the high level at the time when a clock applied to the final gate changes from the low level to the high level. CONSTITUTION:At a time (t1A), a clock phi1L is at a low level and a clock phi2 is at a high level, and therefore signal charge Q is stored under a transfer electrode which is provided to a clock phi1. At a time (t2A), the clock phi1L becomes the high level and the clock phi2 begins to change from the high level to the low level. Under the condition, signal charge Q begins to flow out from a potential well under the transfer electrode which is provided with the clock phi2. However, since the clock phi1L has been already the high level, and the potential well for signal charge storage is securely formed under the transfer electrode which is provided with the clock phi1L. The signal charge beginning to flow out from under the transfer electrode which is provided with the clock phi2 is entirely stored under a final gate 11 and advanced feed mode of signal charge DELTAQ is not thereby generated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a charge transfer device, and more particularly to a method for driving a charge transfer device in which the final gate is wired separately for high-speed driving.

[Conventional technology]

Some conventional charge transfer devices have the final gate wired separately for high-speed operation (for example, Japanese Patent Laid-Open No. 58-10
3172). This is because the clock change speed of the final gate is increased in order to increase the speed at which signal charges flow into the floating junction section of the pressure converter.

A conventional technique of this type of charge transfer device is shown in FIG. The structure of the conventional device has an N-type layer 2 on a P-type silicon substrate 1, as shown in FIG. 7(a-). The N-type layer 2 of the charge transfer section has a P-type barrier region 7, and a pair of transfer electrodes 8 on the N-type layer 2 and barrier region 7 are provided on the surface thereof. are doing. A clock φ and a clock φ2 having an opposite phase are alternately applied to one set of transfer electrodes 8. An output portion is formed at the right end portion of the N-type layer 2, and this output portion includes an N-type floating junction portion 12 and a reset drain N-type layer 3, and a reset pulse φ is applied to the upper part between these. A given reset gate 4 is formed.

An output V is output from the floating junction section 12 via an output buffer 5. . , has been taken out. A fixed potential VRD, which is, for example, a ground potential, is applied to the reset drain N-type layer 3. A fixed potential V is applied immediately before the floating junction section 12. . An output gate 6 is provided, which is provided with a final gate 11. The final gate 11 receives a clock φ that is the same as the clock φ1 but is output separately from the clock φ1.
1L is provided through a different wiring from the clock φ1.

Since the clock φ1L is applied only to the final gate 11, the waveform is a steep pulse without rounding, and high-speed output is possible.

[Problem to be solved by the invention]

However, the conventional structure in which the clock φ1L to the final gate 11 is wired in columns has a drawback that a normal output waveform cannot be obtained depending on the driving conditions. The contents will be explained below using FIGS. 7(b) to (d) and FIG. 8.

FIGS. 7(b) to (d) show times tl, t2. FIG. 8 is a diagram showing the potential distribution under the transfer electrode 8 and at the output section at t3, and FIG. Reset pulse φ, and output V. It is a timing chart of UT.

At the current time t1, the clock φ1L is at a low level,
Since the clock φ2 is at a high level, signal charges are accumulated under the transfer electrode to which the clock φ1 is applied. The floating junction part 12 has a charge Q just before it.
1 has been accumulated.

At time t2, when the clock φ2 is at a low level and the clock φ1L is at an intermediate level, the signal charge Q is transferred from the potential well under the transfer electrode to which the clock φ2 is applied, as shown in FIG. 3(C). However, since the clock φ1L is still at an intermediate level, a potential well for storing signal charges has not yet been formed under the transfer electrode to which the clock φ1L is applied. Therefore, the clock φ2 and the signal charge Q that has started to flow out from under the applied transfer electrode pass under the final gate 11 and flow into the floating junction section 12. This inflow produces an output signal V in the form of the sum of the previous signal potential Ql and a portion ΔQ of the charge Q to be read.

, J, r, and the output signal V as shown in FIG. . A increases from time t2, resulting in an abnormal waveform.

In such a state where the signal charge ΔQ is shifted ahead, the output signal is added one bit earlier, and the output signal does not exhibit a normal output waveform, and its output level is also unreliable.

Therefore, in the conventional separate line structure for the clock φ1L applied to the final gate, special consideration must be taken to prevent signal charge light from occurring, and the drive circuit becomes complicated.

[Means to solve the problem]

In the charge transfer of the present invention, the relationship between the clock applied to the final transfer gate and the clock applied to the gate one step before is determined by applying the clock applied to the final gate at the time when the clock applied to the final gate changes from a low level to a high level. The device is provided with means for changing from a high level to a low level the clock applied to the gate one stage before the clock applied to the gate after the clock applied to the gate reaches the high level.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1(a) is a cross-sectional view of the vicinity of the output part of the charge transfer used in one embodiment of the present invention, and FIG. 2 is a sectional view of the reset pulse φ8. 3 is a timing chart of clock φIL+φ2 and output Vour. Further, FIGS. 1(b) to 1(d) are diagrams showing the potentials of the charge transfer section and the output section in the charge transfer device at each time tIAp i 2Asi 3A in FIG. 2. The cross-sectional structure of the charge transfer device shown in FIG. 1(a) is the same as that of the charge transfer device shown in FIG. 7(a) described above, so a description thereof will be omitted.

Next, the operation will be explained using FIGS. 1(b) to (d) and FIG. 2. At the current time tlA, the clock φ1L
is at a low level and the clock φ2 is at a high level, so the signal charge Q is accumulated under the transfer electrode applied to the clock φ1. At time t2A, the clock φ1L goes high and the clock φ2 begins to change from high level to low level. In this state, as shown in FIG. 1(C), the signal charge Q begins to flow out from the potential well under the transfer electrode to which the clock φ2 is applied.

Since the clock φ1L is already at high level, the clock φ1
A potential well for accumulating signal charges is reliably formed under the transfer electrode to which clock φ2 is applied, and the signal charges that begin to flow out from under the transfer electrode to which clock φ2 is applied are all accumulated under the final gate 11. , a mode in which the signal charge ΔQ is placed first, which occurs in the prior art, does not occur.

FIG. 3 shows clocks φ1, 2φ2 . . . having a timing relationship according to the present invention. FIG. 2 is a circuit diagram showing an example of a parallel circuit that generates clocks φ1. The clock φ1L is obtained from the inverter 21 in the previous stage of the driver, which is composed of transistors 24, 25 and 26°27 which output the MOS transistor φ2. By doing this, as can be seen from the timing chart in FIG.
．． Signal delay of 23 T211 T221 T23 and Mo
After the clock φ1L completely rises due to the delay Tn of the buffer circuit composed of S transistors 24.25 and 26.27 (time T1), the clock φ2 starts falling.

Next, another embodiment of the present invention will be described using FIGS. 5 and 6.

A charge transfer section and an output section are provided in the N-type layer 52 on the surface of the P-type silicon substrate 510.

The charge transfer section has a P-type barrier region 57, and a pair of transfer electrodes 58 and 59 are provided on the P-type barrier region 57 and the N-type layer 52.

The transfer electrode 59 is provided with a clock φ1, and the transfer electrode 58 is provided with a clock φ2 having an opposite phase. The last of the transfer electrodes is connected to a fixed potential v as an output gate 56.
0° is given. The immediately preceding set of transfer electrodes is formed by an inverter 31 from which the clock φ1L is derived from the clock φ2 as the final gate 61, and is provided through separate wiring from the other transfer electrodes.

A clock φ2 is applied to a set of transfer electrodes 30 immediately before the final gate 61 via inverters 31 to 34, and a clock φ2L
As such, it is also provided with separate wiring from other transfer electrodes. The output section has an N-type floating junction section 62, a reset drain N-type layer 53, and an upper reset gate 54 between them. A fixed potential v3 is applied to the reset drain N-type layer 53, and a reset pulse φ8 is applied to the reset gate 54. An output V is output from the floating junction section 62 via the buffer 55. IJT has been taken out.

In this way, the inverter 31,
32, 33, and 34 are used to generate a clock φ1L+φ2L, which is applied to the final gate 61 immediately before the output gate 56 and a set of transfer electrodes 30 one stage before the final gate 61. These clocks φ2L are connected to inverters 32, 3
3.34 and is a clock delayed from clock φ1L.

By delaying the clock φ2L in this way, the sixth
As you can see from the timing diagram in the figure, this is also the final gate 6.
After the clock φ1L applied to the gate 1 completely rises (time T1), the clock φ2L applied to the set of transfer electrodes 30 in the previous stage of the final gate 61 starts falling. Therefore, it has the same effect as the embodiment described in FIGS. 1 to 4.

〔Effect of the invention〕

As explained above, the present invention provides a charge transfer device including:
At the time when the clock applied to the final gate changes from low level to high level, the clock of the gate one step before it changes from high level to low level after the time when the final gate clock reaches high level. This has the effect of preventing early signal output. Incidentally, the present invention relates to a channel type C embedded in a P type substrate.
The explanation was given using OD as an example, but if the conductivity type is reversed,
It goes without saying that this process can also be carried out on an N-type substrate by reversing the positive and negative voltages. Also, embedded channel type COD
It is obvious that the present invention can also be implemented not only in a surface channel type COD.

[Brief explanation of the drawing]

FIG. 1(a) is a sectional view of a charge transfer device used in an embodiment of the present invention, and FIGS. 1(b) to (d) are potential distributions at each time in the charge transfer section and output section. It is a diagram. FIG. 2 is a timing diagram for explaining the operation of FIG. 1. FIG. 3 is a circuit diagram of a clock generation circuit used in one embodiment of the present invention. FIG. 4 is a waveform diagram showing signals of various parts of the clock generation circuit of FIG. 3. FIG. 5 is a sectional view showing another embodiment of the present invention, and FIG. 6 is a waveform diagram showing its clock timing. Figure 7 is a cross-sectional view of a conventional charge transfer device, Figure 7(b) -
(d) is a potential diagram showing the potential distribution at each time in the charge transfer section and the output section, and FIG. 8 is a timing diagram explaining the operation. 1.51... Semiconductor substrate, 2,52...
・N-type layer, 3.53...Reset drain N-type layer, 4,54...Reset gate, 5,55...
...Output buffer, 6,56...Output gate, 7,57...P-type barrier layer, 8,5
8.59...Transfer electrode, 11.61...
・Final gate, 21, 22, 23° 31. 32, 33.
34...Inverter, 24°25.26.27
...MOS) transistor, 30...transfer electrode agent in front of the final gate Patent attorney Hakama 6th & 7th Hakama 8th

Claims (1)

[Claims] In a charge transfer device formed on at least a semiconductor substrate, a clock applied to a first transfer gate immediately before the output gate of the charge transfer device and a second transfer gate one stage before the first transfer gate, At the time when the clock applied to the first transfer gate changes from low level to high level, after the time when the clock applied to the first transfer gate completes the change to high level, the second A method for driving a charge transfer device, characterized in that a clock applied to a transfer gate of the charge transfer device changes from a high level to a low level.