JP2890409B2 - Charge transfer device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge transfer device, and more particularly, to a method for driving a charge transfer device in which a final gate is separately formed for high-speed driving.

[Conventional technology]

In a conventional charge transfer device, there is a device in which the final gate is provided with a separate wiring for high-speed driving (for example, Japanese Patent Application Laid-Open No.
72). This is to increase the clock change speed of the final gate in order to increase the speed of the signal charge flowing into the floating junction of the output charge-to-voltage converter.

FIG. 7 shows a prior art of this type of charge transfer device. The structure of the conventional device has an N-type layer 2 on a P-type silicon substrate 1 as shown in FIG. The N-type layer 2 of the charge transfer section has a P-type barrier (barrier) region 7, and a surface thereof has a pair of transfer electrodes 8 on the N-type layer 2 and the barrier region 7. doing. A clock φ and a clock φ ₂ having an opposite phase to the clock φ are alternately applied to one set of transfer electrodes 8. The right end portion of the N-type layer 2 output portion is formed, the output unit and the floating junction portion 12 and the reset drain N-type layer 3 of N-type is formed, the reset pulse phi _R to the top between them A given reset gate 4 is formed. The output _VOUT is extracted from the floating junction section 12 via the output buffer 5. The reset drain N-type layer 3 are given a fixed potential V _RD is, for example, ground potential. An output gate 6 to which a fixed potential _VOG is applied is provided immediately before the floating junction section 12, and a final gate 11 is provided before the output gate 6. The final gate 11 has a clock φ ₁
Phi _1L those output separately from the ₁ is the clock phi is the same clock are given in a different wiring from the clock phi ₁ and. Since the clock φ _1L is given only to the final gate 11, the waveform is a sharp pulse without rounding,
High-speed output is possible.

[Problems to be solved by the invention]

However, the conventional structure in which the clock _φ1L is separately wired to the final gate 11 has a drawback that a normal output waveform cannot be obtained depending on driving conditions. Hereinafter, the contents will be described with reference to FIGS. 7 (b) to (d) and FIG.

Figure 7 (b) ~ (d) is a diagram showing the potential distribution of the transfer electrodes 8 below and the output portion of the at time _{t 1, t 2, t 3} , FIG. 8 is a clock phi _1L, phi ₂ , the reset pulse φ _R
6 is a timing chart of an output _VOUT .

In now time t _1, the clock phi _1L signal charge Q for low level, the clock phi ₂ is high are accumulated under the transfer electrodes given clock phi _1. The floating junction section 12 charges to Q ₁ immediately before is accumulated. Time t ₂ next clock phi ₂ becomes the low level, in a state where the clock phi _1L is in the middle level, from the potential well under the transfer electrodes given clock phi ₂ as shown in FIG. 3 (c) Although the signal charges Q have begun to flow out, since the clock φ _1L is still at the intermediate level, a potential well for storing signal charges has not yet been formed below the transfer electrode _{supplied with} the clock φ _1L . Therefore, the signal charge Q that has begun to flow out from under the transfer electrode given the clock φ ₂ passes under the final gate 11 and flows into the floating junction 12. This inflow is caused by adding the signal potential Q ₁ one bit before and the part ΔQ of the charge Q to be read out to the output signal V _OUT
Output signal V _OUT as shown in FIG.
There was an increase from time t _2, an abnormal waveform.

As described above, in the state where the advance of the signal charge ΔQ has occurred, the output signal is added one bit before,
It does not show a normal output waveform and its output level is also unreliable.

Therefore, in another wiring structure of the clock phi _1L given to conventional final gate, gift signal charge destination requires special consideration, such as not to cause the drive circuit has been a complicated.

[Means for solving the problem]

In the charge transfer according to the present invention, the relationship between the clock applied to the final transfer gate and the clock applied to the immediately preceding gate is applied to the final gate when the clock applied to the final gate changes from a low level to a high level. There is provided a means for changing the clock applied to the immediately preceding gate from the high level to the low level after the clock to be output has reached the high level.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1A is a cross-sectional view of the vicinity of an output section of charge transfer used in an embodiment of the present invention, and FIG. 2 is a timing chart of the reset pulse φ _R , clocks φ _1L and φ ₂ and output V _OUT . It is. FIGS. 1B to 1D are diagrams showing the potentials of the charge transfer unit and the output unit in the charge transfer device at each of the times t _1A , t _2A , and t _3A in FIG. The cross-sectional structure of the charge transfer device shown in FIG. 1A is the same as that of the charge transfer device of FIG. 7A described above, and a description thereof will be omitted. Next, the operation will be described with reference to FIGS.
This will be described with reference to the drawings. Now, at time t _1A , since the clock φ _1L is at the low level and the clock φ ₂ is at the high level, the signal charge Q is accumulated under the transfer electrode given to the clock φ ₁ . Next time t _2A, a state of the clock phi ₂ becomes the clock phi _1L is a high level is started to change from a high level to a low level. Has a first view (c) the clock phi ₂ of the signal charges Q from the potential well under the transfer electrodes provided as shown in the beginning to flow out clock phi _1L already high level in this state, the clock phi A potential well for storing signal charges is surely formed under the given transfer electrode of _{1 L} , and all signal charges that have begun to flow out from under the given transfer electrode of clock φ ₂ are accumulated under the final gate 11. Therefore, the advance mode of the signal charge ΔQ as in the prior art does not occur.

FIG. 3 is a circuit diagram showing another example of generating clocks φ ₁ , 2φ ₂ , φ _1L having a timing relationship according to the present invention. MOS transistors 24, 25 outputting clocks φ ₁ , φ ₂ are shown in FIG. And a clock _φ1L is obtained from the inverter 21 at the stage just before the driver composed of 26 and 27. By doing so, as can be seen from the timing chart of FIG. 4, the signal delays T ₂₁ , T ₂₂ ,
T ₂₃ and MOS transistors 24, 25 and the clock phi _1L from completely risen by the delay T _D of the buffer circuit consisting of 26 and 27 (time T ₁₎ fall of the clock phi ₂ is started.

Next, another embodiment of the present invention will be described with reference to FIGS.

The N-type layer 52 on the surface of the P-type silicon substrate 51 has a charge transfer section and an output section. P in the charge transfer section
It has a type barrier region 57, and a pair of transfer electrodes 58 and 59 is provided on the P type barrier region 57 and the N type layer 52. A clock φ ₁ is applied to the transfer electrode 59 and a transfer electrode 58
Is supplied with a clock φ ₂ having a phase opposite to that of the clock φ ₂ .
The last of the transfer electrodes is fixed potential V as output gate 56
_OG is given. In the set of transfer electrodes immediately before that, a clock φ _1L is formed as the final gate 61 by the inverter 31 from the clock φ _2, and is provided by a separate wiring from the other transfer electrodes. The clock φ ₂ is supplied to the set of transfer electrodes 30 immediately before the final gate 61 via the inverters 31 to 34 as the clock φ _2L , also on a separate line from the other transfer electrodes. N-type floating junction at output
62, a reset drain N-type layer 53, and a reset gate 54 above them. Reset drain N-type layer
Fixed potential V _RD to 53, also to the reset gate 54 is given a reset pulse phi _R. An output _VOUT is extracted from the floating junction 62 via a buffer 55.

Inverter than this way, the external input clock φ ₂ 31,3
The clocks φ _1L and φ _2L are generated using 2, 33, and 34, and the final gate 61 immediately before the output gate 56 and the final gate 61
Is provided to a set of transfer electrodes 30 one stage before. These clocks phi _2L has a clock that is delayed from the clock phi _1L using an inverter 32, 33 and 34.

By delaying the clock φ _{2L in} this manner, the sixth
As can be seen from the timing diagram, this is also the final gate 61
After the clock φ _1L to be applied to the first gate 61 completely rises (time T ₁ ), the falling of the clock φ _2L applied to the set of transfer electrodes 30 in the preceding stage of the final gate 61 starts. Therefore, the first to first
4 has the same effect as the embodiment described with reference to FIG.

〔The invention's effect〕

As described above, according to the present invention, in the charge transfer device, at the time when the clock applied to the final gate changes from the low level to the high level, after the final gate clock has reached the high level, Providing the means for changing the gate clock from the high level to the low level has the effect of preventing the advance of the signal output. Although the present invention has been described with reference to a buried channel type CCD of a P-type substrate as an example, it goes without saying that the present invention can be applied to an N-type substrate if the conductivity type is reversed and the polarity of the voltage is reversed. Recessed channel type CC
It is clear that not only D but also a surface channel CCD can be used.

[Brief description of the drawings]

FIG. 1A is a sectional view of a charge transfer device used in an embodiment of the present invention, and FIGS. 1B to 1D show potential distributions of the charge transfer unit and the output unit at each time. FIG. FIG. 2 is a timing chart for explaining the operation of FIG. FIG. 3 is a circuit diagram of a clock generation circuit used in one embodiment of the present invention. FIG. 4 is a waveform diagram showing signals of various parts of the clock generation circuit of FIG. FIG. 5 is a sectional view showing another embodiment of the present invention, and FIG. 6 is a waveform diagram showing the clock timing. FIG. 7 is a sectional view of a conventional charge transfer device, and FIGS.
(D) is a potential diagram showing the potential distribution of the charge transfer section and the output section at each time, and FIG. 8 is a timing chart for explaining the operation. 1,51 ... Semiconductor substrate, 2,52 ... N-type layer, 3,53 ... Reset drain N-type layer, 4,54 ... Reset gate, 5,55 ...
Output buffer, 6,56 Output gate, 7,57 P-type barrier layer, 8,58,59 Transfer electrode, 11,61 Final gate, 21,22,23,31,32,33 , 34 …… Inverter, 24,25,26,2
7 ... MOS transistor, 30 ... Transfer electrode in front of final gate

Claims (1)

(57) [Claims] 1. A charge transfer device in which a plurality of transfer gates are arranged in a charge transfer direction, and adjacent transfer gates among the transfer gates are applied with clocks that change complementarily, respectively. The first transfer gate immediately before the output gate of the charge transfer device and the second transfer gate immediately before the first transfer gate are connected to a low level of a clock applied to the first transfer gate. A charge transfer device wherein a clock applied to the second transfer gate changes from a high level to a low level after the change to a high level is completed.