JPH0723299A - Driving pulse generation circuit - Google Patents

Abstract

PURPOSE:To reduce chip area, to make low power consumption and to improve the characteristic (output transition time) of the waveform of the output signal of a driving pulse to be generated. CONSTITUTION:This circuit is composed by forming a first N-MOS transistor Tr 1 and a second N-MOS transistor Tr 2 where a source terminal b is made common, connecting an input terminal phi in which a reference clock Pc is inputted with the gate electrode of the first N-MOS transistor Tr 1 via the input side node a and the CMOS inverter 1 on the rear stage and connecting the input terminal with the gate electrode of the second N-MOS transistor Tr 2 via an input side node (a). A load 2 is connected with the rear stage of the source terminal b which is common to these first and second N-MOS transistors Tr 1 and Tr 2. The drain terminal of the first N-MOS transistor Tr 1 is grounded and power source voltage VL of a low level is impressed on the drain terminal of the second N-MOS transistor Tr 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive pulse generating circuit, and more particularly to a signal pulse accumulated in each light receiving portion of a solid-state image pickup device having an image pickup area in which a large number of light receiving portions are arrayed, and the signal charge is vertically applied in units of rows. The present invention relates to a drive pulse generation circuit suitable for use in a circuit that generates a vertical transfer pulse or a read pulse applied to a vertical transfer unit that transfers in the direction.

[0002]

2. Description of the Related Art Generally, in a CCD solid-state image pickup device, for example, a field read-out type CCD solid-state image pickup device in which a vertical register is driven by four phases, an image is taken by taking an interline transfer (IT) type structure as an example. A large number of light receiving units that convert the light incident on the region into an amount of electric charge according to the amount of light are arranged in a matrix, and a large number of vertical registers that are common to the light receiving units arranged in the column direction are provided. Each electrode is extended to the horizontal register side, and has a structure in which a large number of electrode groups each having four vertical transfer electrodes as one set are arranged along the vertical register, and transferred from each light receiving unit to the corresponding vertical register. By applying four-phase vertical transfer pulses having mutually different phases to the respective vertical transfer electrodes, the signal charges can be transferred row by row along the vertical registers to the horizontal register side. It is configured.

The four-phase vertical transfer pulses applied to the vertical transfer electrodes are composed of two kinds of pulse signals having binary signal levels and two kinds of pulse signals having ternary signal levels. Supplied from the vertical driver circuit.

When the four vertical transfer electrodes arrayed and formed on the vertical register are defined as first, second, third and fourth vertical transfer electrodes toward the horizontal register side, respectively, The signal charge from the light receiving portion is read out under the first and third vertical transfer electrodes. Then, the signal charges read under the first and third vertical transfer electrodes are mixed in, for example, a transfer process on the vertical register and sequentially transferred to the horizontal register side.

Therefore, the vertical transfer pulse has a binary signal level waveform having an intermediate level and a low level necessary for transferring the signal charge, and a high level signal level necessary for reading from the light receiving section to the vertical register. Separately from the ternary pulse signal having a waveform and the ternary pulse signal,
The pulse signal is composed of only a binary signal level waveform having an intermediate level and a low level necessary for transferring signal charges.

In the above example, the ternary pulse signal is the first pulse signal.
And corresponding to the first and third vertical transfer pulses P ₁ and P ₃ applied to the third vertical transfer electrode, and the binary pulse signal is applied to the second and fourth vertical transfer electrodes. Second
And the fourth vertical transfer pulses P ₂ and P ₄ .

A drive pulse generating circuit for generating the first vertical transfer pulse P ₁ and the second vertical transfer pulse P ₂ will be typically described below.

First, as shown in FIG. 12, the binary driver circuit for generating the second vertical transfer pulse P ₂ is transferred via the input side node a to the subsequent stage of the input terminal φin to which the reference clock Pc is input. A gate G is connected and a load (in this case, a CCD solid-state image sensor) 101 is connected to the subsequent stage of the transfer gate G via an output-side node b.

The transfer gate G is an N-channel type MO having a common drain terminal and source terminal.
It is composed of an S transistor (hereinafter simply referred to as N-MOS transistor) Tn1 and a P-channel MOS transistor (hereinafter simply referred to as P-MOS transistor) Tp1. The common drain terminal of the transfer gate G is grounded, and the common source terminal is connected to the output side node b. The input side node a is connected to the gate electrode of the P-MOS transistor Tp1, and the input side node a is connected to the gate electrode of the N-MOS transistor Tn1 by the CMOS inverter 102.
Connected through.

In this binary driver circuit, an N-MOS transistor Tn2 whose source is an output side node b is connected, and an input side node a is connected to a drain of a gate electrode of the N-MOS transistor Tn2. A low level power supply voltage _VL (= -10V) is applied to the terminals. In addition, P- in the transfer gate G
The substrate bias potential of the MOS transistor Tp1 is a high level potential V _H (= + 15V), and the substrate bias potentials of the N-MOS transistors Tn1 and Tn2 are a low level potential V _L (= -10V).

The signal processing of this binary driver circuit is shown in FIG.
The timing chart will be described. Input terminal φ
in, 2 of high level potential is 5V and low level potential is 0V
When the reference clock Pc, which is a pulse signal of a value, is input, when the reference clock Pc is at a high level, the transfer
At the same time that the gate G turns off, the N-MOS transistor Tn2 turns on, and when the reference clock Pc is at a low level, the transfer gate G turns on and at the same time the N-MOS transistor Tn2 turns off. Is a binary pulse signal P having a ground level potential Vs during the high level period of the reference clock Pc and a low level potential V _L during the low level period of the reference clock Pc.
o, that is, in the above example, the second vertical transfer pulse P ₂ is applied.

Next, the ternary driver circuit for generating the _first vertical transfer pulse P ₁ has the transfer gate G and the N-MOS transistor Tn2 as in the above binary driver circuit, but the output side node b Source and a high level power supply voltage V _H is applied to the drain terminal of PM
The point that the OS transistor Tp2 is connected and this P
-The first, second and third reference clocks Pc1, Pc2 and Pc3 which are out of phase with each other are input to the gate electrodes of the MOS transistor Tp2, the transfer gate G and the gate electrode of the N-MOS transistor Tn2, respectively. And φ3. Each reference clock Pc1, Pc2 and Pc3
Shows a binary pulse signal waveform in which the high level potential is 5V and the low level potential is 0V. The substrate bias potential of the P-MOS transistor Tp2 is the high level potential V
_{It is H.}

The signal processing of this ternary driver circuit is shown in FIG.
The timing chart will be described. First, the first, second and third reference clocks Pc1, Pc2 and Pc
During the period when each of c3 is at the high level potential, P
-MOS transistor Tp2 is off operation, transfer gate G is off operation, N-MOS transistor Tn2
Is turned on, the output potential is low level potential V _L.
Becomes Next, in a period in which the first reference clock Pc1 is at a high level potential and the second and third reference clocks Pc2 and Pc3 are at a low level potential, respectively, the P-MOS
Since the transistor Tp2 is turned off, the transfer gate G is turned on, and the N-MOS transistor Tn2 is turned off, the output potential becomes the ground level potential Vs. Next, the first reference clock Pc1 is a low level potential,
In the period in which the second reference clock Pc2 has a high level potential and the third reference clock Pc3 has a low level potential,
The P-MOS transistor Tp2 is turned on, the transfer gate G is turned off, and the N-MOS transistor Tn is turned on.
2 is turned off, the output potential is the high level potential V
It becomes _H. Therefore, the ternary pulse signal Po, that is, the first vertical transfer pulse P _{1 in} the above example is applied to the load 101.

[0014]

However, in the conventional binary driver circuit and ternary driver circuit, the P-MOS transistor Tp1 and the N-MOS are used as a switching circuit for selectively outputting the ground level potential Vs.
Since the transfer gate G composed of two MOS transistors of the transistor Tn1 is used, there is a problem that the occupied area for forming the transfer gate G on the silicon substrate becomes large.

In particular, in order to increase the driving power of each driver circuit, it is necessary to increase the size of each transistor. In this case, it is necessary to increase the occupied area for forming the transfer gate G. There are problems that the chip area and the power consumption are increased, the manufacturing cost is increased, and the electronic device equipped with the CCD solid-state imaging device is increased in size.

Therefore, in the conventional binary driver circuit and ternary driver circuit, high density formation of pixels in the CCD solid-state image pickup device of recent years, high speed by the frame / interline transfer system, electronic equipment equipped with the CCD solid-state image pickup device There is an inconvenience that it is not possible to cope with miniaturization of

Further, the above-mentioned conventional binary driver circuit and 3
In the value driver circuit, since the rising time and the falling time of each vertical transfer pulse that is an output signal are delayed, unnecessary mixing (interference) of signal charges occurs in the process of transferring the signal charges as shown below. There is an inconvenience that it will occur.

That is, for example, as shown in FIG.
By applying the _first to fourth vertical transfer pulses P _{1 to} P ₄ having different phases to the fourth vertical transfer electrodes TG1 to TG4, the signal charge e is transferred to the horizontal register side along the vertical register. Consider the case.

First and fourth vertical transfer pulses P ₁ and P
₄ is the low level potential V _L , and the second and third vertical transfer pulses P ₂ and P ₃ are at the ground level potential Vs at time t ₁ , continuous under the second and third vertical transfer electrodes TG2 and TG3. From the state where the signal charge e is accumulated in the formed potential well, the second vertical transfer pulse P _{2 is set} to the low level potential V _L and the fourth vertical transfer pulse P ₄ is grounded as shown at time t _3. By setting the level potential Vs,
Looking at the process of transferring one stage of the vertical transfer electrode to the horizontal register side, since the falling time of the _second transfer pulse P _{2 and} the rising time of the fourth transfer pulse P ₄ are delayed,
The depth of the potential well under the second and fourth vertical transfer electrodes TG2 and TG4 at t ₂ in the transfer process becomes shallow, and therefore the signal charge e accumulated in the potential well overflows, As a result, there arises a problem that the signal charges e are unnecessarily mixed between the potential wells adjacent to each other. This unnecessary mixing of the signal charges e appears as interference when viewed as a reproduced image, and significantly deteriorates the image quality.

The present invention has been made in view of the above problems, and an object of the present invention is to generate a drive pulse capable of reducing the chip area and power consumption. To provide a circuit.

Another object of the present invention is to provide a drive pulse generation circuit capable of improving the characteristics (output transition time) of the output signal waveform of the generated drive pulse.

Another object of the present invention is to vertically transfer the signal charges accumulated in each light receiving portion of a solid-state image pickup device having an image pickup area in which a plurality of light receiving portions are arranged in a vertical direction in units of rows. When applied to a drive pulse generation circuit that generates a vertical transfer pulse and a read pulse applied to the transfer unit, the vertical transfer charge amount in the vertical transfer unit can be improved, and the quality of a reproduced image deteriorates (so-called It is an object of the present invention to provide a drive pulse generation circuit capable of suppressing V sag and smear.

Another object of the present invention, when applied to a drive pulse generation circuit for generating a vertical transfer pulse and a read pulse of the solid-state image pickup device, is to reduce the IC of an electronic device equipped with this solid-state image pickup device. It is an object of the present invention to provide a drive pulse generation circuit that can reduce power consumption and size, and can achieve size and weight reduction of the electronic device.

[0024]

A drive pulse generating circuit according to the present invention receives a timing signal Pc having a binary signal level and performs an ON operation when the timing signal Pc has one value. , A first switching circuit that selectively outputs a first signal level waveform Vs that forms a drive pulse, and the timing signal Pc are input, and the ON operation is performed when the timing signal Pc has the other value. And the second signal level waveform V that constitutes the drive pulse
_A second switching circuit that selectively outputs _L is included in the configuration, and the first and second switching circuits are each configured by a single N-channel type MIS transistor Tr1 and Tr2.

Further, in the drive pulse generating circuit according to the present invention, as the timing signal Pc, first, second and third timing signals Pc1, Pc2 and Pc3 which are independently supplied and have different phases from each other are provided. In addition to the first and second switching circuits Tr1 and Tr2,
A third switching circuit is provided, which is selectively turned on based on the input of the third timing signal Pc1 and selectively outputs the third signal level waveform V _H forming the drive pulse. The first switching circuit Tr1 is configured to selectively output the first signal level waveform Vs based on the input of the first timing signal Pc2, and the second switching circuit Tr1.
2 selectively outputs the second signal level waveform V _L based on the input of the second timing signal Pc3, and the third switching circuit is a single P
The channel type MIS transistor Tr3 is used.

In the drive pulse generating circuit according to the present invention, the first switching circuit Tr1 or the second switching circuit
The inverting circuit 3 may be connected before the switching circuit Tr2.

When the drive pulse generation circuit according to the present invention is applied to a solid-state image pickup device having an image pickup area in which a large number of light receiving portions are arranged, a drive pulse output from the drive pulse generation circuit, In particular, a drive pulse composed of the first signal level waveform Vs and the second signal level waveform _VL is applied to the vertical transfer unit that vertically transfers the signal charges accumulated in each light receiving unit row by row. Vertical transfer pulse.

Further, when the drive pulse generation circuit according to the present invention is applied to a solid-state image pickup device having an image pickup area in which a large number of light receiving portions are arranged, a drive pulse output from the drive pulse generation circuit, That is, of the first to third signal level waveforms, the first and second signal level waveforms Vs
And V _L can be vertical transfer pulses applied to the vertical transfer unit that transfers the signal charges accumulated in each light receiving unit in the vertical direction row by row, and the third signal level waveform V _H can be _expressed as
It can be used as a read pulse for transferring the signal charge accumulated in each light receiving section to the vertical transfer section.

[0029]

In the drive pulse generation circuit according to the present invention,
First, the timing signal Pc having a binary signal level is input to the first switching circuit Tr1 and the second switching circuit Tr2. Then, when the signal level of the timing signal Pc is one value, the first switching circuit Tr1 is turned on, and the first switching circuit Tr1 outputs the first signal level waveform Vs.

On the other hand, when the signal level of the timing signal Pc is the other value, the second switching circuit Tr2 is turned on this time, and the second signal level waveform V is output from the second switching circuit Tr2. _L is output.

That is, the first signal level waveform Vs and the second signal level waveform Vs corresponding to the signal level of the input timing signal Pc.
The signal level waveform V _{L of} is output selectively, resulting in 2
A drive pulse of value will be generated.

In particular, in the case of the present invention, since both the first and second switching circuits Tr1 and Tr2 are each composed of a single N-channel type MIS transistor, they are different from the conventional one using a transfer gate. Also,
The occupied area required for forming the element can be reduced.

That is, the transfer gate is composed of a P-channel type MIS transistor and an N-channel type MIS transistor. In the present invention, the area occupied by the P-channel type MIS transistor which is a constituent member of the transfer gate is occupied. To the deleted part,
By forming the N-channel type MIS transistor, the area of the N-channel type MIS transistor can be doubled.

In this case, in general, the occupied area Ap of the P-channel type MIS transistor is larger than the occupied area An of the N-channel type MIS transistor, so that the N-channel type MIS is obtained.
Even if the transistor size is doubled, the transfer
It is smaller than the gate formation area. Therefore, the entire chip area can be reduced and low power consumption can be achieved.

Further, the first and second switching circuits T
Since each of r1 and Tr2 is composed of a single N-channel MIS transistor, it is possible to improve the characteristics (output transition time) of the output signal waveform of the generated drive pulse.

Therefore, in the drive pulse generating circuit according to the present invention, the signal charges accumulated in each of the light receiving portions of the solid-state image pickup device having the image pickup area in which a large number of light receiving portions are arranged are vertically transferred in units of rows. When applied to a drive pulse generation circuit that generates a vertical transfer pulse applied to the vertical transfer unit, it is possible to reduce the power consumption and the size of the IC of an electronic device equipped with the solid-state image sensor, The size and weight of the device can be reduced. Further, the amount of vertical transfer charges in the vertical transfer unit can be improved, and deterioration of the image quality of a reproduced image (so-called V sag, smear, etc.) can be suppressed.

Next, in the drive pulse generating circuit according to the present invention, the timing signal Pc is the first, second and third timing signals Pc1, Pc2 and Pc3 which are independently supplied and have mutually different phases, In addition to the first and second switching circuits Tr1 and Tr2,
A third switching circuit Tr3 is provided, which is selectively turned on based on the input of the third timing signal Pc1 and selectively outputs the third signal level waveform V _H forming the drive pulse. In this case, first, the first, second and third timing signals Pc2, Pc3 having binary signal levels respectively in the first switching circuit Tr1, the second switching circuit Tr2 and the third switching circuit Tr3. , And Pc1 are input respectively.

Then, the first switching circuit Tr1 is turned on based on the input of the first timing signal Pc2, and the first switching circuit Tr1 outputs the first switching signal.
The signal level waveform Vs of is output. The second switching circuit Tr2 is turned on based on the input of the second timing signal Pc3, and the second switching circuit Tr2 outputs the second signal level waveform V _L. Further, the third switching circuit Tr3 is selectively turned on based on the input of the third timing signal Pc1, and the third signal level waveform V _H is output.

That is, the first signal level waveform Vs, the second signal level waveform V _L , and the third signal level waveform corresponding to the inputs of the first, second, and third timing signals Pc2, Pc3, and Pc1. V _H is selectively output, and as a result, a ternary drive pulse is generated.

In this case as well, similarly, the first and second switching circuits Tr1 and Tr2 are both independent N
Since it is composed of channel type MIS transistors,
Compared to the conventional one using a transfer gate, the area required for forming the element can be reduced, the chip area can be reduced, and the characteristics of the output signal waveform of the generated drive pulse (Output transition time) can be improved.

Therefore, the drive pulse generation circuit according to the present invention is applied to a solid-state image pickup device having an image pickup area in which a large number of light receiving portions are arranged, and the first and second signal level waveforms are applied to the respective light receiving portions. The signal charge accumulated in each light receiving unit is used as a vertical transfer pulse and a read pulse applied to the vertical transfer unit that vertically transfers the signal charge accumulated in each light receiving unit in a row unit. When used as a read pulse for transferring to the vertical transfer unit, it is possible to reduce the power consumption and the size of the IC of the electronic device equipped with the solid-state imaging device, and achieve the size and weight reduction of the electronic device. Can be made. Further, the amount of vertical transfer charges in the vertical transfer unit can be improved, and deterioration of the image quality of a reproduced image (so-called V sag, smear, etc.) can be suppressed.

[0042]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A drive pulse generation circuit according to the present invention will be described below.
An embodiment applied to a drive pulse generation circuit for generating a vertical transfer pulse in an image sensor of an interline transfer system using a CCD solid-state image sensor (hereinafter,
(Hereinafter simply referred to as a drive pulse generation circuit according to the embodiment) is shown in FIG.
This will be described with reference to FIG.

The CCD solid-state image pickup device to which the drive pulse generation circuit according to this embodiment is applied is, for example, a CCD solid-state image pickup device of the field reading type in which the vertical register is driven by four phases, for example, the interline transfer (IT) type. Taking the structure as an example, a large number of light receiving sections that convert the light incident on the imaging area into electric charges of an amount corresponding to the light quantity are arranged in a matrix, and are common to the light receiving sections arranged in the column direction. A plurality of vertical registers formed on the side of the horizontal register, and a plurality of electrode groups each including four vertical transfer electrodes as a set are arranged along the vertical register.
The signal charges transferred from the respective light receiving parts to the corresponding vertical registers are respectively transferred to the respective vertical transfer electrodes by different phases.
By applying a vertical transfer pulse of a phase, it is configured to transfer in a row unit along the vertical register to the horizontal register side.

The four-phase vertical transfer pulses applied to the vertical transfer electrodes are composed of two kinds of pulse signals having binary signal levels and two kinds of pulse signals having ternary signal levels. Supplied from the vertical driver circuit.

When the four vertical transfer electrodes arrayed and formed on the vertical register are defined as the first, second, third and fourth vertical transfer electrodes toward the horizontal register side, respectively, The signal charge from the light receiving portion is read out under the first and third vertical transfer electrodes. Then, the signal charges read under the first and third vertical transfer electrodes are mixed in, for example, a transfer process on the vertical register and sequentially transferred to the horizontal register side.

Therefore, the vertical transfer pulse is a binary signal level waveform having an intermediate level and a low level required to transfer the signal charge and a high level signal level waveform required to read from the light receiving section to the vertical register. Having 3
A pulse signal having a binary value and a pulse signal having only a binary signal level waveform having an intermediate level and a low level necessary for transferring signal charges, separately from the ternary pulse signal. Become.

In the above example, the ternary pulse signal is the first pulse signal.
And corresponding to the first and third vertical transfer pulses P ₁ and P ₃ applied to the third vertical transfer electrode, and the binary pulse signal is applied to the second and fourth vertical transfer electrodes. Second
And the fourth vertical transfer pulses P ₂ and P ₄ .

Typically, the drive pulse generation circuit according to the present embodiment for generating the first vertical transfer pulse P ₁ and the second vertical transfer pulse P ₂ , that is, the three-value driver circuit and the two-value driver circuit are used. This will be described below.

First, as shown in FIG. 1, the binary driver circuit for generating the second vertical transfer pulse P ₂ has two N-channel MOS transistors (first N- MOS transistor Tr1 and second N
-An input terminal φin having a MOS transistor Tr2) and to which the reference clock Pc from the previous stage is input is connected to the gate electrode of the first N-MOS transistor Tr1 via the input node a in the subsequent stage and the CMOS inverter 1. And the second N-MO via the input side node a.
It is configured to be connected to the gate electrode of the S transistor Tr2. Then, a load (in this case, a CCD solid-state image pickup device) 2 is provided at the subsequent stage of the common source terminal b of the first and second N-MOS transistors Tr1 and Tr2.
Are connected.

The first N-MOS transistor Tr1
Has its drain terminal grounded and the substrate bias potential set to the high level potential V _H (= + 15 V). Second
The low-level power supply voltage _VL (= -10V) is applied to the drain terminal of the N-MOS transistor Tr2 of
The substrate bias potential is set to the low level potential _VL (= -10V).

The signal processing of the binary driver circuit according to the above embodiment will be described with reference to the waveform diagram by simulation shown in FIG. High level potential is 5 at input terminal φin
When the reference clock Pc, which is a binary pulse signal of V and a low level potential of 0V, is input, when the reference clock Pc is at a high level, the first N-MOS transistor Tr1 is turned off and at the same time the second N-MOS transistor Tr1 is turned off. -MOS transistor Tr
2 is turned on and the first N-MOS transistor Tr1 is turned on at the same time when the reference clock Pc is at a low level, the second N-MOS transistor Tr2 is turned off at the same time. A binary pulse signal P in which Pc is the low level potential V _L during the high level period and the reference clock Pc is the ground level potential Vs during the low level period.
o, that is, in the above example, the second vertical transfer pulse P ₂ is applied.

As described above, in the binary driver circuit according to the present embodiment, the circuit for selectively outputting the ground level waveform of the _second vertical transfer pulse P ₂ is the first NM alone.
Since the circuit configured by the OS transistor Tr1 and selectively outputting the low-level waveform of the _second vertical transfer pulse P2 is configured by the single second N-MOS transistor Tr2, The area required for forming the element can be reduced as compared with the conventional one using the transfer gate as a circuit for selectively outputting the ground level waveform of the vertical transfer pulse P ₂ of FIG.

That is, the transfer gate is P-
Since it is composed of a MOS transistor and an N-MOS transistor, for example, as shown in FIG.
If the occupied areas for forming the MOS transistor and the N-MOS transistor are Ap and An, respectively,
The occupied area for forming the transfer gate is Ap
It becomes + An. Generally, since the occupied area Ap of the P-MOS transistor is larger than the forming area An of the N-MOS transistor, Ap + An> 2An.

In this embodiment, the circuit for selectively outputting the ground level waveform of the _second vertical transfer pulse P ₂ is constituted by the single first N-MOS transistor Tr1. As shown in FIG. 3 (b), this first
Even if the occupying area A of the N-MOS transistor Tr1 is set to be twice (2An) the occupying area An of the N-MOS transistor forming the transfer gate, the area A is the entire occupying area of the transfer gate. Will be smaller than.

As described above, according to the binary driver circuit of the above-described embodiment, the entire chip area can be reduced as compared with the conventional one using the transfer gate, and the low power consumption can be achieved. Can be made.

From the waveform diagram of the simulation shown in FIG. 2, the time required for the pulse signal Po (second vertical transfer pulse P ₂ ) output from the binary driver circuit to rise from the low level to the ground level becomes very short. It can be seen that the characteristics of the output signal waveform (output transition time) are improved.

Next, the ternary driver circuit according to the present embodiment for generating the _first vertical transfer pulse P ₁ will be described with reference to FIGS.
Will be described with reference to. The same reference numerals are given to those corresponding to FIG.

As shown in FIG. 4, the ternary driver circuit according to this embodiment is similar to the binary driver circuit in that
Of the first and second N-MO transistors Tr1 and Tr2.
The common source terminal b of the S transistors Tr1 and Tr2 is used as a source, and a P-MOS transistor Tr3 to which a high-level power supply voltage V _H (= + 15 V) is applied is connected to the drain terminal. The gate electrode of the MOS transistor Tr3, the gate electrode of the first N-MOS transistor Tr1 and the gate electrode of the second N-MOS transistor Tr2 have first, second and third reference clocks Pc1, which have mutually different phases. Pc2
And Pc3 are input via input terminals φ1, φ2, and φ3, respectively. Each reference clock Pc
1, Pc2 and Pc3 have binary pulse signal waveforms with a high level potential of 5V and a low level potential of 0V. The substrate bias potential of the P-MOS transistor Tr3 is the high level potential _VH (= + 15V).

The signal processing of the ternary driver circuit according to this embodiment will be described with reference to the waveform chart by simulation shown in FIG. First, the first and third reference clocks Pc
1 and Pc3 are high level potentials, the second reference clock Pc
In the period in which 2 is a low level potential, the output potential of the P-MOS transistor Tr3 is off, the first N-MOS transistor Tr1 is off, and the second N-MOS transistor Tr2 is on. It becomes the low level potential V _L. Next, the first and second reference clocks P
c1 and Pc2 are high level potentials, the third reference clock P
During the period when c3 is at the low level potential, the P-MOS
Since the transistor Tr3 turns off, the first N-MOS transistor Tr1 turns on, and the second N-MOS transistor Tr2 turns off, the output potential becomes the ground level potential Vs.

Next, while the first, second and third reference clocks Pc1, Pc2 and Pc3 are at low level potentials respectively, the P-MOS transistor Tr3 is turned on and the first N-MOS transistor Tr1 is turned on. Is turned off and the second N-MOS transistor Tr2 is turned off, so that the output potential becomes the high level potential V _H. Therefore, the ternary pulse signal Po, that is, the first vertical transfer pulse P _{1 in} the above example is applied to the load 2.

As described above, also in the ternary driver circuit according to this embodiment, the circuit for selectively outputting the ground level waveform of the _first vertical transfer pulse P ₁ is the first NM alone.
Since the circuit configured by the OS transistor Tr1 and selectively outputting the low-level waveform of the _first vertical transfer pulse P1 is configured by the single second N-MOS transistor Tr2, Transfer circuit as a circuit that selectively outputs the ground level waveform of the vertical transfer pulse Tr1 of
Compared to the conventional one using a gate, the occupied area required for forming the element can be reduced, and the entire chip area can be reduced as compared with the conventional one using a transfer gate. Power consumption can also be achieved. Moreover, in the ternary driver circuit according to this embodiment, the first reference clock P ₁ is directly fed to the first N-MO.
Since the input is applied to the gate electrode of the S-transistor Tr1, the CMOS inverter inserted in the input line of the second reference clock Pc2 should be deleted when compared with the conventional ternary driver circuit shown in FIG. The chip area can be reduced accordingly.

From the waveform diagram by the simulation of FIG. 5, the time for the pulse signal Po (first vertical transfer pulse P ₁ ) output from the ternary driver circuit to rise from the low level to the ground level and the high level from the ground level. It can be seen that the time to rise to the level is very fast and the characteristics of the output signal waveform (output transition time) are improved.

Therefore, two three-valued driver circuits shown in FIG. 4 and two shown in FIG. 1 are provided corresponding to the first to fourth vertical transfer electrodes arranged along the vertical register of the CCD solid-state image pickup device. Of the _first to fourth vertical transfer pulses P1 to P4 supplied to the first to fourth vertical transfer electrodes, respectively, two value driver circuits are provided, and the first and _fourth read pulse having the read pulse are provided. The third vertical transfer pulses P ₁ and P ₃ are generated by the two ternary driver circuits, respectively, and the second and fourth vertical transfer pulses P ₂ and P ₄ having no read pulse are generated by the two binary drivers. If each is generated by the circuit, it is possible to provide the _first to fourth vertical transfer pulses P _{1 to} P ₄ having a very fast rise time, and unnecessary signal charges that have been a problem in the past are unnecessary. Reproduced image due to mixing It is possible to prevent the occurrence of interference noise.

That is, for example, as shown in FIG. 6, by applying the _first to fourth vertical transfer pulses P _{1 to} P ₄ having mutually different phases to the first to fourth vertical transfer electrodes TG 1 to TG _4. , Consider the case where the signal charge e is transferred to the horizontal register side along the vertical register.

First, as shown in FIG. 7, the first and fourth vertical transfer pulses P ₁ and P ₄ are at the low level potential V _L , and the second and third vertical transfer pulses P ₂ and P ₃ are grounded. At the time t ₁ which is the level potential Vs, from the state where the signal charge e is accumulated in the potential well formed continuously under the second and third vertical transfer electrodes TG2 and TG3,
_As shown at ₃ o'clock, by setting the second vertical transfer pulse P ₂ to the low level potential V _L and the fourth vertical transfer pulse P ₄ to the ground level potential Vs, one stage of the vertical transfer electrode is moved to the horizontal register side. Looking at the transfer process, the second transfer pulse P
_Although the fall time of ₂ is slow, the rise time of the _fourth transfer pulse P ₄ is very fast, so that a potential well having a sufficient depth is continuously formed below the third and fourth vertical transfer electrodes TG3 and TG4. Will be done. Therefore, in the transfer process, the signal charges e accumulated in the potential wells do not overflow, and the problem that the signal charges are unnecessarily mixed between adjacent potential wells does not occur.

Therefore, the binary driver circuit and the ternary driver circuit according to the present embodiment are applied to the vertical transfer section for vertically transferring the signal charges accumulated in each light receiving section of the CCD solid-state image pickup device row by row. When applied to a drive pulse generation circuit that generates a vertical transfer pulse and a read pulse, the vertical transfer charge amount in the vertical transfer unit can be improved, and the image quality of a reproduced image is deteriorated (so-called V sag or smear). Can be suppressed.

Further, since the formation area of the binary driver circuit and the ternary driver circuit is reduced, it is possible to reduce the power consumption and the size of the IC of the electronic device equipped with the CCD solid-state image pickup device. It is possible to reduce the size and weight of the electronic device.

From the above, if the binary driver circuit and the ternary driver circuit according to the present embodiment are used, high density formation of pixels in the CCD solid-state image pickup device in recent years, speedup by the frame / interline transfer system, It is possible to promote miniaturization of an electronic device equipped with a CCD solid-state image sensor.

In the above three-value driver circuit, the second N-MOS transistor Tr1 is directly connected to the gate electrode of the second N-MOS transistor Tr1.
The second reference clock Pc2 is input to the second reference clock Pc2 as shown in FIG.
You may make it input into the gate electrode of the 1st N-MOS transistor Tr1 via the MOS inverter 3. In this case, the second reference clock Pc2 has a signal waveform obtained by inverting the signal waveform of the second reference clock shown in FIG. 5, as shown in FIG.

In the above example, the first to fourth vertical transfer electrodes TG are mainly used in the vertical transfer section of the CCD solid-state image pickup device.
Although the binary driver circuit and the ternary driver circuit for generating the _first to fourth vertical transfer pulses P _{1 to} P ₄ to be supplied to the 1 to TG ₄ have been described, the drive pulse generating circuit according to the present embodiment is also described. Can also be applied to an inverting circuit.

That is, in the normal inverting circuit, as shown in FIG. 10A, the P-MOS transistor Qp to which the high level power supply voltage V _H is applied to the drain terminal and the low level power supply voltage to the drain terminal are provided. The N-MOS transistor Qn to which _VL is applied is connected in series at the common source terminal b, and the input signal S supplied to the input terminal φin is supplied to the gate electrodes of the transistors Qp and Qn via the input side node a. Is connected to the common source terminal b through the output terminal φout to output the output signal So.
Is configured to take out. In this case, in order to increase the driving force of the inverting circuit, it is necessary to increase the occupied areas Ap and An of the P-MOS transistor Qp and the N-MOS transistor Qn as shown in FIG.

On the other hand, in the inverting circuit according to the present embodiment, as shown in FIG. 10B, instead of the P-MOS transistor Qp in the normal inverting circuit, the N-MO transistor is used.
An S transistor Qn is provided, and a CMOS inverter 11 is connected between the N-MOS transistor Qn and the input side node a.

In this case, in combination with the CMOS inverter 11, the number of transistors is three N-MOS transistors and one P-MOS transistor, resulting in the use of four transistors. 11
As shown in (b), the occupying areas Ap and An of each transistor are small, and even if the occupying areas Ap and An of each transistor are increased in order to increase the driving force, the enlargement width is small, and the above-mentioned normal In the case of an inverting circuit (Fig. 1
1 (a)), the entire occupied area A (= Ap + 3
An) is small.

Moreover, since the CMOS inverter 11 is inserted, the characteristics of the output waveform can be improved.

[0075]

As described above, according to the drive pulse generation circuit of the present invention, a timing signal having a binary signal level is input, and the ON operation is performed when the timing signal has one value. A first switching circuit that selectively outputs a first signal level waveform that constitutes a drive pulse, and the timing signal are input, and an ON operation is performed when the timing signal has the other value, And a second switching circuit that selectively outputs a second signal level waveform that forms the drive pulse. Further, the first and second switching circuits are both N-channel type of a single unit. Since the MIS transistor is used, the chip area where the drive pulse generating circuit that outputs a pulse signal having at least a binary signal level waveform is formed is reduced. Reduction can be achieved, yet it is possible to reduce the power consumption, it is possible to additionally improve the characteristics of the output signal waveform of the drive pulses to be generated (output transition time).

Further, the timing signals are first, second and third timing signals which are independently supplied and have mutually different phases, and the third and third switching circuits are provided in addition to the first and second switching circuits. A third switching circuit, which is selectively turned on in response to the input of the timing signal and selectively outputs the third signal level waveform forming the drive pulse, is provided. The switching circuit selectively outputs the first signal level waveform based on the input of the first timing signal, and the second switching circuit outputs the first signal level waveform based on the input of the second timing signal. And selectively output the second signal level waveform, and the third switching circuit is composed of a single P-channel MIS transistor. Therefore, it is possible to reduce the chip area in which the drive pulse generation circuit that outputs the pulse signal having the ternary signal level waveform is formed, and further it is possible to reduce the power consumption. Characteristics of the output signal waveform of the drive pulse generated by (output transition time)
Can be improved.

Therefore, the vertical transfer applied to the vertical transfer unit for vertically transferring the signal charges accumulated in each light receiving unit of the solid-state image pickup device having the image pickup region in which a plurality of light receiving units are arranged in a vertical direction. When applied to a drive pulse generation circuit that generates a pulse and a read pulse, the vertical transfer charge amount in the vertical transfer unit can be improved, and deterioration of the image quality of a reproduced image (so-called V sag, smear, etc.) can be suppressed. It becomes possible. Further, when applied to a drive pulse generation circuit that generates a vertical transfer pulse and a read pulse of the solid-state image pickup device, it is possible to achieve low power consumption and downsizing of an IC of an electronic device equipped with this solid-state image pickup device. It is possible to reduce the size and weight of the electronic device.

[Brief description of drawings]

FIG. 1 is an embodiment in which a drive pulse generation circuit according to the present invention is applied to a binary driver circuit for generating a vertical transfer pulse in an image sensor of an interline transfer system using a CCD solid-state image sensor (hereinafter, FIG. 3 is a circuit diagram showing a binary driver circuit according to an embodiment).

FIG. 2 is a timing chart showing signal processing of the binary driver circuit according to the present embodiment.

FIG. 3 is a circuit diagram of an N constituting a binary driver circuit according to this embodiment.
-A conceptual diagram showing the occupied area of a MOS transistor in comparison with that of a conventional transfer gate. Fig. 10A shows the occupied area of a conventional transfer gate, and Fig. 9B shows the N-MOS. The occupied area of the transistor is shown.

FIG. 4 is an example in which the drive pulse generation circuit according to the present invention is applied to a ternary driver circuit for generating a vertical transfer pulse in an image sensor of, for example, an interline transfer system using a CCD solid-state image sensor (hereinafter, FIG. 3 is a circuit diagram showing a ternary driver circuit according to an embodiment).

FIG. 5 is a timing chart showing signal processing of the ternary driver circuit according to the present embodiment.

FIG. 6 is an operation showing a transfer state of signal charges by applying these vertical transfer pulses when the first to fourth vertical transfer pulses are generated by the binary driver circuit and the ternary driver circuit according to the present embodiment. It is a conceptual diagram.

FIG. 7 is a timing chart showing first to fourth vertical transfer pulses created by the binary driver circuit and the ternary driver circuit according to the present embodiment.

FIG. 8 is a circuit diagram showing another example of the three-value driver circuit according to the present embodiment.

FIG. 9 is a timing chart showing signal processing of another example of the three-value driver circuit according to the present embodiment.

FIG. 10 is a circuit diagram showing an embodiment in which the drive pulse generation circuit according to the present invention is applied to an inverting circuit (hereinafter, simply referred to as an inverting circuit according to the embodiment) in comparison with a normal inverting circuit; The figure (a) shows the normal inverting circuit, and the figure (b) shows the inverting circuit according to the present embodiment.

FIG. 11 is a graph showing the occupied area of each transistor forming the inverting circuit according to the present embodiment as the CMO forming the normal inverting circuit.
It is a conceptual diagram shown in comparison with the occupied area of the S-transistor, the figure (a) shows the occupied area of a normal inverting circuit, the same figure (b) shows each transistor constituting the inverting circuit according to the present embodiment. Indicates the occupied area.

FIG. 12 is a circuit diagram showing a binary driver circuit according to a conventional example.

FIG. 13 is a timing chart showing signal processing of a binary driver circuit according to a conventional example.

FIG. 14 is a circuit diagram showing a three-value driver circuit according to a conventional example.

FIG. 15 is a timing chart showing signal processing of a ternary driver circuit according to a conventional example.

FIG. 16 is an operation concept showing a transfer state of signal charges due to application of these vertical transfer pulses when the first to fourth vertical transfer pulses are generated by the binary driver circuit and the ternary driver circuit according to the conventional example. It is a figure.

FIG. 17 is a timing chart showing first to fourth vertical transfer pulses created by a binary driver circuit and a ternary driver circuit according to a conventional example.

[Explanation of symbols]

Tr1 First N-MOS transistor Tr2 Second N-MOS transistor Tr3 P-MOS transistor 1,3 CMOS inverter 2 Load Pc Reference clock Pc1, Pc2 and Pc3 First, second and third reference clocks TG1 to TG4 First to fourth vertical transfer electrodes P _{1 to} P ₄ First to fourth vertical transfer pulses

Claims (5)

[Claims] 1. A timing signal having a binary signal level is input, and an ON operation is performed when the timing signal has one value to selectively output a first signal level waveform forming a drive pulse. A first switching circuit for outputting and the timing signal are input, and when the timing signal has the other value, an ON operation is performed to selectively output a second signal level waveform forming the drive pulse. Second
2. The drive pulse generation circuit according to claim 1, wherein each of the first and second switching circuits is composed of a single N-channel type MIS transistor. 2. The timing signals are first, second and third timing signals which are supplied independently of each other and have different phases, and the third and third switching circuits are provided in addition to the first and second switching circuits. And a third switching circuit for selectively outputting a third signal level waveform constituting the drive pulse, the ON operation being selectively performed based on the input of the timing signal The circuit selectively outputs the first signal level waveform based on the input of the first timing signal, and the second switching circuit selects based on the input of the second timing signal. To output the second signal level waveform, and the third switching circuit is a single P-channel type M
The drive pulse generation circuit according to claim 1, wherein the drive pulse generation circuit comprises an IS transistor. 3. The drive pulse generation circuit according to claim 1, wherein an inverting circuit is connected to a stage preceding the first switching circuit or the second switching circuit. 4. The drive pulse composed of the first signal level waveform and the second signal level waveform is applied to each of the light receiving parts of the solid-state imaging device having an imaging region in which a plurality of light receiving parts are arranged. 4. The drive pulse generation circuit according to claim 1, wherein the drive pulse generation circuit is a vertical transfer pulse applied to a vertical transfer unit that vertically transfers the accumulated signal charges in a row unit. 5. A solid-state image pickup device having an image pickup area in which a plurality of light receiving portions are arranged, among the first to third signal level waveforms forming the drive pulse. Is a vertical transfer pulse applied to a vertical transfer unit that vertically transfers the signal charge accumulated in each of the light receiving units in a row unit, and the third signal level waveform is accumulated in each of the light receiving units. 5. The drive pulse generation circuit according to claim 2, wherein the drive pulse generation circuit is a read pulse for transferring the signal charge to the vertical transfer unit.