JP2010041361A - Solid-state imaging apparatus, method of driving the same, and imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To ensure that rising characteristics of a readout pulse are steep and that trailing characteristics of a transfer pulse are gradual without change in a driver side of the chip exterior. <P>SOLUTION: As for vertical transfer pulses ϕV1 to ϕV4 applied to pads 31/32, carrying out transmission via a first transmission path 41 including a resistance element 412 causes the trailing characteristics tf of the vertical transfer pulses ϕV1 to ϕV4 made gradual. As for a readout pulse ϕROP, carrying out transmission via a second transmission path 42 having a lower resistance value than that of the first transmission path 41 causes the rising characteristics tr of the readout pulse ϕROP to be steep. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device, a driving method of the solid-state imaging device, and an imaging device, and in particular, a charge transfer type solid-state imaging device represented by a CCD (Charge Coupled Device) solid-state imaging device, a driving method of the solid-state imaging device, and the solid state The present invention relates to an imaging apparatus using the imaging apparatus.

  A charge transfer solid-state imaging device, for example, a CCD solid-state imaging device, includes a sensor unit that performs photoelectric conversion, a read gate unit that reads signal charges accumulated in the sensor unit, and a signal charge that is read by the read gate unit. And a charge transfer portion for transferring. In the case of an area sensor, the charge transfer unit transfers a signal charge in the pixel arrangement direction (vertical direction) of the pixel column and a horizontal transfer unit that transfers the signal charge in the pixel arrangement direction (horizontal direction) of the pixel row. It consists of a transfer part.

  In general, a transfer electrode of a specific phase of the vertical transfer unit, for example, in the case of four-phase driving, each transfer electrode corresponding to the first phase and the third phase also serves as the gate electrode of the read gate unit It has become. From this, among the four-phase transfer pulses φV1 to φV4, the first-phase and third-phase transfer pulses φV1 and φV3 take three values of low level, intermediate level, and high level. The third high-level pulse is used as a read pulse applied to the gate electrode of the read gate section (see, for example, Patent Document 1).

JP 2007-142696 A (refer to paragraph 0018 and FIG. 2 in particular)

  Here, when the intermediate level is 0 V, the read pulse is a positive voltage pulse, and the transfer pulse is a negative voltage pulse. The peak value (maximum voltage value) of the read pulse is set to a voltage value much higher than the peak value of the transfer pulse.

  In order for the readout pulse to reach the maximum value within the specified time and the signal charge to be reliably read out, it is more advantageous that the rise characteristic tr of the readout pulse is steeper. On the other hand, with respect to the transfer of signal charges in the charge transfer section, a gradual transfer pulse falling characteristic tf is advantageous because a transfer electric field can be secured.

  However, with respect to the read pulse and the transfer pulse, the rise characteristic tr and the fall characteristic tf of the read pulse and the transfer pulse are the same unless changed on the driver side such as a timing generator outside the chip (substrate). . Therefore, it is impossible to achieve both the steep rise characteristic tr of the read pulse and the slow fall characteristic tf of the transfer pulse.

  Therefore, the present invention provides a solid-state imaging device, a driving method for the solid-state imaging device, and an imaging device capable of making both the rising characteristics of the readout pulse steep and the falling characteristics of the transfer pulse gentle. The purpose is to provide.

In order to achieve the above object, the present invention provides:
A sensor unit that performs photoelectric conversion;
A read gate unit for reading out signal charges accumulated in the sensor unit;
A charge transfer unit that transfers the signal charge read by the read gate unit, and a transfer electrode of a specific phase also serves as the gate electrode of the read gate unit;
On the substrate on which the sensor unit, the read gate unit, and the charge transfer unit are formed, a transfer pulse that drives the transfer electrode and the read gate provided in the middle of the wiring connected to the transfer electrode that also serves as the gate electrode In a solid-state imaging device including a pulse transmission unit that transmits a readout pulse that drives the unit,
The pulse transmission unit is provided with a first transmission line including a resistance element and a second transmission line having a resistance value lower than that of the first transmission line,
The transfer pulse is transmitted to the transfer electrode through a first transmission path, and the read pulse is transmitted to the read gate unit through a second transmission path.

  In the solid-state imaging device having the above configuration, the transfer pulse is transmitted by the first transmission path including the resistance element, so that the transfer pulse is input to the first transmission path by the resistance component (including the wiring resistance) of the resistance element. Fall more slowly than. On the other hand, by transmitting the read pulse through the second transmission path having a resistance value lower than that of the first transmission path, the read pulse rises more steeply than when the read pulse is transmitted through the first transmission path. In other words, due to the action of the first and second transmission lines of the pulse transmission unit provided on the semiconductor substrate, the rising characteristics of the read pulse can be sharpened and transferred without changing on the driver side outside the chip. It is possible to make the falling characteristics of the pulse gentle.

  According to the present invention, it is possible to make both the rising characteristics of the read pulse steep and the falling characteristics of the transfer pulse gradual without changing on the driver side outside the chip. As a result, the signal charge transfer performance can be improved while maintaining the signal charge read performance.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the present embodiment, a case where the present invention is applied to, for example, an interline transfer (IT) type CCD solid-state imaging device will be described as an example.

  FIG. 1 is a schematic configuration diagram showing an example of a CCD solid-state imaging device to which the present invention is applied. In FIG. 1, an imaging unit 11 includes a plurality of sensor units (pixels) 12 two-dimensionally arranged in a matrix, a readout gate unit 13 provided adjacent to the sensor units 12, and a matrix pixel array. On the other hand, it is composed of a vertical transfer unit 14 composed of a CCD provided for each pixel column.

  In the imaging unit 11, one unit including a packet of one sensor unit 12, a reading gate unit 13 adjacent to the sensor unit 12, and a vertical transfer unit 14 corresponding to one sensor unit 12 is a unit cell 15. Here, the packet of the vertical transfer unit 14 is a unit for handling the signal charge for one pixel in the vertical transfer unit 14. Then, the transfer channel of the vertical transfer unit 14 is formed by continuously connecting these packets.

  The sensor unit 12 is composed of, for example, a PN junction photodiode, and photoelectrically converts incident light into a signal charge having a charge amount corresponding to the luminance level and accumulates the signal light. The read gate unit 13 reads the signal charges accumulated in the sensor unit 12 to the vertical transfer unit 14 by applying a read pulse φROP. The vertical transfer unit 14 is driven to transfer by, for example, four-phase vertical transfer pulses φV1 to φV4, and the signal charges read from the sensor unit 12 by the read gate unit 13 are scanned by one scanning line in part of the horizontal blanking period. The portions corresponding to (one line) are sequentially transferred in the vertical direction. Here, the vertical direction refers to the arrangement direction of the pixels in the pixel column.

  Here, in the vertical transfer unit 14, four transfer electrodes corresponding to the four-phase vertical transfer pulses φV1 to φV4 are repeatedly arranged in the transfer direction above a transfer channel in which packets are connected. For example, each transfer electrode corresponding to the first phase and the third phase also serves as the gate electrode of the read gate unit 13. From this, among the four-phase vertical transfer pulses φV1 to φV4, the first-phase and third-phase vertical transfer pulses φV1 and φV3 take the three values of the low level, the intermediate level, and the high level. A high level pulse becomes a read pulse φROP applied to the read gate section 13.

  That is, the third-phase read pulse φROP of the first-phase and third-phase vertical transfer pulses φV1 and φV3 is applied to each transfer electrode (gate electrode of the read gate unit 13) corresponding to the first and third phases. The As a result, the signal charge accumulated in the sensor unit 12 is read out to the vertical transfer unit 14. The vertical transfer pulses φV2 and φV3 of the second phase and the fourth phase have binary values of a low level and an intermediate level. Then, the four-phase vertical transfer pulses φV1 to φV4 periodically transition between the low level and the intermediate level, whereby the transfer drive of the vertical transfer unit 14 is performed, and the signal charge read from the sensor unit 12 is changed. The vertical transfer unit 14 performs vertical transfer.

  On one end side of the vertical transfer unit 14, a horizontal transfer unit 16 composed of a CCD is disposed. Signal charges corresponding to one line are sequentially shifted (transferred) from the plurality of vertical transfer units 14 to the horizontal transfer unit 16. The horizontal transfer unit 16 is driven to transfer by, for example, two-phase horizontal transfer pulses φH1 and φH2, so that the signal charge for one line shifted from the plurality of vertical transfer units 14 is converted into the horizontal after the horizontal blanking period. The images are sequentially transferred in the horizontal direction during the scanning period. Here, the horizontal direction refers to the arrangement direction of the pixels in the pixel row.

  At the end of the horizontal transfer unit 16 on the transfer destination side, for example, a charge voltage conversion unit 17 having a floating diffusion amplifier configuration is provided. The charge / voltage converter 17 sequentially converts the signal charges horizontally transferred by the horizontal transfer unit 16 into signal voltages and outputs the signal voltages. This signal voltage enters the imaging unit 11 through the subject, and is output as an imaging signal OUT obtained by photoelectric conversion by the sensor unit 12 according to the luminance level.

  The components such as the sensor unit 12, the read gate unit 13, the vertical transfer unit 14, the horizontal transfer unit 16, and the charge / voltage conversion unit 17 described above are formed on a semiconductor substrate (hereinafter also referred to as “chip”) 18. Is formed. The semiconductor substrate 18 is biased by a substrate bias voltage Vsub described later. The interline transfer type CCD solid-state imaging device 10 is configured as described above.

  The drive control of the CCD solid-state imaging device 10 is performed by timing control by a timing control circuit 21 outside the chip. The timing control circuit 21 controls the CCD drive circuit 22 and the shutter drive circuit 23 in order to control various operations of the CCD solid-state imaging device 10 based on the vertical synchronization signal VD, the horizontal synchronization signal HD, and the master clock MCK. To do. Here, various operations include control of a signal charge accumulation (exposure) period in the sensor unit 12, readout of signal charges from the sensor unit 12 to the vertical transfer unit 14, vertical transfer in the vertical transfer unit 14, horizontal Examples include horizontal transfer in the transfer unit 16 and reset operation of the charge-voltage conversion unit 17.

  Specifically, the timing control circuit 21 performs drive control of the CCD drive circuit 22 so that one frame (frame) image can be obtained in two fields in order to perform field reading. Under the timing control by the timing control circuit 21, the CCD drive circuit 22 drives the vertical transfer unit 14 and the horizontal transfer unit 16 by the four-phase vertical transfer pulses φV1 to φV4 and the two-phase horizontal transfer pulses φH1 and φH2. .

  The shutter drive circuit 23 sweeps the signal charges accumulated in the sensor unit 12 toward the semiconductor substrate 18 by applying a shutter pulse φVsub to the semiconductor substrate 18 at a predetermined timing under timing control by the timing control circuit 21. An electronic shutter operation is performed. By this electronic shutter operation, the accumulation period in which the signal charge is accumulated in the sensor unit 12, that is, the exposure period is controlled. At this time, the shutter pulse φVsub is applied in a form superimposed on the substrate bias voltage Vsub for biasing the semiconductor substrate 18.

  FIG. 2 shows the timing relationship between the four-phase vertical transfer pulses φV1 to φV4 and the read pulse φROP. As is apparent from FIG. 2, the read pulse φROP is a positive voltage pulse, and the vertical transfer pulses φV1 to φV4 are negative voltage pulses. In this example, the low level of the vertical transfer pulses φV1 to φV4 is set to −7.5V, the high level (intermediate level) is set to 0V, and the voltage value (high level) of the read pulse φROP is set to 13V. However, these numerical values are only examples, and are not limited to the numerical values.

  As apparent from FIG. 2, the read pulse φROP becomes active (high level) in the vertical blanking period (V-Blk) of each field. As a result, signal charges are read from the sensor unit 12 to the vertical transfer unit 14 by the read gate unit 13. Further, the operation in which the four-phase vertical transfer pulses φV1 to φV4 transition between the intermediate level (0 V) and the low level (−7.5 V) is periodically repeated in the horizontal blanking period (H-Blk). By the transfer driving by the vertical transfer pulses φV1 to φV4, the vertical transfer unit 14 transfers the signal charge in the vertical direction.

  Here, consider the transmission unit of the vertical transfer pulses φV1 to φV4. As shown in FIG. 3, the first-phase and third-phase vertical transfer pulses φV1 and φV3 including the read pulse φROP are input into the semiconductor substrate 18 from the CCD drive circuit 22 outside the chip via the pad 31. The second-phase and fourth-phase vertical transfer pulses φV2 and φV4 not including the read pulse φROP are input from the CCD drive circuit 22 into the semiconductor substrate 18 via the pad 32. On the semiconductor substrate 18, generally, the vertical transfer unit 14 is supplied through the wirings 33 and 34 between the pads 31 and 32 and the imaging unit 11.

  As described above, when the vertical transfer pulses φV1 to φV4 are simply transmitted through the wirings 33 and 34, the read pulse φROP and the vertical transfer pulses φV1 to φV4 have the same rising characteristics tr and falling characteristics tf. However, this is not the case when changes are made on the driver side such as the timing control circuit 21.

  Therefore, it is impossible to make both the rising characteristic tr of the read pulse φROP steep and the falling characteristic tf of the vertical transfer pulses φV1 to φV4 gradual. That is, if the transition characteristic tr / tf of the read pulse φROP is designed to be steep, the falling characteristics tf of the vertical transfer pulses φV1 to φV4 also become steep. Conversely, if the transition characteristics of the vertical transfer pulses φV1 to φV4 are designed to be gentle, the rising characteristic tr of the read pulse φROP also becomes gentle.

  Incidentally, as described above, in order for the readout pulse φROP to reach the maximum value within the specified time and the signal charge to be reliably read out, the steep rise characteristic tr of the readout pulse φROP is more advantageous. is there. On the other hand, with respect to the transfer of signal charges in the vertical transfer unit 14, the gradual falling characteristics tf of the vertical transfer pulses φV1 to φV4 is advantageous because the transfer electric field can be secured.

[Characteristics of this embodiment]
In the present embodiment, the rising characteristic tr of the read pulse φROP is made steep and the falling characteristics tf of the vertical transfer pulses φV1 to φV4 are made gradual without changing on the driver side outside the chip. In order to achieve both, the following configuration is adopted.

  That is, a first transmission path including a resistance element and a second transmission path having a resistance value lower than that of the first transmission path are provided in the transmission unit of the vertical transfer pulses φV1 to φV4 on the chip (substrate). Then, the vertical transfer pulses φV1 to φV4 are transmitted to the transfer electrode of the vertical transfer unit 14 through the first transmission path, and the read pulse φROP is transmitted to the gate electrode of the read gate unit 13 through the second transmission path.

  By transmitting the vertical transfer pulses φV1 to φV4 through the first transmission path including the resistance element, the falling characteristics tf of the vertical transfer pulses φV1 to φV4 are caused by the resistance component (including the wiring resistance) of the resistance element. It will be more gradual than when it enters the road. On the other hand, when the read pulse φROP is transmitted through the second transmission line having a resistance value lower than that of the first transmission line, the rising characteristic tr of the read pulse φROP is steeper than that in the case of transmitting through the first transmission line. .

  That is, due to the action of the first and second transmission lines, the rising characteristic tr of the read pulse φROP is made steep and the falling characteristics of the vertical transfer pulses φV1 to φV4 without changing on the driver side outside the chip. Both tf can be made moderate. As a result, the signal charge transfer performance of the vertical transfer unit 14 can be improved while maintaining the signal charge read performance of the read gate unit 13.

  Hereinafter, specific examples of the first and second transmission lines provided in the pulse transmission units of the vertical transfer pulses φV1 to φV4 will be described.

  The first and second transmission lines are the first-phase / third-phase transfer electrodes of the vertical transfer unit 14 from the pad 31 to which the first-phase and third-phase vertical transfer pulses φV1 and φV3 including the read pulse φROP are input. In the middle of the wiring 33 connected to the transfer electrode of the first phase / third phase. The first and second transmission lines are also provided in the middle of the wiring 34 on the pad 32 side where the second-phase and fourth-phase vertical transfer pulses φV2 and φV4 that do not include the read pulse φROP are input.

Example 1
FIG. 4 is a circuit diagram illustrating the configuration of the pulse transmission unit according to the first embodiment.

  Here, the pulse transmission units on the first phase and third phase vertical transfer pulses φV1 and φV3 side will be described as a representative, but the second phase and fourth phase vertical transfer pulses φV2 and φV4 side pulse transmission units are also described. It becomes the same composition. As a matter of course, the pulse transmission units of the vertical transfer pulses φV1 to φV4 are provided independently of each other.

  The pulse transmission unit according to the first embodiment includes a first transmission path 41 having a diode 411 that is a unidirectional element and a resistance element 412 made of, for example, polysilicon, and a second transmission path 42 having a diode 421. ing.

  The diode 411 is provided so that the cathode electrode is on the pad 31 side. Resistance element 412 is connected in series to diode 411. In this example, the resistance element 412 is connected to the diode 411 in series, for example, on the anode electrode side. The diode 421 is connected in parallel to the series connection circuit of the diode 411 and the resistance element 412 so that the anode electrode is on the pad 31 side.

  In the pulse transmission unit according to the first embodiment having the above configuration, first, a circuit operation when the read pulse φROP is applied to the pad 31 will be described. As described above, the read pulse φROP is a positive voltage pulse. Therefore, at the moment when the read pulse φROP is applied to the pad 31, the diode 411 on the first transmission path 41 side is reverse-biased, so that the diode 411 becomes non-conductive.

  On the other hand, with respect to the diode 421 on the second transmission path 42 side, the read pulse φROP is applied to the pad 31 and becomes forward biased at the moment when the read pulse φROP rises from 0V to 13V. It becomes. Accordingly, the wiring system and the transfer electrode are charged through the second transmission path 42 by the read pulse φROP applied to the pad 31.

  At this time, since only the diode 421 is provided in the second transmission path 42, the resistance value of the second transmission path 42 is larger than the resistance value of the first transmission path 41 when the diode 411 is in a conductive state. Very small. Therefore, the rising characteristic (waveform) tr of the read pulse φROP transmitted through the second transmission path 42 is steep, similar to the waveform when applied to the pad 31.

  However, when the read pulse φROP disappears, that is, when the read pulse φROP transitions from 13V to 0V, the diode 411 becomes forward biased and becomes conductive, and the diode 421 becomes reverse biased and becomes nonconductive. Therefore, since the falling characteristic tf of the read pulse φROP is determined by the time constant of the first transmission line 41 including the resistance element 412, the waveform becomes dull (tr ≠ tf).

  Here, the falling characteristic tf of the read pulse φROP has a dull waveform, and even if it gradually transitions, it is after the signal charge read operation has been completed, and thus has an influence on the signal charge read operation. There is nothing. What is important for reliably reading the signal charge is that the rising characteristic tr of the read pulse φROP is steep.

  Next, the circuit operation when the first-phase / third-phase vertical transfer pulses φV1 / φV3 are applied to the pad 31 will be described. As described above, the vertical transfer pulses φV1 / φV3 are negative voltage pulses. Accordingly, at the moment when the vertical transfer pulse φV1 / φV3 is applied to the pad 31, the diode 421 on the second transmission path 42 side is reverse-biased, so that the diode 421 becomes non-conductive.

  On the other hand, for the diode 411 on the first transmission line 41 side, the vertical transfer pulse φV1 / φV3 is applied to the pad 31, and at the moment when the vertical transfer pulse φV1 / φV3 falls from 0V to −7.5V, the forward bias is applied. Therefore, it becomes a conductive state. Therefore, the transfer electrodes and the wiring system are charged through the first transmission path 41 by the vertical transfer pulses φV1 / φV3 applied to the pad 31.

  At this time, a resistance element 412 is connected to the first transmission path 41 in series with the diode 411, and the falling characteristic tf of the vertical transfer pulse φV1 / φV3 is the first transmission path 41 including the resistance element 412. Since it is determined by a constant, the waveform becomes dull. That is, the falling characteristic tf of the vertical transfer pulse φV1 / φV3 becomes gentler than when applied to the pad 31.

  However, when the vertical transfer pulse φV1 / φV3 disappears, that is, when the vertical transfer pulse φV1 / φV3 transits from −7.5V to 0V, the diode 421 becomes forward biased and becomes conductive, and the diode 411 becomes reverse biased. Becomes a non-conductive state. Therefore, the rising characteristic tr of the vertical transfer pulse φV1 / φV3 becomes steep (tr ≠ tf).

  Here, even if the rising characteristic tr of the vertical transfer pulse φV1 / φV3 has a steep waveform, it is the falling characteristic tf that is advantageous for securing the transfer electric field, and therefore the transfer operation is affected. There is no. That is, what is important for securing the transfer electric field is that the falling characteristics tf of the vertical transfer pulses φV1 / φV3 are gentle.

  FIG. 5 shows waveforms of the read pulse φROP (A) and the vertical transfer pulses φV1 / φV3 (B). 5A and 5B, when (a) does not adopt the configuration of the first embodiment, (b) shows the read pulse φROP and the vertical transfer pulses φV1 / φV3 when the configuration of the first embodiment is employed. Each waveform is shown.

  In the case where the configuration of the first embodiment is not adopted, both the read pulse φROP and the vertical transfer pulses φV1 / φV3 have the rising characteristic tr = the falling characteristic tf. On the other hand, in the case of the first embodiment, neither the read pulse φROP nor the vertical transfer pulse φV1 / φV3 substantially maintains the steep rising characteristic tr, and the falling characteristic tf does not adopt the configuration of the first embodiment. Compared to the case, it can be made gentler (tr ≠ tf).

  As described above, with respect to the read pulse φROP, since the rising characteristic tr is steep, the read pulse φROP reaches the maximum value within a specified time, so that the signal charge can be reliably read out. Further, for the first-phase and third-phase vertical transfer pulses φV1 and φV3, the falling characteristics tf are gentle, which is advantageous because a transfer electric field can be secured.

  The first and second transfer paths 41 and 42 are provided on the wiring 34 side for transmitting the second-phase and fourth-phase vertical transfer pulses φV2 and φV4 that do not include the read pulse φROP, similarly to the wiring 33 side. ing. Therefore, the same effects as the first-phase and third-phase vertical transfer pulses φV1 and φV3 can be obtained for the vertical transfer pulses φV2 and φV4.

  As described above, according to the first embodiment, the rise characteristic tr of the read pulse φROP is made steep and the fall characteristics tf of the vertical transfer pulses φV1 to φV4 without changing on the driver side outside the chip. It is possible to achieve both of the above. As a result, the signal charge transfer performance of the vertical transfer unit 14 can be improved while maintaining the signal charge read performance of the read gate unit 13.

<Configuration Example 1 of Diode>
By the way, when the diodes 411 and 421 are mounted on the semiconductor substrate 18, there is a concern that hot carriers are generated from the PN junction. Therefore, when mounting the diodes 411 and 421 on the semiconductor substrate 18, it is preferable that the diodes 411 and 421 are surrounded by a well.

  Specifically, as shown in FIG. 6, for example, a P-type well 19 is formed in a surface layer portion of an N-type semiconductor substrate 18, and diodes 411 and 421 are formed in the well 19. An appropriate bias voltage, for example, a negative voltage of −7.5 V is applied to the well 19.

  By adopting the structure of Configuration Example 1, it is possible to suppress generation of unnecessary substrate current when the diodes 411 and 421 are mounted on the semiconductor substrate 18.

<Example 2 of diode configuration>
FIG. 7 is a cross-sectional view showing the structure of Configuration Example 2 of the diodes 411 and 421. In this configuration example 2, a structure in which the diodes 411 and 421 are made of polysilicon (Poly Si) is adopted. Specifically, as shown in FIG. 7, P-type and N-type regions are provided on a polysilicon electrode by using ion implantation or the like to form a PN junction, and the PN junction is used as diodes 411 and 421.

(Example 2)
FIG. 8 is a circuit diagram illustrating the configuration of the pulse transmission unit according to the second embodiment. In FIG. 8, the same parts as those in FIG. 4 are denoted by the same reference numerals.

  Here, the pulse transmission units on the first phase and third phase vertical transfer pulses φV1 and φV3 side will be described as a representative, but the second phase and fourth phase vertical transfer pulses φV2 and φV4 side pulse transmission units are also described. It becomes the same composition. Further, the pulse transmission units of the vertical transfer pulses φV1 to φV4 are provided independently of each other.

  The pulse transmission unit according to the second embodiment includes a first transmission path 43 having a resistance element 431 made of polysilicon, for example, and a second transmission path 44 having a P-channel MOS transistor 441. The resistance element 431 is inserted in the middle of the wiring 33 extending from the pad 31 to the first-phase / third-phase transfer electrode of the vertical transfer unit 14.

  The P channel MOS transistor 441 has a predetermined threshold voltage, for example, a threshold voltage Vth in the vicinity of 0 V, and is connected in parallel to the resistance element 431 so that the source electrode is on the pad 31 side. The gate electrode of the MOS transistor 441 is grounded, for example, to the ground GND. Alternatively, 0 V may be applied to the gate electrode of the MOS transistor 441.

  In the pulse transmission unit according to the second embodiment having the above-described configuration, first, a circuit operation when a read pulse φROP is applied to the pad 31 will be described. As described above, the read pulse φROP is a positive voltage pulse. Therefore, at the moment when the read pulse φROP is applied to the pad 31 and the read pulse φROP rises from 0V to 13V, the gate-source of the P-channel MOS transistor 441 on the second transmission path 44 side becomes negatively biased. The MOS transistor 441 becomes conductive.

  At this time, the resistance value of the pulse transmission unit composed of the first and second transmission lines 43 and 44 is a parallel combined resistance value of the on-resistance value of the P-channel MOS transistor 441 and the resistance value of the resistance element (polysilicon resistor) 431. It becomes. Here, if the on-resistance value of the MOS transistor 441 is set to be extremely small compared to the resistance value of the resistance element 431, the pulse transmission unit composed of the first and second transmission lines 43 and 44 has no resistance component. Is equivalent to

  The wiring system and transfer electrode are charged by the read pulse φROP applied to the pad 31 as shown in FIG. 9A. The first and second transmission lines 43 have a resistance value extremely smaller than that of the resistance element 431. , 44 through parallel circuits. Since the on-resistance value of the MOS transistor 441 is extremely smaller than the resistance value of the resistance element 431, it can be understood that the read pulse φROP is transmitted through the second transmission path 44. At this time, since the resistance value of the transmission path of the read pulse φROP is smaller than the resistance value of the resistance element 431, the rising characteristic tr of the read pulse φROP is as steep as when applied to the pad 31.

  Next, the circuit operation when the vertical transfer pulse φV1 / φV3 is applied to the pad 31 will be described. The vertical transfer pulses φV1 / φV3 are negative voltage pulses. Therefore, when the vertical transfer pulse φV1 / φV3 is applied to the pad 31 and the vertical transfer pulse φV1 / φV3 falls from 0V to −7.5V, the gate of the P-channel MOS transistor 441 on the second transmission path 44 side. Since the source is positively biased, the MOS transistor 441 is turned off.

  Thus, the vertical transfer pulses φV1 / φV3 are transmitted through the first transmission path 43 including the resistance element 431 as shown in FIG. 9B. That is, the transfer electrode and the wiring system are charged through the first transmission path 43 by the vertical transfer pulses φV1 / φV3 applied to the pad 31. At this time, since the resistance element 431 is inserted into the first transmission path 43, the falling characteristic tf of the vertical transfer pulse φV1 / φV3 passing through the resistance element 431 is applied from the time when the pad 31 is applied. Will also be moderate.

  As described above, according to the second embodiment, the rising characteristic tr of the read pulse φROP is made steep and the falling characteristics tf of the vertical transfer pulses φV1 to φV4 without changing on the driver side outside the chip. It is possible to achieve both of the above. As a result, the signal charge transfer performance of the vertical transfer unit 14 can be improved while maintaining the signal charge read performance of the read gate unit 13.

(Example 3)
FIG. 10 is a circuit diagram illustrating the configuration of the pulse transmission unit according to the third embodiment. In FIG. 10, the same parts as those in FIG.

  As shown in FIG. 10, in the third embodiment, a pad 31A to which a first-phase / third-phase vertical transfer pulse φV1 / φV3 is applied and a pad 31B to which a read pulse φROP is applied are provided independently. It has been. Then, the first transmission path 45 including the resistance element 451 is inserted between the wiring 33 reaching the first-phase / third-phase transfer electrode of the vertical transfer unit 14 and the pad 31A, and between the wiring 33 and the pad 31B. A second transmission line 46 composed of a wiring 461 is inserted in the cable. A transmission path 47 including a resistance element 471 is inserted between the wiring 34 reaching the second-phase / fourth-phase transfer electrode of the vertical transfer unit 14 and the pad 32.

  That is, in the third embodiment, the first-phase / third-phase transfer electrodes and the wiring system of the vertical transfer unit 14 are charged by the first-phase / third-phase vertical transfer pulses φV1 / φV3 applied to the pad 31A. This is performed through the first transmission line 45 including the resistance element 451. In addition, charging of the second and fourth phase transfer electrodes and the wiring system of the vertical transfer unit 14 by the second and fourth phase vertical transfer pulses φV2 / φV4 applied to the pad 32 includes the resistance element 471. This is performed through the transmission line 47.

  Here, a resistance element 451 is provided in the transmission path 45 of the vertical transfer pulses φV1 / φV3, and a resistance element 471 is provided in the transmission path 47 of the vertical transfer pulses φV2 / φV4, and the vertical transfer pulses φV1 to φV4 Since the falling characteristic tf is determined by the time constant of the transmission line 45/47 including the resistance elements 451/471, the waveform becomes dull. That is, the falling characteristics tf of the vertical transfer pulses φV1 to φV4 become gentler than when applied to the pads 31A and 32.

  On the other hand, charging of the first-phase / third-phase transfer electrodes and the wiring system of the vertical transfer unit 14 by the read pulse φROP applied to the pad 31B is performed through the second transmission path 46 including the wiring 461. Here, the resistance value of the second transmission path 46 includes only the wiring resistance of the wiring 461, and is extremely smaller than that of the first transmission path 45 including the resistance element 451. Therefore, the rising characteristic (waveform) tr of the read pulse φROP transmitted through the second transmission path 46 is steep, similar to the waveform when applied to the pad 31B.

  As described above, according to the third embodiment, the rise characteristic tr of the read pulse φROP is made steep and the fall characteristics tf of the vertical transfer pulses φV1 to φV4 without changing on the driver side outside the chip. It is possible to achieve both of the above. As a result, the signal charge transfer performance of the vertical transfer unit 14 can be improved while maintaining the signal charge read performance of the read gate unit 13.

  In particular, the read pulse φROP is inputted into the chip independently of the first-phase and third-phase vertical transfer pulses φV1 and φV3, and transmitted through the first and second transmission lines 45 and 46, respectively. Thus, the following effects can be obtained. That is, it is possible to moderate only the falling characteristics tf of the vertical transfer pulses φV1 to φV4 while maintaining the rising characteristics tr / falling characteristics tf of the read pulse φROP set on the driver side outside the chip.

[Modification]
The present invention is not limited to application to a CCD solid-state imaging device, and can be applied to all solid-state imaging devices having a charge transfer portion in which a transfer electrode of a specific phase also serves as a gate electrode of a readout gate portion. Note that the solid-state imaging device may be formed as a single chip, or may be in a modular form having an imaging function in which an imaging unit and a signal processing unit or an optical system are packaged together. Good.

  Further, the present invention is not limited to application to a solid-state imaging device, and can also be applied to an imaging device that uses the solid-state imaging device as an imaging device. Here, the imaging apparatus refers to a camera system such as a digital still camera or a video camera, or an electronic device having an imaging function such as a mobile phone. Note that the above-described module form mounted on an electronic device, that is, a camera module may be used as an imaging device.

[Imaging device]
FIG. 11 is a block diagram showing an example of the configuration of the imaging apparatus according to the present invention. As shown in FIG. 11, an imaging apparatus 100 according to the present invention includes an optical system including a lens group 101 and the like, an imaging element 102, a DSP circuit 103 which is a camera signal processing circuit, a frame memory 104, a display apparatus 105, and a recording apparatus 106. The operation system 107 and the power supply system 108 are included. The DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, the operation system 107, and the power supply system 108 are connected to each other via a bus line 109.

  The lens group 101 captures incident light (image light) from a subject and forms an image on the imaging surface of the imaging element 102. The imaging element 102 converts the amount of incident light imaged on the imaging surface by the lens group 101 into an electrical signal in units of pixels and outputs the electrical signal. As the imaging element 102, the CCD solid-state imaging device according to the above-described embodiment is used.

  The display device 105 includes a panel type display device such as a liquid crystal display device or an organic EL (electroluminescence) display device, and displays a moving image or a still image captured by the image sensor 102. The recording device 106 records a moving image or a still image captured by the image sensor 102 on a recording medium such as a video tape or a DVD (Digital Versatile Disk).

  The operation system 107 issues operation commands for various functions of the imaging apparatus under operation by the user. The power supply system 108 appropriately supplies various power supplies serving as operation power supplies for the DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, and the operation system 107 to these supply targets.

It is a schematic block diagram which shows an example of the CCD solid-state imaging device to which this invention is applied. 4 is a timing chart showing a timing relationship between four-phase vertical transfer pulses φV1 to φV4 and a read pulse φROP. It is a figure which shows the general wiring structure between a pad and the transfer electrode of a transfer part. FIG. 3 is a circuit diagram illustrating a configuration of a pulse transmission unit according to the first embodiment. FIG. 6 is a waveform diagram for explaining an operation of the pulse transmission unit according to the first embodiment. It is sectional drawing which shows the structure of the structural example 1 of a diode. It is sectional drawing which shows the structure of the structural example 2 of a diode. FIG. 6 is a circuit diagram illustrating a configuration of a pulse transmission unit according to a second embodiment. FIG. 6 is an operation explanatory diagram of a pulse transmission unit according to the second embodiment. It is a circuit diagram which shows the structure of the pulse transmission part which concerns on an Example. It is a block diagram which shows an example of a structure of the imaging device which concerns on this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... CCD solid-state imaging device, 11 ... Imaging part, 12 ... Sensor part, 13 ... Read-out gate part, 14 ... Vertical transfer part, 15 ... Unit cell, 16 ... Horizontal transfer part, 17 ... Charge voltage conversion part, 18 ... Semiconductor Substrate, 21 ... timing control circuit, 22 ... CCD drive circuit, 23 ... shutter drive circuit, 31, 31A, 31B, 32 ... pad, 33, 34 ... wiring, 41, 43, 45 ... first transmission path, 42, 44 46 second transmission line

Claims (8)

A sensor unit that performs photoelectric conversion;
A read gate unit for reading out signal charges accumulated in the sensor unit;
A charge transfer unit that transfers the signal charge read by the read gate unit, and a transfer electrode of a specific phase also serves as the gate electrode of the read gate unit;
On the substrate on which the sensor unit, the read gate unit, and the charge transfer unit are formed, a transfer pulse that drives the transfer electrode and the read gate provided in the middle of the wiring connected to the transfer electrode that also serves as the gate electrode A pulse transmission unit for transmitting a readout pulse for driving the unit,
The pulse transmission unit is
A first transmission path including a resistance element and transmitting the transfer pulse to the transfer electrode;
A solid-state imaging device comprising: a second transmission path having a resistance value lower than that of the first transmission path and transmitting the readout pulse to the readout gate unit. The read pulse is a positive voltage pulse, the transfer pulse is a negative voltage pulse,
The first transmission line includes a diode connected in series with the resistance element so that a side on which the transfer pulse is input becomes a cathode electrode,
The solid-state imaging device according to claim 1, wherein the second transmission path includes a diode provided so that a side to which the readout pulse is input becomes an anode electrode. The solid-state imaging device according to claim 2, wherein the diodes of the first and second transmission lines are formed in a well formed in the substrate. The solid-state imaging device according to claim 2, wherein the diodes of the first and second transmission lines are formed on a polysilicon electrode provided on the substrate. The read pulse is a positive voltage pulse, the transfer pulse is a negative voltage pulse,
2. The solid-state imaging device according to claim 1, wherein the second transmission path includes a P-channel MOS transistor connected in parallel to the resistance element so that a side on which the readout pulse is input becomes a source electrode. The solid-state imaging device according to claim 1, wherein the transfer pulse and the readout pulse are independently input to the first transmission path and the second transmission path. A sensor unit that performs photoelectric conversion;
A read gate unit for reading out signal charges accumulated in the sensor unit;
A charge transfer unit that transfers the signal charge read by the read gate unit, and a transfer electrode of a specific phase also serves as the gate electrode of the read gate unit;
On the substrate on which the sensor unit, the read gate unit, and the charge transfer unit are formed, a transfer pulse that drives the transfer electrode and the read gate provided in the middle of the wiring connected to the transfer electrode that also serves as the gate electrode In driving the solid-state imaging device including a pulse transmission unit that transmits a readout pulse that drives the unit, in the pulse transmission unit,
Transmitting the transfer pulse to the transfer electrode by a first transmission line including a resistive element;
A method of driving a solid-state imaging device, wherein the readout pulse is transmitted to the readout gate unit through a second transmission path having a resistance value lower than that of the first transmission path. A sensor unit that performs photoelectric conversion;
A read gate unit for reading out signal charges accumulated in the sensor unit;
A charge transfer unit that transfers the signal charge read by the read gate unit, and a transfer electrode of a specific phase also serves as the gate electrode of the read gate unit;
On the substrate on which the sensor unit, the read gate unit, and the charge transfer unit are formed, a transfer pulse that drives the transfer electrode and the read gate provided in the middle of the wiring connected to the transfer electrode that also serves as the gate electrode A pulse transmission unit for transmitting a readout pulse for driving the unit,
The pulse transmission unit is
A first transmission path including a resistance element and transmitting the transfer pulse to the transfer electrode;
An imaging apparatus using a solid-state imaging apparatus, having a second transmission path having a resistance value lower than that of the first transmission path and transmitting the readout pulse to the readout gate unit.

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