JPH09307817A - Driver circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the need for a power supply voltage with different polarity by using only a power supply voltage of positive or negative voltage polarity so as to convert an input pulse signal into a pulse signal with different polarity from that of the power supply voltage. SOLUTION: An amplitude conversion circuit 5 uses an intermediate voltage VL from a voltage division circuit 9 to convert timing pulse signals V1 -V4 into signals V1m -V4m with a prescribed amplitude, the signals Vim , V3m are given to a clamp/pulse synthesis circuit 8 and the signals V2m , V4m are given to a clamp circuit 7. Furthermore, an amplitude conversion circuit 6 uses a positive voltage VH from a power supply circuit to convert a timing signal TG into a signal TGm with a prescribed amplitude and given to the clamp/pulse synthesis circuit 8. The outputs of the clamp circuit 7 are pulse voltage signals ϕV2 , ϕV4 exclusively for vertical CCD drive and the outputs of the clamp/pulse synthesis circuit 8 are pulse voltage signals ϕV1 , ϕV3 for driving the read and vertical CCD.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driver circuit for generating a multi-valued pulse signal and a method for generating a multi-valued pulse signal, and more particularly to a driver circuit for operating a CCD type solid-state imaging device and driving of the CCD type solid-state imaging device. The present invention relates to a method for generating a pulse signal for use.

[0002]

2. Description of the Related Art A CCD (Charge Coupled Dev) is used as a solid-state image sensor used in various camera systems such as video cameras, surveillance cameras, doorphone cameras, in-vehicle cameras, TV phone cameras, and multimedia cameras.
Ice) type solid-state imaging devices are widely used. FIG. 1 shows the configuration of a conventional general CCD type solid-state imaging device 100. As shown in FIG. 1, the charges photoelectrically converted by the photodiode 101 of the light receiving portion are first transferred to the vertical CCD 102 at once. The charges of the vertical CCDs 102 are transferred to the horizontal CCDs 103 row by row in accordance with the four-phase pulse voltage signals applied to the terminals v _{1 to} v ₄ . Horizontal C
The charges transferred to the CD 103 are supplied to the horizontal CCD 10 according to the two-phase pulse voltage signals applied to the terminals h ₁ and h _2.
3 are sequentially transferred and output as a video signal.

FIG. 2 shows an example of four-phase pulse voltage signals φV _{1 to} φV ₄ for driving the vertical CCD 102. As shown in FIG. 2, φV ₂ and φV ₄ are negative levels (−
_VL ) and 0 level (0 potential), and φV ₁ and φV ₃ are positive level (V _H ), negative level (−V _L ), and intermediate level (0 potential). It is a three-valued voltage signal. Typically, the value of -V _L and V _H, respectively, is set to about -10V and 15V. The intermediate level is from the photodiode 101 to the vertical CCD 10.
Threshold voltage (0 to 1
V) can be selected, but 0 potential is often selected because of the simplicity of system design.

The transfer of charges in the vertical CCD 102 is usually performed by applying pulse voltages of negative level and 0 level to each gate of the vertical CCD. That is, as shown in FIG. 2, pulse voltage signals φV _{1 to} φ
A negative level at V ₄ (-V _L) and 0 level (zero potential)
The electric charge in the vertical CCD 102 is transferred by the signal portion of (2) (transfer period). In addition, the photodiode 1
The charge transfer from 01 to the vertical CCD 102 is performed by applying a positive level pulse voltage to the read gate. That is, as shown in FIG. 2, the photoelectrically converted charges are read out from the photodiode 101 by the positive level (V _H ) pulse of the pulse voltage signals φV ₁ and φV ₃ (readout period). As described above, the pulse voltage signals φV ₂ and φV ₄ are supplied to the vertical CCD 102.
The pulse voltage signals φV ₁ and φV ₃ are drive signals that contribute only to the transfer of the electric charges in the vertical CCD 102 and the photoelectric conversion of the charges in the vertical CCD 102.

The reason why charges in the vertical CCD 102 are transferred by a negative voltage is as follows. Since the threshold voltage of the read gate is about 0 to 1V, when the charge transfer is performed at a voltage of 0V or higher, the charge accumulated in the photodiode 101 during the charge transfer in the vertical CCD is transferred to the vertical CCD 102. It will leak out. Therefore, it is possible to prevent the charge from leaking from the read gate by transferring the charge by the negative voltage signal. Also,
Another reason is that by accumulating holes (pinning state) in the boundary surface between the bulk (semiconductor layer) and the oxide film in the vertical CCD 102, the dark current generated near the boundary between the bulk and the oxide film is eliminated. Vertical CC to suppress
This is because the voltage applied to D102 needs to be a negative voltage.

As shown in FIG. 3, the CCD type image pickup device 100 is driven by a driver circuit 120 which applies pulse voltage signals φV _{1 to} φV ₄ (see, for example, Japanese Patent Laid-Open _No. 5-58).
No. 103272). The driver circuit 120 uses the DC voltage corresponding to the levels V _H and −V _L supplied from the power supply circuit 160 to generate the timing circuit 14 of the peripheral IC.
Timing pulse signal given from 0 (usually 0V to 5
The pulse voltage signals φV _{1 to} φV ₄ having a predetermined voltage level are generated from the (V drive) and applied to the CCD image pickup device 100.

The timing circuit 140 generates timing pulse signals V _{1 to} V ₄ for driving the vertical CCD and a timing pulse signal TG for reading. FIG. 4 shows an example of the timing pulse signal. As can be seen from FIG. 4, the timing pulse signal TG is at a high (H) level (5V) only during the period for reading out the charges from the photodiode 101, and during the period for transferring the charges in the vertical CCD 102 is at the low (L) level (0V). ). The timing pulse signals V _{1 to} V ₄ have pulses of different phases during the charge transfer period.

Since the voltage level of the timing pulse signal is normally a logic level of 0V to 5V, the driver circuit 12
0 (called a V driver) allows the vertical CCD 10
2 is converted into pulse voltage signals φV _{1 to} φV ₄ for driving having a voltage level required for driving 2. As can be seen from FIGS. 2 and 4, the timing pulse signals V _{1 to} V ₄ correspond to the pulse voltage signals φV _{1 to} φV ₄ , respectively, and the read pulse (H level) of the timing pulse signal TG is It is carried by the positive level pulse (V _H ) of the pulse voltage signals φV ₁ and φV ₃ . Like this, two of five
Timing pulse signals V ₁ ~V ₄ value, a pulse voltage signal .phi.V ₁ and .phi.V ₃ of two ternary, it is converted into a pulse voltage signal of the two binary .phi.V ₂ and .phi.V _4.

FIG. 5 shows an example of the configuration of a conventional driver circuit 120. As shown in FIG. 5, the driver circuit 120 includes a clamp circuit 121, a first amplitude conversion circuit 122, a second amplitude conversion circuit 124, and a pulse synthesis circuit 123. Negative power supply voltage from the power supply circuit 160 (-V _L) is supplied to the clamp circuit 121. and the first amplitude converter 122, a positive supply voltage (V _H) from the power supply circuit 160 and the second amplitude conversion It is supplied to the circuit 124.

The timing pulse signals V _{1 to} V ₄ input to the driver circuit 120 are respectively supplied to the clamp circuit 12.
By 1 and the first amplitude converting circuit 122, it is converted into a signal V _{1 m} ~V _4m having a predetermined amplitude (-V _L ~0).
The timing pulse signal TG is supplied to the second amplitude conversion circuit 12
4, the signal TG _m having a predetermined amplitude (0 to V _H )
Is converted into the pulse synthesis circuit 123 and is given to the pulse synthesis circuit 123.

Amplitude-converted timing pulse signal V _2m
And V _4m are the pulse voltage signals φV ₂ and φV _{4 as they are.}
Is output as The amplitude-converted timing pulse signals V _1m and V _3m are further subjected to a positive level pulse (V _H ) corresponding to the read period in the pulse synthesizing circuit 123.
Are added and output as pulse voltage signals φV ₁ and φV ₃ . FIG. 6 shows a timing signal V _1m
V _4m and TG _m are shown.

FIG. 7 shows a concrete configuration example of the clamp circuit 121 and the first amplitude conversion circuit 122. Figure 7
The clamp circuit 121 shown in is a diode clamp circuit having a capacitor C and a diode 131. The anode of the diode 131 has 1
The negative voltage (-V _L) is applied from 60. The clamp circuit 121 is a timing pulse signal input to the input line 130a (V ₂ and V ₄ are shown in FIG. 7).
The AC component (amplitude 5V) of is transmitted by the capacitor C. Further, the direct current component outputted from the clamping circuit 121 is determined by the cathode potential of the diode 131 is stabilized becomes higher potential than the anode potential (-V _L). Therefore, the signal on output line 130b is
As shown in FIG. 7, a binary signal level _{-V L ~ (-V L +5)} .

Strictly speaking, the potential on the cathode side is stable at a potential higher than the potential on the anode side minus the drop potential of the diode, but since the drop potential is about 0.5 V, the drop potential is ignored for simplicity. I will think about it.

The first amplitude conversion circuit 122 is the power supply circuit 1
60 consists of two connected stages of CMOS inverters between the negative power supply voltage applied (-V _L) and a ground voltage (0V) from. The signal output from the clamp circuit 121 is
The pulse is inverted by the first-stage CMOS inverter of the first amplitude conversion circuit 122, and the pulse amplitude is −
The pulse signal is amplified so that it becomes V _L ˜0, and the pulse is inverted again by the second-stage inverter and output as a pulse signal whose amplitude is amplified (−V _L ˜0) (in FIG. 7, V _L ). _2m and V _4m are shown). The amplitude-converted timing signals V _2m and V _4m are directly output as pulse voltage signals φV ₂ and φV ₄ and used for driving the vertical CCD 102.

FIG. 8 shows a specific configuration example of the second amplitude converting circuit 124 and the pulse synthesizing circuit 123. The configurations and operations of the clamp circuit 121 and the first amplitude conversion circuit 122 are as described in FIG. The timing pulse signals V ₁ and V ₃ are amplitude-converted by the clamp circuit 121 and the first amplitude conversion circuit 122 and output to the pulse synthesizing circuit 123 as timing signals V _1m and V _3m .

The second amplitude conversion circuit 124 is the power supply circuit 1
It is composed of a two-stage CMOS inverter connected between a positive power supply voltage (V _H ) given from 60 and the ground voltage (0 V). The timing signal TG is pulse-inverted by the first-stage CMOS inverter of the second amplitude conversion circuit 124, amplified so that the pulse amplitude becomes 0 to V _H , and further pulsed again by the second-stage inverter. Is inverted and output as a pulse signal TG _m .
The amplitude-converted timing signal TG _m is given to the pulse synthesizing circuit 123.

The pulse synthesizing circuit 123 is a switch / adding circuit for synthesizing the signals (V _1m and V _3m ) from the first amplitude converting circuit 122 and the signal TG _m from the second amplitude converting circuit 124. . As shown in FIG. 8, the pulse synthesizing circuit 123 includes an N-channel MOSFET 133a and a P-channel MOSFET 133a.
It has a channel MOSFET 133b. MOSF
The gate terminal of the ET 133a is the second amplitude conversion circuit 124.
Timing signal T output from the first-stage inverter of
The amplified inverted signal TG _m bar of G is input to the MOSFET
The gate terminal of 133b is grounded.

Therefore, while the timing pulse signal TG is at 0V level (charge transfer period), the MOSFET 133b is turned off by the 0V level timing signal TG _m output from the second amplitude conversion circuit 124, and at the same time, V _H level inverted signal TG _m M by
The OSFET 133a is turned on. As a result, in the charge transfer period, the pulse synthesizing circuit 123 outputs the outputs (amplified timing signals V _1m and V _3m ) from the first amplitude converting circuit 122.

Further, the period timing pulse signal TG is 5V level (reading period), the timing signal T V _H V level output from the second amplitude converter 124
The MOSFET 133b is turned on by G _m and, at the same time, the MOSF is turned on by the inverted signal TG _m bar of 0V level.
ET133a is turned off. As a result, during the read period, the pulse synthesis circuit 123 outputs the amplified timing signal T (amplified timing signal T) from the second amplitude conversion circuit 124.
G _m ) is output.

Thus, according to the timing signal TG,
By selectively outputting the outputs from the first and first amplitude conversion circuits 122 and 124, the amplified timing signals V _1m and V _3m and TG _m are combined, and a pulse voltage for reading and CCD driving is synthesized. It is output as signals φV ₁ and φV ₃ .

[0021]

As described above, in the conventional driver circuit 120, the positive level (V _H ) power supply voltage for charge read and the negative level (-V _L ) power supply voltage for charge transfer are used. And need. Therefore, the power supply circuit 160
Must supply two power supply voltages having different polarities, which complicates the circuit configuration and occupies a large space. Therefore, this is a major obstacle to downsizing and cost reduction of a camera system using a solid-state image sensor. Also,
The problem of supplying two power supply voltages with different polarities is that the CC
The same problem occurs not only in the driver circuit for the D image pickup device but also in the conventional driver circuit that generates a multivalued drive pulse to drive various systems.

The present invention has been made in view of the above circumstances, and an object thereof is to use an input pulse signal as a power supply voltage by using only a power supply voltage of either positive voltage or negative voltage of one polarity. To a pulse signal having a pulse (amplitude peak) having a polarity different from that of the above, to provide a driver circuit that does not separately require a power supply voltage having a polarity different from that of a positive voltage or a negative voltage. It is an object of the present invention to provide a driver circuit that can generate a multi-level drive pulse signal including amplitude peaks of different polarities using only a power supply voltage.

[0023]

A driver circuit of the present invention generates a drive pulse signal having a plurality of levels by using a power supply voltage of a first polarity supplied from a power supply, based on an input timing signal. A driver circuit for generating a first voltage by dividing the power supply voltage, and converting the amplitude of the input timing signal using the first voltage, An amplitude converting means for generating an amplified signal having a peak substantially at the first voltage and the ground voltage, and the ground voltage peak of the amplified signal having a second polarity different from the first polarity. Clamp means for clamping the amplified signal at a predetermined voltage between the ground voltage and the first voltage so as to be shifted to a second voltage, whereby the second signal is provided. Has a peak in voltage Generating a pulse voltage signal having a substantially equal amplitude of the voltage. This achieves the above object.

There may be provided a synthesizing means for synthesizing the pulse voltage signal generated by the clamp means with the third voltage signal to generate a driving pulse voltage signal having three or more levels.

The third voltage signal may be a DC voltage signal having a power supply voltage level of the first polarity supplied from the power supply.

The third voltage signal may be a pulse voltage signal having peaks at the power supply voltage and the ground voltage.

The synthesizing means may include means for switching and outputting the pulse voltage signal generated by the clamp means and the third voltage signal at a predetermined timing.

The power supply voltage supplied from the power supply is used to convert the amplitude of the second input timing signal, and the power supply voltage of the first polarity and the ground voltage have a second peak.
The second amplitude conversion means for generating the amplified signal of 1 may be further provided.

The third voltage signal may be the second amplified signal.

The predetermined voltage clamped by the clamp means may be a ground voltage.

The clamp means may be a diode clamp circuit having a capacitor and a diode.

The method of the present invention is a method of generating a driving pulse voltage signal having a plurality of levels by using a power supply voltage of a first polarity supplied from a power supply based on an input timing signal. The method includes a voltage dividing step of dividing the power supply voltage to generate a first voltage, and converting the amplitude of the input timing signal using the first voltage to substantially reduce the first voltage. And an amplitude conversion step of generating an amplified signal having a peak at the ground voltage, and shifting the ground voltage peak of the amplified signal to a second voltage having a second polarity different from the first polarity. Thus, by clamping the amplified signal at a predetermined voltage between the ground voltage and the first voltage, the second voltage has a peak and the first voltage
And a clamping step for producing a pulsed voltage signal having an amplitude substantially equal to the voltage of the.

The method may include a synthesizing step of synthesizing the third voltage signal with the pulse voltage signal generated in the clamping step to generate a driving pulse voltage signal having three or more levels.

In the synthesizing step, a DC voltage signal supplied from the power supply and having a power supply voltage level of the first polarity may be used as the third voltage signal.

In the combining step, a pulse voltage signal having peaks at the power supply voltage and the ground voltage may be used as the third voltage signal.

The synthesizing step may include a step of switching the pulse voltage signal generated by the clamp means and the third voltage signal at a predetermined timing and outputting the pulse voltage signal.

The amplitude of the second input timing signal is converted by using the power supply voltage of the first polarity supplied from the power supply, and the second amplified signal having the peaks of the power supply voltage and the ground voltage is generated. It may further include a second amplitude conversion step of

In the combining step, the second amplified signal may be used as the third voltage signal.

In the step of clamping, the predetermined voltage may be a ground voltage.

[0040]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A driver circuit according to the present invention will be described below with reference to the drawings using an embodiment of a driver circuit for driving a CCD image pickup device.

FIG. 9 shows a driver circuit 1 according to the present invention as C
The case where it is used to drive the CD-type image sensor 3 is shown. As shown in FIG. 9, the driver circuit 1 includes a power supply circuit 4
DC voltage of positive level (V _H ) is supplied from the
The timing circuit 2 supplies the timing pulse signals V _{1 to} V ₄ for driving the vertical CCD and the timing pulse signal TG for reading. The timing circuit 2 is similar to the conventional timing circuit 140. The driver circuit 1 according to the present invention includes a timing pulse signal (usually 0V to 5V).
Drive), pulse voltage signals φV _{1 to} φV ₄ having a predetermined voltage level are generated by using only the positive level power supply voltage and applied to the CCD image pickup device 3.

(Embodiment 1) FIG. 10 shows the configuration of the driver circuit 1 according to the first embodiment. As shown in FIG. 10, the driver circuit 1 includes a first amplitude conversion circuit 5,
It has a second amplitude conversion circuit 6, a clamp circuit 7, a clamp / pulse synthesizing circuit 8, and a voltage dividing circuit 9. The positive power supply voltage (V _H ) from the power supply circuit 4 is supplied to the second amplitude conversion circuit 6, one terminal of the voltage dividing circuit 9, and the clamp / pulse synthesizing circuit 8. The output (intermediate voltage V _L ) of the voltage dividing circuit 9 is supplied to each amplitude converting circuit 5. The timing pulse signals V _{1 to} V ₄ are input to the corresponding first amplitude conversion circuit 5, and the timing pulse signal TG is input to the second amplitude conversion circuit 6.

Each of the first amplitude conversion circuits 5 uses the intermediate voltage (V _L ) given from the voltage dividing circuit 9 and has timing pulse signals V _{1 to} V ₄ with a predetermined amplitude (0 to V _L ). Signals V _{1m to} V _4m are converted. The amplitude-converted timing signals V _1m and V _3m are input to the clamp / pulse synthesis circuit 8, and the amplitude-converted timing signals V _2m and V _4m are
It is input to the clamp circuit 7.

The second amplitude conversion circuit 6 uses the positive level voltage (V _H ) supplied from the power supply circuit 4 to convert the timing signal TG into a signal TG _m having a predetermined amplitude (0 to V _H ). Convert to. As will be described later, the signal TG _m is a signal obtained by amplifying the amplitude of the timing signal TG and inverting the pulse (that is, low level when the timing signal TG is high level, and low level when the timing signal TG is low level). High level). The amplitude-converted timing signal TG _m is input to the clamp / pulse synthesis circuit 8.

The output of the clamp circuit 7 becomes the pulse voltage signals φV ₂ and φV ₄ dedicated to the vertical CCD drive, and the output of the clamp / pulse combination 8 becomes the pulse voltage signals φV ₁ and φV ₃ of the read and vertical CCD drive. .

As shown in FIG. 10, the voltage dividing circuit 9 has resistors R1 and R2 connected in series, one terminal of which is connected to the positive level power supply voltage (V _H ) and the other of which is connected. The terminal is connected to the ground voltage (0V). An intermediate voltage V _L obtained by resistance-dividing the voltage V _H is output from the connection node of the resistors R ₁ and R ₂ and supplied to the first amplitude conversion circuit 5.

FIG. 11 shows a specific configuration example of the first amplitude conversion circuit 5. The first amplitude conversion circuit 5 includes an intermediate voltage (V _L ) supplied from the voltage dividing circuit 9 and a ground voltage (0
V) with a two-stage CMOS inverter. As shown in FIG. 11, each CMOS inverter is composed of an N-channel MOSFET 50a (50b) and a P-channel MOSFET 50c (50d).

The timing signals V _{1 to} V ₄ input to the first amplitude conversion circuit 5 are pulse-inverted by the first-stage CMOS inverter and are amplified so that the pulse amplitude becomes 0 to _VL , Further, the pulse is inverted again by the second-stage inverter and output as pulse signals V _{1m to} V _4m whose amplitude is amplified to 0 to _VL . The waveforms of the timing signals V _{1 to} V ₄ input to the first amplitude conversion circuit 5 and the amplitude-converted timing signals V _{1m to} V _4m output are as shown in FIG.

FIG. 13 shows a concrete configuration example of the second amplitude conversion circuit 6. The second amplitude conversion circuit 6 includes a two-stage CMOS inverter connected between the positive power supply voltage (V _H ) supplied from the power supply circuit 4 and the ground voltage (0 V). As shown in FIG. 13, each CMOS inverter includes an N-channel MOSFET 60a (60
b) and a P-channel MOSFET 60c (60d).

The timing signal TG input to the second amplitude conversion circuit 6 has its pulse inverted by the CMOS inverter of the first stage and amplified so that the pulse amplitude becomes 0 to V _H , and then the timing signal TG is output from the node 61. The inverted amplified signal TG _m is output. At the same time, the inverted amplified signal TG _m is
Further, the pulse is inverted again by the inverter of the second stage, and the amplified pulse signal T of amplitude 0 to V _H is output from the node 62.
It is output as G _m '. In the present embodiment, FIG.
As shown in, only the inverted amplified signal TG _m is supplied to the clamp / pulse synthesizing circuit 8. The inverted amplified signal T
A case where G _m and the amplified pulse signal TG _m ′ are supplied to the clamp / pulse synthesizing circuit 8 will be described later as a second embodiment.

FIG. 14 shows an example of the configuration of the clamp circuit 7. The clamp circuit 7 shown in FIG. 14 has a capacitor C and a diode 71.
1 is a negative clamp circuit configured such that the current flowing from the output line 70b to the ground voltage side in the first direction is in the forward direction.
The anode of the diode 71 is connected to the output signal line 70b from the capacitor C, and the cathode is grounded (0 level).
Have been. The clamp circuit 7 transmits the AC component (amplitude _VL ) of the amplified pulse signals ( _V2m and _V4m ) input to the input line 70a by the capacitor C. Also,
The DC component output from the clamp circuit 7 is determined when the signal on the output signal line 70b stabilizes at a potential at which the cathode side potential (0 V) of the diode 71 becomes higher than the anode side potential. That is, the signal on output signal line 70b whose anode is connected, since its level is shifted to be less than 0V, the signal on the output line 70b, as shown in FIG. 14, the level -V _L It becomes a binary signal of 0.

As described above, by clamping at the ground voltage, the pulse amplitude (peak to peak) does not change, and the signals V _2m and V having peaks at the ground voltage and the positive voltage are obtained.
From _4m (amplitude level 0 to V _L), a signal having a peak to a negative voltage and a ground voltage (amplitude level -V _L ~0) is generated. The timing signals V _2m and V _4m clamped in this way are directly output as pulse voltage signals φV ₂ and φV ₄ (FIG. 12). For simplification, the drop voltage in the diode 71 is ignored in the description. The same applies to the following description.

The capacitance of the capacitor C of the clamp circuit 7 is
It is preferable that the value is such that the pulse amplitude is not lowered. For example, when a 1/3 inch CCD is used, the capacitance of the capacitor C is suitably 0.1 μF or more. In this case, the vertical CCD has an electrode load capacity of about 3000.
Since the voltage is pF, the voltage applied to the electrodes of the vertical CCD due to the capacitance voltage division with the capacitor C having a capacitance of 0.1 μF is
As shown by the following equation (1), it decreases to about 97.1%. However, if the voltage drops to this extent, there is no practical problem.

[0054]

[Equation 1]

The clamp circuit 7 can be constructed by using other semiconductor elements such as MOSFET in addition to the diode clamp circuit shown in FIG. MOSFET
Can be used as a two-terminal switching element that is turned on when the voltage applied between the source and the drain exceeds a threshold value by short-circuiting the gate terminal and the drain terminal.

For example, as shown in FIG. 15, an N-channel MOSFET 72 may be used instead of the diode 71. In the MOSFET 72, the gate and the drain are connected to the output line 70b, and the source is grounded. Also,
Similarly, FIG. 16 shows an example in which a P-channel MOSFET 73 is used instead of the diode 71. MOS
The gate and drain of the FET 73 are grounded, and the source is connected to the output line 70b. The clamp circuit 7 is
Not limited to these, other peak clamp circuits and other clamp circuits can also be used.

FIG. 17 shows an example of the configuration of the clamp / pulse synthesizing circuit 8. As shown in FIG. 17, the clamp / pulse synthesizing circuit 8 has a clamp unit 8a and a pulse synthesizing unit 8b.

The clamp section 8a has the same structure as the clamp circuit 7 described in FIG. 14, and is a negative clamp circuit having a capacitor C and a diode 81. However, between the capacitor C and the diode 81, the pulse synthesizing unit 8
The N-channel MOSFET 82c of b is inserted.
The capacitance of the capacitor C of the clamp portion 8a is set to 0.1 μF or more as in the case of the clamp circuit 7.

The pulse synthesizer 8b is a P-channel MOSFET 82a for controlling ON / OFF of the connection between the positive level (V _H ) power supply voltage and the output line 80b, and the clamp unit 8b.
N-channel MOSF for ON / OFF controlling the connection between the cathode of the diode 81 of a and the ground voltage (0V)
It has an ET 82b and an N-channel MOSFET 82c that controls ON / OFF of the connection between the capacitor C of the clamp portion 8a and the output line 80b.

The gate terminals of the three MOSFETs 82a to 82c are connected to the node 61 of the second amplitude amplifier circuit 6, respectively.
The inverted amplified signal TG _m output from is input. Therefore, as shown in FIG. 12, the inverted amplified signal TG _m is at the high level (V _H ) during the transfer period when the timing signal TG is at the low level (0 V).
ET82a is in OFF state, NMOSFETs 82b and 8
2c is turned on. Therefore, during the transfer period,
The clamp section 8a is in the same connection state as the clamp circuit 7 described above, and the clamp / pulse synthesizing circuit 8 performs the same operation as the clamp circuit 7.

During the transfer period, the clamp section 8a transmits the AC component (amplitude V _L ) of the amplified pulse signals (V _1m and V _3m ) input to the input line 80a by the capacitor C and the DC component by the diode. Clamp by 81. Thus, the signal on the output line 80b in the transfer period is a binary signal level -V _L ~0.

In addition, in the read period when the timing signal TG is at high level (5V), the inverted amplified signal T
Since G _m is made the low level (0V), PMOSFET
82a is turned on, and NMOSFETs 82b and 82c are turned off. Therefore, in the read period,
The power supply voltage (V _H ) is output via the output line 80b.

[0063] Thus, as from the clamp / pulse synthesizing circuit 8, shown in FIG. 12, the low level (-V _L),
Three-valued pulse voltage signals φV ₁ and φV ₃ having an intermediate value (0 V) and a high level (V _H ) are output.

As in the case of the clamp circuit 7, the clamp portion 8a can be configured by using other semiconductor elements such as MOSFET in addition to the clamp circuit using the diode shown in FIG. For example, as shown in FIG.
Instead of the diode 81, a P-channel MOSFET 83
May be used. In the PMOSFET 83, the gate and the drain are grounded via the NMOSFET 82b, and the source is connected to the output line 80b. In addition, FIG.
N-channel MOSFET 84 instead of diode 81
Shows an example using. In the NMOSFET 84, the gate and drain are connected to the output line 80b, and the source is N
It is grounded through the MOSFET 82b. The clamp circuit 8a is not limited to these examples, but other peak clamp circuits or other clamp circuits can be used.

Next, a concrete design example of each element in the clamp / pulse synthesizing circuit 8 will be described. The capacitance of the capacitor C of the clamp portion 8a is 0.1 μm as described above.
It is sufficient if it is about F or more. The capacitor C has a relatively large capacitance, but the driver circuit 1 according to the present embodiment is used.
In the case of integrating the same, or in the case of integrating with the CCD image pickup device 3 as described later, the capacitor C is also formed on the same substrate by utilizing the thin film technology of the high dielectric material and the insulating film. It is possible. However,
The capacitor C having a relatively large capacity may have an external configuration.

MOSFETs 82a to 82a of the pulse synthesizing unit 8b
The transistor used for 82c needs to drive the transfer electrode load capacitance of several thousand pF in the vertical CCD in a short time, so that the conductance value of the transistor needs to be designed large.

Here, gate width: W, gate length: L, channel mobility: μ, gate capacitance per unit area:
Assuming C ₀ , the voltage between the gate and source terminals: V _GS , and the threshold voltage: V _th , the transconductance g _m of the transistor in the saturation region is represented by the following formula (2).

[0068]

[Equation 2]

Therefore, the transconductance g _m can be increased by increasing the design size (gate width W / gate length L) of the transistor.

For example, C used in a video camera, for example
In the case of a CD image pickup device, in order to drive the vertical CCD according to the TV standard, it is necessary to set the time constant τ of rising and falling of the pulse to about 100 ns. Time constant τ
Is represented by the following equation (3).

[0071]

(Equation 3)

In the case of the 1 / 3-type CCD as in the above-mentioned example, since the electrode load capacitance C _L of the vertical CCD is about 3000 pF, g _m = 30 _m mho. Where the gate −
Difference between source terminal voltage V _GS and threshold voltage V _th (V _GS
-V _th): 5V, the thickness of the gate oxide film: 800 Å assuming calculate the gate capacitance C _0, N-channel MOSFET
Mobility μ _N : 600 cm ² / VS, P-channel MOSF
Assuming that ET mobility μ _{P is} 200 cm ² / VS, the design dimension (W / L) of the P-channel MOSFET 82a is about 700, and the N-channel MOSFET 8 is calculated from the above equation (2).
For 2b and 82c it is about 230.

Next, another configuration example of the clamp / pulse synthesizing circuit 8 will be described. FIG. 20 shows the pulse synthesizer 8b.
To the P-channel MOSFET 82a and the N-channel MO.
An example of the clamp / pulse synthesizing circuit 8 configured by using the SFET 82d is shown.

As shown in FIG. 20, the clamp portion 8a
Is a negative clamp circuit having the same configuration as the clamp circuit 7 described in FIG. 14 and having a capacitor C and a diode 81. The output line 80b of the clamp section 8a is connected to the source terminal of the NMOSFET 82d of the pulse synthesizing section 8b. The capacitance of the capacitor C of the clamp portion 8a is set to 0.1 μF or more as in the case of the clamp circuit 7.

In the pulse synthesizer 8b, the source terminal of the P-channel MOSFET 82a is connected to the positive level (V _H ) power supply voltage. P-channel MOSFET 8
The drain terminals of 2a and the N-channel MOSFET 82d are both connected to the output line 80c. P channel M
The inverted amplified signal TG _m output from the node 61 of the second amplitude amplifier circuit 6 is input to the gate terminals of the OSFET 82a and the N-channel MOSFET 82d.

Therefore, during the transfer period when the inverted amplified signal TG _m is at the high level (V _H ), the PMOSFET 8 is
2a is in the OFF state and NMOSFET 82d is in the ON state, so the output line 80c of the clamp / pulse conversion circuit 8 is
, The signal on the output line 80b of the clamp unit 8a is output to. During the transfer period, the clamp unit 8a, like the clamp circuit 7, receives the AC component (amplitude level 0) of the amplified pulse signals (V _1m and V _3m ) input to the input line 80a.
~V _L) transmitted by the capacitor C, and clamped by diodes 81 a direct current component. Thus, the signal on the output line 80c in the transfer period level -V 2 of the _L ~0
Value signal.

In the read period when the inverted amplified signal TG _m is at low level (0 V), the PMOS FE
Since T82a is in the ON state and NMOSFET 82d is in the OFF state, the power supply voltage (V _H ) is output via the output line 80c.

[0078] Thus, as from the clamp / pulse synthesizing circuit 8, shown in FIG. 12, the low level (-V _L),
Three-valued pulse voltage signals φV ₁ and φV ₃ having an intermediate value (0 V) and a high level (V _H ) are output.

Even in the above example, the clamp portion 8a is
Similar to the case of the clamp circuit 7, in addition to the clamp circuit using the diode as shown in FIG. 20, another semiconductor element such as MOSFET may be used. For example, as shown in FIG. 21, instead of the diode 81, P
A channel MOSFET 83 may be used. PMOS
The gate and drain of the FET 83 are grounded, and the source is connected to the output line 80b. Further, FIG. 22 shows an example in which an N-channel MOSFET 84 is used instead of the diode 81. The NMOSFET 84 has its gate and drain connected to the output line 80b, and its source grounded. The clamp circuit 8a is not limited to these examples, but other peak clamp circuits or other clamp circuits can be used.

As described above, the driver circuit 1 of this embodiment
According to, by clamping the input pulse signal (timing signal) after amplitude conversion, only the positive level of the supply voltage (V _H) by using the voltage circuit 4 for supplying a negative voltage level (-V _L) Binary pulse voltage signal (φV ₂
And φV ₄ ) can be generated. From the positive level power supply voltage (V _H ) to the intermediate voltage (V _L ) using the voltage dividing circuit 9.
By generating a power supply voltage and can obtain a different negative voltage absolute value (-V _L).

In the present embodiment, the clamp circuit 7 and the clamp section 8a of the clamp / pulse synthesizing circuit 8 are clamped by the ground voltage (0V). However, the voltage to clamp is not limited to this, and the ground voltage and
It is possible to freely select between the intermediate voltage obtained by the voltage dividing circuit 9 and the intermediate voltage. For example, if the clamp voltage is V _c (0 <V _c
<When set to V _L), the amplitude peaks pulse signal 0 to V _L, the amplitude peaks - is (V _L -V _c) shift so that the pulse signal ~V _c.

Further, the binary pulse voltage signal having the negative voltage level thus obtained is combined with the signal having the positive level (that is, switched and output at a predetermined timing) to obtain the negative voltage level. (For example −
V _L ), an intermediate value (eg 0 V), and a ternary pulse voltage signal (φV ₁ and φ) having a positive voltage level (eg V _H ).
V ₃ ) can be generated. As described above, when the clamp voltage is set to V _c , the negative voltage level (V _c −
It is possible to obtain a ternary pulsed voltage signal having a V _L ), an intermediate value (V _c ), and a positive voltage level (eg V _H ).

In the present embodiment, the case where the positive level DC voltage (V _H ) is combined has been described, but it is also possible to combine a binary signal having a positive level or more (for example, a binary pulse signal). . As described above, the pulse voltage signal to be combined is not limited to the three values, and it is possible to generate a pulse voltage signal having a desired multilevel level by performing clamping and pulse combination.

In this embodiment, 1 for generating a positive voltage is used.
Although the driver circuit for generating a multi-valued pulse voltage signal including a negative voltage level has been described using the power supply circuit of the system, the present invention is not limited to this. According to the present invention, similarly, it is also possible to generate a multi-valued pulse voltage signal including a positive voltage level by using only one system of power supply circuit that generates a negative voltage. As described above, according to the present invention, it is possible to generate a pulse voltage signal of a desired multi-valued level including a positive level and a negative level by using either one of the positive and negative power supply circuits.

(Embodiment 2) FIG. 23 shows a configuration of a driver circuit 1 according to a second embodiment of the present invention. FIG.
As shown in FIG. 3, the driver circuit 1 has a first amplitude conversion circuit 5, a second amplitude conversion circuit 6, a clamp circuit 7, a clamp / pulse synthesizing circuit 8, and a voltage dividing circuit 9. The positive power supply voltage (V _H ) supplied from the power supply circuit 4 (see FIG. 9) is supplied to one terminal of the second amplitude conversion circuit 6 and the voltage dividing circuit 9. The output (intermediate voltage V _L ) of the voltage dividing circuit 9 is supplied to each amplitude converting circuit 5. The timing pulse signals V _{1 to} V ₄ are input to the corresponding first amplitude conversion circuit 5, and the timing pulse signal TG is input to the second amplitude conversion circuit 6.

Similar to the first embodiment, each first amplitude conversion circuit 5 uses the intermediate voltage (V _L ) given from the voltage dividing circuit 9 and outputs the timing pulse signals V _{1 to} V ₄ to a predetermined amplitude (V _L ). 0
~V _L) into a signal V _{1 m} ~V _4m with. The amplitude-converted timing signals V _1m and V _3m are input to the clamp / pulse synthesis circuit 8, and the amplitude-converted timing signals V _2m and V _4m are input to the clamp circuit 7.

The second amplitude conversion circuit 6 uses the positive level voltage (V _H ) supplied from the power supply circuit 4 and outputs the signal TG _m having a predetermined amplitude (0 to V _H ) from the timing signal TG. And TG _m '. As described in the first embodiment, the signal TG _m is a signal obtained by amplifying the amplitude of the timing signal TG and inverting the pulse (that is, the timing signal TG is at the low level when the timing signal TG is at the high level, and the timing signal TG is at the low level). High level when level). The signal TG _m 'is a signal in which only the amplitude of the timing signal TG is amplified. The amplitude-converted timing signals TG _m and TG _m ′ are input to the clamp / pulse synthesizing circuit 8.

The output of the clamp circuit 7 becomes the pulse voltage signals φV ₂ and φV ₄ dedicated to the vertical CCD drive, and the output of the clamp / pulse combination 8 becomes the pulse voltage signals φV ₁ and φV ₃ of the read and vertical CCD drive. .

As shown in FIG. 23, the voltage dividing circuit 9 has resistors R1 and R2 connected in series, one terminal of which is connected to the positive level power supply voltage (V _H ) and the other of which is connected. The terminal is connected to the ground voltage (0V). An intermediate voltage V _L obtained by resistance-dividing the voltage V _H is output from the connection node of the resistors R ₁ and R ₂ and supplied to the first amplitude conversion circuit 5.

First amplitude conversion circuit 5 and clamp circuit 7
11 and 14 to 16 respectively.
As shown in FIG. The operations of the first amplitude conversion circuit 5 and the clamp circuit 7 are similar to those described in the first embodiment, and therefore the description thereof will not be repeated here. The waveforms of the timing signals V _{1 to} V ₄ input to the first amplitude conversion circuit 5 and the amplitude-converted timing signals V _{1m to} V _4m output are as shown in FIG. 12 as in the first embodiment. is there. Also,
The clamped signals output from the clamp circuit 7, that is, the pulse voltage signals φV ₂ and φV ₄ are also as shown in FIG. In the present embodiment as well, for simplification, the drop voltage in the diode 71 will be ignored and described.

The concrete configuration of the second amplitude conversion circuit 6 is as follows.
Similar to the first embodiment, it is as shown in FIG. The timing signal TG input to the second amplitude conversion circuit 6 has its pulse inverted by the CMOS inverter of the first stage and amplified so that the pulse amplitude becomes 0 to V _H , and then the inverted amplified signal from the node 61. It is output as TG _m . Also,
At the same time, the pulse of the inverted amplified signal TG _m is inverted again by the second-stage inverter, and the inverted amplified signal TG _m is output from the node 62 as an amplified pulse signal TG _m ′ having an amplitude of 0 to V _H. In the present embodiment, as shown in FIG. 23, the inverted amplified signal TG _m and the amplified pulse signal TG _m ′ are supplied to the clamp / pulse synthesizing circuit 8.

FIG. 24 shows an example of the configuration of the clamp / pulse synthesizing circuit 8 according to this embodiment. As shown in FIG. 24, the clamp / pulse synthesizing circuit 8 has a clamp unit 8a and a pulse synthesizing unit 8b. The inverted amplified signal T output from the node 61 of the second amplitude conversion circuit 6
G _m is supplied to the input line 80 d from one terminal, and the amplified pulse signal TG _m ′ output from the node 62 is supplied to the input line 80 e from the other terminal.

The clamp section 8a has the same structure as the clamp circuit 7 described in FIG. 14, and is a negative clamp circuit having a capacitor C and a diode 81. However, between the capacitor C and the diode 81, the pulse synthesizing unit 8
The N-channel MOSFET 82c of b is inserted.
The capacitance of the capacitor C of the clamp portion 8a is set to 0.1 μF or more as in the case of the clamp circuit 7.

The pulse synthesizing unit 8b is a P-channel MOS.
It has an FET 82a, an N-channel MOSFET 82b, and an N-channel MOSFET 82c. The P-channel MOSFET 82a has an input line 80e and an output line 8 to which the amplified pulse signal TG _m '(amplitude level 0 to V _H ) is supplied.
ON / OFF control the connection with 0b. The N-channel MOSFET 82b is the diode 8 of the clamp portion 8a.
Turn on / off the connection between the cathode of 1 and the ground voltage (0V)
OFF control. The N-channel MOSFET 82c controls ON / OFF of the connection between the capacitor C of the clamp portion 8a and the output line 80b.

The gate terminals of the three MOSFETs 82a to 82c are connected to the input line 80d, and
The inverted amplification signal TG _m output from the node 61 of the amplitude amplification circuit 6 is input. Therefore, as shown in FIG. 12, in the transfer period in which the timing signal TG is at low level (0 V), the inverted amplified signal TG _m is at high level (V _H ), so that the PMOSFET 82a is in the OFF state and the NMOSFETs 82b and 82c are It is turned on. Therefore, during the transfer period, the clamp section 8a is in the same connected state as the above-mentioned clamp circuit 7, and the clamp /
The pulse synthesis circuit 8 performs the same operation as the clamp circuit 7.

In the transfer period, the clamp section 8a transmits the AC component (amplitude V _L ) of the amplified pulse signals (V _1m and V _3m ) input to the input line 80a by the capacitor C and the DC component by the diode. Clamp by 81. Thus, the signal on the output line 80b in the transfer period is a binary signal level -V _L ~0.

Timing signal TG is at high level (5V)
In the read period, the inverted amplified signal TG _m is at a low level (0 V), so that the PMOSFET 82 a
Is ON, NMOSFETs 82b and 82c are OFF
State. At this time, since the amplified pulse signal TG _m 'supplied to the input line 80e is at the high level (V _H ), the high level voltage (V _H ) is output to the output line 80b via the PMOSFET 82a.

[0098] Therefore, from the clamp / pulse synthesizing circuit 8, in the same manner as in Example 1, as shown in FIG. 12, the low level (-V _L), intermediate value (0V), and the high level (V _H) Three-valued pulse voltage signals φV ₁ and φV _{3 having}
Is output.

As shown in FIG. 25, the pulse synthesizing unit 8b can also be configured by using a PMOSFET 82e with its gate grounded instead of the PMOSFET 82a.

Similar to the case of the clamp circuit 7, the clamp portion 8a can be constructed by using other semiconductor elements such as MOSFET in addition to the clamp circuit using the diode shown in FIG. For example, as shown in FIG.
Instead of the diode 81, a P-channel MOSFET 83
May be used. In the PMOSFET 83, the gate and the drain are grounded via the NMOSFET 82b, and the source is connected to the output line 80b. Further, even in this case, as shown in FIG.
PMOSFET 82 with its gate grounded instead of 2a
The pulse synthesizing unit 8b can also be configured by using e.

Further, as shown in FIG.
Instead of 1, the N-channel MOSFET 84 may be used to configure the clamp portion 8a. The NMOSFET 84 is
The gate and drain are connected to the output line 80b, and the source is grounded via the NMOSFET 82b. Furthermore, even in this case, as shown in FIG.
PM whose gate is grounded instead of MOSFET 82a
The pulse synthesizing unit 8b can also be configured using the OSFET 82e.

The clamp circuit 8a is not limited to the above example, but another peak clamp circuit or another clamp circuit can be used.

Next, another configuration example of the clamp / pulse synthesizing circuit 8 will be described. FIG. 30 shows an example of the clamp / pulse synthesizing circuit 8 in which the pulse synthesizing unit 8b is configured by using the P-channel MOSFET 82a and the N-channel MOSFET 82d.

As shown in FIG. 30, the clamp portion 8a
Is a negative clamp circuit having the same configuration as the clamp circuit 7 described in FIG. 14 and having a capacitor C and a diode 81. The output line 80b of the clamp section 8a is connected to the source terminal of the NMOSFET 82d of the pulse synthesizing section 8b. The capacitance of the capacitor C of the clamp portion 8a is set to 0.1 μF or more as in the case of the clamp circuit 7.

In the pulse synthesizer 8b, the source terminal of the P-channel MOSFET 82a is the amplified pulse signal T output from the node 62 of the second amplitude amplifier circuit 6.
Input line 80e to which G _m '(amplitude level 0 to V _H ) is supplied
It is connected to the. The drain terminals of the P-channel MOSFET 82a and the N-channel MOSFET 82d are both connected to the output line 80c. P channel MOSFE
The gate terminals of the T82a and N-channel MOSFET82d is inverted amplified signal TG _m outputted from the second node 61 of the amplitude amplification circuit 6 is connected to the input line 80d to be supplied.

Therefore, the inverted amplified signal TG_mIs high level
(V_H), The PMOSFET 8
2a is in the OFF state and NMOSFET 82d is in the ON state
Therefore, the output line 80c of the clamp / pulse conversion circuit 8
The signal on the output line 80b of the clamp section 8a is output to
It is. During the transfer period, the clamp unit 8a clamps
As with the circuit 7, the amplified signal input to the input line 80a is input.
Pulse signal (V_1mAnd V _3m) AC component (amplitude level 0
~ V_L) Is transmitted by the capacitor C, and the DC component is reduced.
Clamp with Iodo 81. Therefore, the transfer period
The signal on the output line 80c at level -V_L~ 0 of 2
It becomes a value signal.

The inverted amplified signal TG _m is at low level (0 V)
During the read period, the PMOSFET 82a
Turns on and the NMOSFET 82d turns off. At this time, since the amplified pulse signal TG _m 'supplied to the input line 80e is at the high level (V _H ), PM
The high level voltage (V _H ) is output to the output line 80c via the OSFET 82a.

[0108] Thus, as from the clamp / pulse synthesizing circuit 8, shown in FIG. 12, the low level (-V _L),
Three-valued pulse voltage signals φV ₁ and φV ₃ having an intermediate value (0 V) and a high level (V _H ) are output.

As shown in FIG. 31, the pulse synthesizing unit 8b can also be constructed by using a PMOSFET 82e with its gate grounded instead of the PMOSFET 82a.

Similar to the case of the clamp circuit 7, the clamp portion 8a can be formed by using other semiconductor elements such as MOSFET in addition to the clamp circuit using the diode shown in FIG. For example, as shown in FIG.
Instead of the diode 81, a P-channel MOSFET 83
May be used. The PMOSFET 83 has its gate and drain grounded, and its source connected to the output line 80b. Further, also in this case, as shown in FIG. 33, the pulse synthesizing unit 8b can be configured by using the PMOSFET 82e whose gate is grounded instead of the PMOSFET 82a.

As shown in FIG. 34, the diode 8
Instead of 1, the N-channel MOSFET 84 may be used to configure the clamp portion 8a. The NMOSFET 84 is
The gate and drain are connected to the output line 80b, and the source is grounded. Furthermore, in this case as well, FIG.
As shown in, instead of the PMOSFET 82a,
The pulse synthesizing unit 8b can be configured by using the PMOSFET 82e whose gate is grounded.

The clamp circuit 8a in the clamp / pulse synthesizing circuit 8 is not limited to the above example, but other peak clamp circuits or other clamp circuits can be used.

Also in this embodiment, the same effect as that of the first embodiment can be obtained. Further, in the case of the present embodiment, the pulse signal supplied from the second amplitude conversion circuit is used as the voltage signal having a high level to be supplied to the clamp / pulse combination circuit, instead of the DC voltage from the power supply circuit. . Therefore, there is an advantage in that the transistor does not latch up due to its configuration.

(Embodiment 3) Driver circuit 1 according to the present invention
Can be integrated independently, but can also be integrated with the CCD image pickup device 3 to be integrated. In this embodiment, a case where the driver circuit 1 and the CCD image pickup device 3 are integrally formed on the same substrate will be described.

FIG. 36 is a circuit diagram of the driver circuit 1 shown in FIG.
The clamp circuit 7 using the diode 71 shown in
The configuration when integrated with the CD image pickup device 3 is shown. Here, a pulse voltage signal φV for driving the vertical CCD
A case where the clamp circuit 7 that outputs ₄ is formed will be described.

As shown in FIG. 36, in the n-type substrate 11 which is the substrate of the integrated circuit, the vertical C of the CCD image pickup device 3 is used.
The impurity concentration is thin and shallow in the CCD 3'that forms the CD.
The well 12 is formed, and the p-well 1 with a high impurity concentration is formed in the clamp circuit portion 7 ′ forming the clamp circuit 7.
4 is formed.

In the CCD section 3 ', a driving electrode 13 is formed on the surface of the p well via an oxide film (not shown). To each electrode 13, through the respective wiring,
Pulse voltage signals φV _{1 to} φV ₄ for driving the CCD are applied. A positive voltage V _OFD is applied to the n-type substrate 11.

In the clamp circuit portion 7'of the n-type substrate 11, a PN junction diode 71 is formed in the p-well 14. The cathode of the diode 71 is grounded, and the anode is connected to the output line 70b from the capacitor C. The amplified timing signal V _4m is supplied to the capacitor C via the input line 70a. The capacitor C is formed externally or in a region (not shown) of the n-type substrate 11. As described in the first embodiment, the pulse voltage signal φV ₄ for driving the CCD is output from the output line 70b and applied to the corresponding electrode 13.

FIG. 37 is a circuit diagram of the driver circuit 1 shown in FIG.
The configuration in which the clamp / pulse synthesizing circuit 8 using the diode 81 shown in FIG. Here, a clamp / pulse synthesizing circuit 8 for outputting a pulse voltage signal φV ₁ for driving a vertical CCD
Will be described.

As shown in FIG. 37, in the n-type substrate 11 which is the substrate of the integrated circuit, the vertical C of the CCD image pickup device 3 is used.
The impurity concentration is thin and shallow in the CCD 3'that forms the CD.
The well 12 is formed, and the clamp / pulse synthesis circuit portion 8 ′ forming the clamp / pulse synthesis circuit 8 has a deep p-well 1 with a high impurity concentration corresponding to each element.
5 to 17 are formed.

In the CCD section 3 ', a driving electrode 13 is formed on the surface of the p well via an oxide film (not shown). To each electrode 13, through the respective wiring,
Pulse voltage signals φV _{1 to} φV ₄ for driving the CCD are applied. A positive voltage V _OFD is applied to the n-type substrate 11.

As shown in FIG. 37, in the clamp / pulse synthesizing circuit portion 8'of the n-type substrate 11, an N-channel MOSFET 82c is formed in the p-well 15 and p-type
An N channel MOSFET 82b and a diode 81 are formed in the well 16, and a P channel MOSFET 82a is formed in the p well 17.

The amplified timing signal V _1m is supplied to the capacitor C via the input line 80a. The capacitor C is formed externally or in a region (not shown) of the n-type substrate 11. The output from the capacitor C is connected to the source of the NMOSFET 82c, and
The drain of the SFET 82c is connected to the output line 80b.

The anode of the diode 81 is connected to the output line 80b, and the cathode of the diode 81 is NMOS.
It is connected to the source of the FET 82b. NMOSFE
The drain of T82 is grounded. Also, the output line 80
The power supply voltage (V _H ) is applied to b through the PMOSFET 82a in the p well 17. MOSFET 82a
The inverted amplified signal TG _m is input to each of the gates 82c to 82c, and as described in the first embodiment, the output line 80b outputs CC.
The pulse voltage signal φV ₁ for D driving is output and applied to the corresponding electrode 13.

In any of the examples shown in FIGS. 36 and 37, the p-well 12 formed in the CCD section has an excess charge n in the photodiode due to the punch-through phenomenon caused by setting the positive voltage V _OFD to a high voltage. It is preferable that the impurity concentration is low and the impurity concentration is low so that the impurity is emitted to the mold substrate 11 side. On the other hand, the deep p-wells 14 to 17 of the clamp circuit unit 7'and the clamp / pulse combination circuit unit 8'have MOSs.
Since the FET and the like are formed, it is necessary to form the FET deep so that the punch through phenomenon does not occur and to make the impurity concentration relatively high. Therefore, generally, the p well 12 is formed to have a carrier density of 10 ¹⁴ cm ⁻³ and a junction depth of about 2 μm, and the p wells 14 to 17 have a carrier density of 10 ¹⁵ c.
m ⁻³ , and the junction depth is 4 μm or more.

The p-wells 15 to 17 of the clamp / pulse synthesizing circuit portion 8'shown in FIG. 37 may have the same impurity concentration and the same depth. In addition, p well 16 and p well 17
Since the potentials of both are 0V, they can be formed as a common p-well. Since the p-well 15 has a different potential,
It is formed separately.

By forming the p wells 16 and 17 as a common p well, an N-channel MOSFET 82b formed inside and the n well 1 in the p well 17 are formed.
If the P-channel MOSFET 82a formed in 8 may cause a latch-up phenomenon, the p-well 16 and the p-well 17 should be formed separately.

[0128]

As described above, according to the driver circuit of the present invention, the input pulse signal (timing signal) is amplitude-converted and then clamped to supply only the power supply voltage of the positive level (V _H ). using the voltage circuit of the system, it is possible to generate a pulse voltage binary signal having a negative voltage level (-V _L). From a positive level of the power supply voltage, by generating an intermediate voltage using a voltage divider circuit (V _L), the supply voltage and can obtain a different negative voltage absolute value (-V _L). The voltage to be clamped in the clamp section of the clamp circuit or the clamp / pulse combination circuit can be freely selected between the ground voltage (0 V) and the intermediate voltage (V _L ) obtained by the voltage dividing circuit.

The binary voltage signal having the negative voltage level thus obtained is combined with the signal having the positive level (that is, switched at a predetermined timing and output) to obtain the negative voltage level. (For example −
It is possible to generate a ternary pulse voltage signal having V _L ), an intermediate value (eg 0 V) and a positive voltage level (eg V _H ). In the above embodiment, the case where the positive level DC voltage (V _H ) is combined has been described, but it is also possible to combine a binary signal having a positive level or higher (for example, a binary pulse signal). In this way, the pulse voltage signal to be combined is not limited to three values, but it is possible to generate a pulse voltage signal having a desired multilevel level by performing clamping and pulse combination.

In the above embodiment, the driver circuit for generating the multi-valued pulse voltage signal including the negative voltage level by using the one-system power supply circuit for generating the positive voltage has been described. It is not limited to.
According to the present invention, similarly, it is also possible to generate a multi-valued pulse voltage signal including a positive voltage level by using only one system of power supply circuit that generates a negative voltage. As described above, according to the present invention, by using either one of the positive and negative power supply circuits,
It is possible to generate a driving pulse voltage signal of a desired multi-valued level including a positive level and a negative level.

Therefore, according to the present invention, a multi-level pulse voltage signal for driving various devices can be provided without separately providing a power supply circuit for generating voltage signals having different polarities (positive voltage or negative voltage). Can be generated, so that the device can be downsized and the cost can be reduced. Further, the circuit configuration can be further simplified by integrally forming the clamp circuit and the clamp / pulse combination circuit with the CCD image pickup device.

The driver circuit according to the present invention is not limited to driving a CCD image pickup device. However, as described in the embodiments, when the driver circuit of the present invention is applied to drive a vertical CCD of a CCD image pickup device in a camera system, it is advantageous in many points as described below.

In a camera system, ICs and electrolytic capacitors usually occupy most of the board area of the camera system. An electrolytic capacitor must be provided for each power source in order to prevent noise. Therefore, for example, when the power supply circuit has a positive voltage system and a negative voltage system,
An electrolytic capacitor is required for each system.

According to the present invention, since only one power supply circuit can be provided, the number of electrolytic capacitors that occupy a large area of the board of the camera system can be significantly reduced. It is very advantageous for weight reduction and weight reduction. Furthermore, power supply parts (electrolytic capacitor, D
Since it is possible to reduce the number of C converters, wiring, connectors of the power supply section, etc., it is possible to reduce costs.

The IC portion is composed of a CCD, a driver circuit (driver IC), a timing circuit and the like. By using only one power supply circuit, the internal structure of the driver circuit can be simplified and the number of foot pins can be reduced.

It is also possible to integrally form the driver circuit inside the CCD. CCD driver circuit
Although the chip area increases by that amount, the increase in the chip area as a whole can be suppressed by using a single power supply circuit. Therefore, even if they are integrated, it is advantageous for downsizing the camera system.

Further, according to the driver circuit of the present invention, the CCD can be driven only by the positive level (or negative level) power supply voltage. Therefore, positive power supply (or negative power supply)
Therefore, a DC converter for generating a negative voltage (or a positive voltage) becomes unnecessary, and power consumption can be reduced accordingly.
In simple image input devices (for example, personal digital assistants, PCs, TV phones, etc.) using CCD image pickup devices, there is a particularly high demand for low power consumption. According to the present invention, not only can the device be made lighter and more compact, but it is also possible to satisfy such demands for lower power consumption.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a conventional CCD type image pickup device.

FIG. 2 is a time chart showing a conventional pulse voltage signal for driving a vertical CCD of a CCD image pickup device.

FIG. 3 is a block diagram showing a conventional driver circuit for driving a CCD image pickup device, a timing circuit, and a power supply circuit.

FIG. 4 is a time chart showing a timing signal generated by a conventional timing circuit.

FIG. 5 is a block diagram showing a configuration of a conventional driver circuit.

FIG. 6 is a time chart showing a pulse signal output from an amplitude conversion circuit in a conventional driver circuit.

FIG. 7 is a block diagram showing a configuration of a clamp circuit and an amplitude conversion circuit in a conventional driver circuit.

FIG. 8 is a clamp circuit in a conventional driver circuit,
It is a block diagram which shows the structure of an amplitude conversion circuit and a pulse synthesis circuit.

FIG. 9 is a block diagram showing a configuration for driving a CCD image pickup device by a driver circuit according to the present invention.

FIG. 10 is a block diagram showing a configuration of a driver circuit according to one embodiment of the present invention.

FIG. 11 is a block diagram showing a configuration of a first amplitude conversion circuit in the driver circuit of the present invention.

FIG. 12 is a time chart showing various pulse signals generated in the driver circuit of the present invention.

FIG. 13 is a block diagram showing a configuration of a second amplitude conversion circuit in the driver circuit of the present invention.

FIG. 14 is a block diagram showing one configuration example of a clamp circuit in the driver circuit of the present invention.

FIG. 15 is a block diagram showing another configuration example of the clamp circuit in the driver circuit of the present invention.

FIG. 16 is a block diagram showing another configuration example of the clamp circuit in the driver circuit of the present invention.

FIG. 17 is a block diagram showing a configuration example of a clamp / pulse synthesizing circuit in a driver circuit according to one embodiment of the present invention.

FIG. 18 is a block diagram showing another configuration example of the clamp / pulse synthesizing circuit in the driver circuit according to one embodiment of the present invention.

FIG. 19 is a block diagram showing another configuration example of the clamp / pulse synthesizing circuit in the driver circuit according to one embodiment of the present invention.

FIG. 20 is a block diagram showing another configuration example of the clamp / pulse synthesizing circuit in the driver circuit according to one embodiment of the present invention.

FIG. 21 is a block diagram showing another configuration example of the clamp / pulse synthesizing circuit in the driver circuit according to one embodiment of the present invention.

FIG. 22 is a block diagram showing still another configuration example of the clamp / pulse synthesizing circuit in the driver circuit according to one embodiment of the present invention.

FIG. 23 is a block diagram showing a configuration of a driver circuit according to another embodiment of the present invention.

FIG. 24 is a block diagram showing a configuration example of a clamp / pulse synthesizing circuit in a driver circuit according to another embodiment of the present invention.

FIG. 25 is a block diagram showing another configuration example of the clamp / pulse synthesizing circuit in the driver circuit according to another embodiment of the present invention.

FIG. 26 is a block diagram showing another configuration example of the clamp / pulse synthesizing circuit in the driver circuit according to another embodiment of the present invention.

FIG. 27 is a block diagram showing another configuration example of the clamp / pulse synthesizing circuit in the driver circuit according to another embodiment of the present invention.

FIG. 28 is a block diagram showing another configuration example of the clamp / pulse synthesizing circuit in the driver circuit according to another embodiment of the present invention.

FIG. 29 is a block diagram showing another configuration example of the clamp / pulse synthesizing circuit in the driver circuit according to another embodiment of the present invention.

FIG. 30 is a block diagram showing another configuration example of the clamp / pulse synthesizing circuit in the driver circuit according to another embodiment of the present invention.

FIG. 31 is a block diagram showing still another configuration example of the clamp / pulse synthesizing circuit in the driver circuit according to another embodiment of the present invention.

FIG. 32 is a block diagram showing another configuration example of the clamp / pulse synthesizing circuit in the driver circuit according to another embodiment of the present invention.

FIG. 33 is a block diagram showing another configuration example of the clamp / pulse synthesizing circuit in the driver circuit according to another embodiment of the present invention.

FIG. 34 is a block diagram showing another configuration example of the clamp / pulse synthesizing circuit in the driver circuit according to another embodiment of the present invention.

FIG. 35 is a block diagram showing still another configuration example of the clamp / pulse synthesizing circuit in the driver circuit according to another embodiment of the present invention.

FIG. 36 is a sectional view showing a configuration example of a clamp circuit formed on a substrate according to one embodiment of the present invention.

FIG. 37 is a cross-sectional view showing a configuration example of a clamp / pulse synthesizing circuit formed on a substrate according to one embodiment of the present invention.

[Explanation of symbols]

 4 Power Supply Circuit 5 1st Amplitude Conversion Circuit 6 2nd Amplitude Conversion Circuit 7 Clamp Circuit 70a Input Line 70b Output Line 71 Diode 8 Clamp / Pulse Synthesis Circuit 8a Clamp Section 8b Pulse Synthesis Section 80a Input Line 80b Output Line 81 Diode 82a ~ C MOSFET 9 voltage divider

Claims (17)

[Claims] 1. A driver circuit for generating a driving pulse signal having a plurality of levels by using a power supply voltage of a first polarity supplied from a power supply based on an input timing signal, the driver circuit comprising: A voltage dividing means for generating a first voltage by dividing the power supply voltage, and converting the amplitude of the input timing signal by using the first voltage to substantially divide the first voltage and the ground voltage. Amplitude converting means for generating an amplified signal having a peak at, and the ground voltage peak of the amplified signal being shifted to a second voltage having a second polarity different from the first polarity, Clamp means for clamping the amplified signal at a predetermined voltage between the ground voltage and the first voltage, whereby the second voltage has a peak and the first voltage
A driver circuit that produces a pulsed voltage signal having an amplitude substantially equal to the voltage of the. 2. A synthesizing unit for synthesizing a pulse voltage signal generated by the clamp unit with a third voltage signal to generate a driving pulse voltage signal having a level of three values or more. The driver circuit described in. 3. The driver circuit according to claim 2, wherein the third voltage signal is a DC voltage signal having a power supply voltage level of the first polarity supplied from the power supply. 4. The driver circuit according to claim 2, wherein the third voltage signal is a pulse voltage signal having peaks at the power supply voltage and the ground voltage. 5. The driver circuit according to claim 2, wherein the synthesizing means includes means for switching and outputting the pulse voltage signal generated by the clamp means and the third voltage signal at a predetermined timing. 6. The power supply voltage supplied from the power supply is used to convert the amplitude of a second input timing signal to generate a second amplified signal having peaks at the power supply voltage of the first polarity and the ground voltage. The driver circuit according to claim 2, further comprising second amplitude converting means for generating. 7. The driver circuit according to claim 6, wherein the third voltage signal is the second amplified signal. 8. The driver circuit according to claim 1, wherein the predetermined voltage clamped by the clamp means is a ground voltage. 9. The driver circuit according to claim 1, wherein the clamp means is a diode clamp circuit having a capacitor and a diode. 10. Based on the input timing signal,
A method of generating a driving pulse voltage signal having a plurality of levels using a power supply voltage of a first polarity supplied from a power supply, the method dividing the power supply voltage to generate a first voltage. A voltage division step of generating, and an amplitude conversion step of converting the amplitude of the input timing signal using the first voltage to substantially generate an amplified signal having a peak between the first voltage and the ground voltage. , The ground voltage and the first voltage of the amplified signal such that the ground voltage peak of the amplified signal is shifted to a second voltage having a second polarity different from the first polarity. Clamping at a predetermined voltage between and to produce a pulsed voltage signal having a peak at the second voltage and an amplitude substantially equal to the first voltage. . 11. The synthesizing step according to claim 10, further comprising: a synthesizing step of synthesizing a third voltage signal with the pulse voltage signal generated in the clamping step to generate a driving pulse voltage signal having three or more levels. Of generating pulse voltage signal for driving. 12. The third step in the synthesis step.
As the voltage signal of, a DC voltage signal having a power supply voltage level of the first polarity supplied from the power supply is used.
The method of generating a driving pulse voltage signal according to claim 11. 13. The third step in the synthesis step.
12. The method for generating a driving pulse voltage signal according to claim 11, wherein a pulse voltage signal having a peak at the power supply voltage and the ground voltage is used as the voltage signal. 14. The driving pulse according to claim 11, wherein the synthesizing step includes a step of switching the pulse voltage signal generated in the clamping step and the third voltage signal at a predetermined timing and outputting the pulse voltage signal. How to generate a voltage signal. 15. A second amplified signal having the peaks of the power supply voltage and the ground voltage, wherein the amplitude of the second input timing signal is converted using the power supply voltage of the first polarity supplied from the power supply. The driving pulse voltage signal generating method according to claim 11, further comprising a second amplitude converting step for generating. 16. The third step in the synthesizing step
16. The method for generating a driving pulse voltage signal according to claim 15, wherein the second amplified signal is used as the voltage signal of. 17. The step of clamping comprises:
The method of generating a driving pulse voltage signal according to claim 10, wherein the predetermined voltage is a ground voltage.