JP3600103B2 - Buffer circuit and driver including buffer circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a buffer circuit and a driver including the same, and more particularly to a technique for reducing current consumption of a buffer circuit including a CMOS inverter in an output stage.
[0002]
[Prior art]
FIG. 7 shows a configuration of a conventional buffer circuit. As shown in the figure, the buffer circuit includes an input inverter circuit 3, an output-stage CMOS inverter circuit 10 in which a P-channel MOS transistor TRp and an N-channel MOS transistor TRn are connected in series, and the like. . Here, the source S of the P-channel MOS transistor TRp is connected to the power supply VDD, and the source S of the N-channel MOS transistor TRn is connected to GND (ground).
[0003]
In such a buffer circuit, the input signal IN input to the input terminal 1 is normally delayed by a predetermined time due to the operation delay in the input inverter circuit 3 and the output-stage CMOS inverter circuit 10 and is output from the output terminal 2. Is done. When the buffer circuit is used as an output buffer of various circuits, the size (current capacity) of the transistors TRp and TRn constituting the output-stage CMOS inverter circuit 10 depends on the load connected to the output terminal 2. ) Etc. are appropriately designed.
[0004]
[Problems to be solved by the invention]
By the way, in the buffer circuit provided with the CMOS inverter circuit 10 in the output stage, although the signal delay and the driving of an arbitrary load can be performed with a simple circuit configuration, the transistors TRp and TRn in the CMOS inverter circuit 10 are used. In the switching, the through current flowing through the transistors cannot be ignored.
[0005]
In particular, in a buffer circuit for driving a load, the through-current of the output-stage CMOS inverter circuit is larger than that of a CMOS inverter circuit simply used for logic inversion or the like. Therefore, in a driver or the like that uses a large number of buffer circuits including such an output-stage CMOS inverter circuit, it is unavoidable to waste power and reduce reliability due to the through current. .
[0006]
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a buffer circuit capable of appropriately preventing a through current of a CMOS inverter circuit while having the CMOS inverter circuit in an output stage. It is to provide a driver having:
[0007]
[Means for Solving the Problems]
Hereinafter, the means for achieving the above object and the effects thereof will be described.
The invention according to claim 1 is a buffer circuit including a CMOS inverter circuit in which a P-channel MOS transistor and an N-channel MOS transistor are connected in series at an output stage, wherein the P-channel MOS transistor and the N-channel MOS transistor are provided. The gist of the invention is to provide a timing adjustment circuit that adjusts the timing of applying an input signal to the gates of these transistors so that the gates do not turn on simultaneously.
[0008]
According to this configuration, the P-channel MOS transistor and the N-channel MOS transistor included in the CMOS inverter circuit are not simultaneously turned on by the timing adjustment circuit. Therefore, a large through current is prevented from flowing through the transistors, and the reliability of the transistors can be improved, and the power consumption of the buffer circuit can be reduced.
[0009]
According to a second aspect of the present invention, in the buffer circuit according to the first aspect, the timing adjustment circuit is configured so that the gates of the P-channel MOS transistor and the N-channel MOS transistor have an off period of one of the transistors. The gist of the present invention is to provide a logic circuit for applying a switching signal for turning on the other transistor.
[0010]
According to this configuration, while being constituted by the logic circuit constituting the timing adjustment circuit, the P-channel MOS transistor and the N-channel MOS transistor are turned on only while the other is off. Therefore, it is surely prevented that these transistors are turned on at the same time.
[0011]
According to a third aspect of the present invention, in the buffer circuit according to the second aspect, the timing adjustment circuit inputs the input signal to one input terminal and inputs the other output signal to the other input terminal. A parallel circuit of a circuit and an OR circuit, wherein the output signal of the AND circuit is applied to the gate of the N-channel MOS transistor, and the output signal of the OR circuit is applied to the gate of the P-channel MOS transistor. Is the gist.
[0012]
According to the configuration, the timing adjustment circuit including the logic circuit can be easily and suitably formed.
According to a fourth aspect of the present invention, in the buffer circuit according to the first aspect, the timing adjustment circuit delays an on-timing of the P-channel MOS transistor to reduce an on-period of the N-channel MOS transistor. A first delay circuit for shortening the ON timing of the N-channel MOS transistor and a second delay circuit for delaying the ON period of the N-channel MOS transistor to be shorter than the OFF period of the P-channel MOS transistor. The gist is to be composed.
[0013]
According to this configuration, the N-channel MOS transistor is turned on before the P-channel MOS transistor is turned on by utilizing the difference between the long rise time or the long fall time of each gate switching signal, and the N-channel MOS transistor is turned on. The P-channel MOS transistor can be turned on before the transistor is turned on. Therefore, it is possible to preferably prevent the transistors from turning on at the same time.
[0014]
According to a fifth aspect of the present invention, in the buffer circuit according to the fourth aspect, the first delay circuit is an inverter circuit having a large fall time constant at the time of signal inversion, and the second delay circuit The gist of the circuit is that the circuit is an inverter circuit in which a rising time constant at the time of signal inversion is set to be large.
[0015]
According to this configuration, the first delay circuit and the second delay circuit can be formed with an extremely simple configuration. Therefore, the present buffer circuit can be formed only by adding a small circuit configuration to the conventional buffer circuit, and the additional cost can be reduced.
[0016]
According to a sixth aspect of the present invention, a plurality of functional circuits having different operation frequencies and different voltages to be handled, and a buffer circuit in each of the circuits performing a predetermined buffer operation are mixedly mounted as a one-chip semiconductor integrated circuit device. A driver circuit having a high frequency of operation among the functional circuits, wherein the buffer circuit comprises a CMOS inverter circuit in which a P-channel MOS transistor and an N-channel MOS transistor are connected in series. Circuit comprising: an output stage; and a first timing adjustment circuit for generating a switching signal for turning on the P-channel MOS transistor during a period in which the N-channel MOS transistor is turned off, based on an input signal. And among the functional circuits, the frequency of operation is low or the voltage handled is high. The functional circuit includes, as the buffer circuit, an output stage including a CMOS inverter circuit in which a P-channel MOS transistor and an N-channel MOS transistor are connected in series, and an on-stage by delaying the on-timing of the P-channel MOS transistor. A switching signal is input to make the period shorter than the off-period of the N-channel MOS transistor and delay the on-timing of the N-channel MOS transistor to make the on-period shorter than the off-period of the P-channel MOS transistor. The gist of the present invention is to provide a buffer circuit having a second timing adjustment circuit that generates a signal based on a signal.
[0017]
According to the configuration, the buffer circuits provided in a plurality of functional circuits having different operation frequencies and voltages handled in the driver are different from the buffer circuit having the first timing adjustment circuit in accordance with the operation frequency of the function circuits. A buffer circuit having the second timing adjustment circuit is used as appropriate. In other words, a function circuit with a high operation frequency is provided with a buffer circuit having a first timing adjustment circuit with a reliable operation, while a function circuit with a low operation frequency or a high voltage to be handled has a small circuit scale. A buffer circuit having a second timing adjustment circuit is provided. Therefore, it is possible to obtain a reliable operation or reduce an increase in the circuit scale while reducing power consumption of a circuit in the driver.
[0018]
According to a seventh aspect of the present invention, in the driver including the buffer circuit according to the sixth aspect, the first timing adjustment circuit inputs the input signal to one input terminal and outputs the other output signal to the other input terminal. A parallel circuit of an AND circuit and an OR circuit input to an input terminal of the CMOS inverter circuit for applying an output signal of the AND circuit to a gate of the N-channel MOS transistor of the corresponding CMOS inverter circuit; The output signal is applied to the gate of the P-channel MOS transistor of the CMOS inverter circuit, and the second timing adjustment circuit is configured to delay the on-timing of the P-channel MOS transistor during signal inversion to delay the on-timing of the P-channel MOS transistor. A first inverter circuit whose falling time constant is set to be large; As its gist to be configured and a second inverter circuit rise time constant is set large signal inversion time in order to delay the on-timing of the OS transistor.
[0019]
According to this configuration, the first timing adjustment circuit and the second timing adjustment circuit can be suitably and simply configured.
According to an eighth aspect of the present invention, there is provided a driver including the buffer circuit according to the sixth or seventh aspect, wherein the driver is a device for driving a CCD image sensor; A first charge pump for boosting and generating a pulse voltage of a pulse used for a transfer operation, and a buffer circuit used for the charge pump is a circuit for delaying a pumping clock input to a pumping capacitor of the charge pump. The functional circuit whose operation frequency is low or whose voltage is high is a circuit that generates and outputs a pulse used for the charge transfer operation of the CCD, or a second charge pump that boosts and generates a bias voltage of the CCD. At the same time as generating and outputting a pulse used for the charge transfer operation. Is a circuit that converts the level of a separately applied timing clock based on the output voltage of the first charge pump, and the buffer circuit used for the second charge pump is The gist of the present invention is to provide a circuit for delaying a pumping clock input to a pumping capacitor.
[0020]
According to the configuration, the buffer circuits provided in a plurality of functional circuits (charge pumps, drive circuits, and the like) having different operation frequencies in the CCD driver and different voltages to be handled are provided according to the operation frequencies of the functional circuits. And a buffer circuit having the second timing adjustment circuit. Therefore, it is possible to obtain the reliable operation or to minimize the increase in the circuit scale while reducing the power consumption of the functional circuit in the CCD driver.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
(First Embodiment)
Hereinafter, a first embodiment of a buffer circuit according to the present invention will be described with reference to FIGS.
[0022]
FIG. 1 is a circuit diagram showing a configuration of the buffer circuit according to the present embodiment.
As shown in FIG. 1, this circuit basically includes an input inverter circuit 3 and a P-channel MOS transistor TRp and an N-channel MOS transistor TRn, similarly to the above-described conventional buffer circuit. The output stage CMOS inverter circuit 10 composed of a series circuit is provided.
[0023]
In addition to the basic configuration of these buffer circuits, the buffer circuit of the present embodiment further includes a timing adjustment circuit 20 including a parallel circuit of an OR circuit 21 and an AND circuit 22.
[0024]
Here, the output of the input inverter circuit 3 is input to one input terminal of the OR circuit 21 and the output of the AND circuit 22 is input to the other input terminal. The output of the OR circuit 21 is input to the AND circuit 22 and the gate of the P-channel MOS transistor TRp as a switching signal Pin.
[0025]
The output of the input inverter circuit 3 is input to one input terminal of the AND circuit 22, and the output of the OR circuit 21 is input to the other input terminal. The output of the AND circuit 22 is input to the OR circuit 21 and the gate of the N-channel MOS transistor TRn as a switching signal Nin.
[0026]
Next, the operation of the buffer circuit of the present embodiment thus configured will be described with reference to the timing chart of FIG.
When the input signal IN changes to the logic "H (high)" level (VDD) at time t1 shown in FIG. 2 (see FIG. 2A), the output of the input inverter circuit 3 becomes the logic "L (low)" level. (0 volts). At time t2, which is a predetermined time later, first, the switching signal Nin, which is the output of the AND circuit 22, goes to the logic "L" level (see FIG. 2C), and accordingly, the N-channel MOS transistor TRn is turned off.
[0027]
At time t3, which is a predetermined time after the output of the AND circuit 22 at the logical "L" level is input to the OR circuit 21, the switching signal Pin, which is the output of the OR circuit 21, changes to the logical "L" level. (See FIG. 2B). Accordingly, the P-channel MOS transistor TRn is turned on, and the output signal OUT of the buffer circuit goes to the logic “H” level (see FIG. 2D).
[0028]
On the other hand, when the input signal IN changes to the logic “L” level at time t4 shown in FIG. 2, the output of the input inverter circuit 3 changes to the logic “H” level. Then, at time t5 after a predetermined time, the output Pin of the OR circuit 21 goes to the logic “H” level, and the P-channel MOS transistor TRn is turned off accordingly.
[0029]
Further, at time t6, which is a predetermined time after the output of the logical "H" level of the OR circuit 21 is input to the AND circuit 22, the output Nin of the AND circuit 22 becomes the logical "H" level (FIG. c)). Accordingly, the N-channel MOS transistor TRn is turned on, and the output signal OUT of the buffer circuit goes to the logical “L” level (see FIG. 2D). Thereafter, the same operation is repeated according to the level change of the input signal IN.
[0030]
That is, in the present embodiment, as shown in FIG. 2, the on-period τnon of the N-channel MOS transistor TRn is formed within the off-period τpoff of the P-channel MOS transistor TRp, and the N-channel MOS An on-period τpon of the P-channel MOS transistor TRp is formed within the off-period τnoff of the transistor TRn. Therefore, when the transistors TRp and TRn are switched, the transistors TRp and TRn are not turned on at the same time, so that a through current flows through the transistors TRp and TRn.
[0031]
As described above, according to the buffer circuit of the present embodiment, the following effects can be obtained.
(1) The switching signals Pin and Nin are formed by the timing adjustment circuit 20 so that the transistors TRp and TRn are not simultaneously turned on. Therefore, a large through current is prevented from flowing through the transistors TRp and TRn, and the reliability of the transistors TRp and TRn can be improved and the power consumption of the buffer circuit can be reduced.
[0032]
(2) Since the timing adjustment circuit 20 is constituted by the logic circuits of the OR circuit 21 and the AND circuit 22, the switching signals Pin and Nin formed by these logic circuits are reliable and highly reliable.
[0033]
The above embodiment can be implemented by changing its configuration as follows.
The configuration of the logic circuit of the timing adjustment circuit 20 is not limited to the configuration shown in FIG. In short, any circuit can be used as long as it can generate the switching signals Pin and Nin that do not turn on the transistors TRp and TRn at the same time.
[0034]
Although the example in which the source S of the N-channel MOS transistor TRn is set to the ground potential GND (0 volt) has been described, the present invention can be similarly applied to a circuit in which the source S is set to a negative potential.
[0035]
(Second embodiment)
Next, a buffer circuit according to a second embodiment of the present invention will be described with reference to FIGS. 3 and 4, focusing on differences from the first embodiment. In FIG. 3, the same elements as those in the circuit of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and the description thereof will not be repeated.
[0036]
As shown in FIG. 3, in the buffer circuit of the second embodiment, the configuration of the timing adjustment circuit is different from the configuration of the timing adjustment circuit 20 of the first embodiment. In the present embodiment, the input inverter circuit 3 is not provided.
[0037]
The timing adjustment circuit 30 of the present embodiment sets the fall time constant at the time of signal inversion, that is, the fall time tf1 of its output to be longer (larger) than the fall time tf2 of the second inverter circuit 32 described below. And the second inverter circuit whose rising time constant at the time of signal inversion, that is, the rising time tr2 of its output is set longer (larger) than the rising time tr1 of the first inverter circuit 31 Consists of 32. An input signal IN is input to both of the inverter circuits 31 and 32, and an output of the first inverter circuit 31 is input to a gate of the P-channel MOS transistor as a switching signal Pin. The output of the inverter circuit 32 is input to the gate of the N-channel MOS transistor as a switching signal Nin.
[0038]
Next, the operation of the buffer circuit of the present embodiment thus configured will be described with reference to the timing chart of FIG.
When the input signal IN changes to the logic "H" level at the time t1 shown in FIG. 4 (see FIG. 4A), the switching signal Nin output from the second inverter circuit 32 becomes the logic "L" level. (See FIG. 4C), and accordingly, the N-channel MOS transistor TRn is turned off. Further, as the input signal IN changes to the logical “H” level, the level of the switching signal Pin, which is the output of the first inverter circuit 31, gradually decreases (see FIG. 4B). When the level of the signal Pin decreases to near the logic "L" level at a time t2 after a predetermined time, the P-channel MOS transistor TRp turns on, and the output signal OUT of the buffer circuit changes to the logic "H" level. (See FIG. 4D).
[0039]
On the other hand, when the input signal IN changes to the logic “L” level at the time t3 shown in FIG. 4, the output Pin of the first inverter circuit 31 changes to the logic “H” level accordingly (see FIG. 4B). ). That is, the P-channel MOS transistor TRp is turned off. Further, as the input signal IN changes to the logical "L" level, the level of the output Nin of the inverter circuit 32 gradually increases (see FIG. 4C). Then, at time t4, when the level of the switching signal Nin rises to a predetermined level, the N-channel MOS transistor TRn turns on, and the output signal OUT of the buffer circuit goes to the logical “L” level (see FIG. 4D).
[0040]
That is, in the present embodiment, as described above, the P-channel MOS transistor at time t2 shown in FIG. 4 a predetermined time after the N-channel MOS transistor TRn is turned off at time t1 shown in FIG. TRp turns on. In addition, the N-channel MOS transistor TRn is turned on at a time t4 shown in FIG. 4 a predetermined time after the P-channel MOS transistor TRp is turned off at a time t3 shown in FIG.
[0041]
Therefore, when switching these transistors TRp and TRn, the transistors TRp and TRn are not turned on at the same time, and in this case also, it is possible to preferably prevent a through current from flowing through the transistors TRp and TRn.
[0042]
As described above, according to the buffer circuit of the present embodiment, the following effects can be obtained.
(1) The switching signals Pin and Nin are formed by the timing adjustment circuit 30 so that the transistors TRp and TRn are not simultaneously turned on. Therefore, a large through current is prevented from flowing through the transistors TRp and TRn, and the reliability of the transistors TRp and TRn can be improved and the power consumption of the buffer circuit can be reduced.
[0043]
(2) Further, the timing adjustment circuit 30 can be formed with an extremely simple configuration of two inverter circuits 31, 32. Therefore, the present buffer circuit can be formed only by adding a small circuit configuration to the conventional buffer circuit, and the additional cost can be reduced.
[0044]
The above embodiment can be implemented by changing its configuration as follows.
The circuit configuration of the timing adjustment circuit 30 is not limited to the configuration shown in FIG. In short, any circuit can be used as long as it can generate the switching signals Pin and Nin that do not turn on the transistors TRp and TRn at the same time.
[0045]
Although the example in which the source S of the N-channel MOS transistor TRn is set to the ground potential GND (0 volt) has been described, the present invention can be similarly applied to a circuit in which the source S is set to a negative potential.
[0046]
(Third embodiment)
Hereinafter, as a third embodiment, a driver including a buffer circuit according to the present invention will be described with reference to FIG. The driver according to the present embodiment drives a well-known frame transfer type CCD image sensor. More specifically, the driver transfers charges generated in an image pickup unit of the CCD to a storage unit at once, so-called vertical transfer drive of charges. Is implemented as a one-chip IC (integrated circuit device).
[0047]
As shown in FIG. 5, the driver according to the present embodiment includes a booster control circuit 41, a low-voltage generation charge pump 42, a high-voltage generation charge pump 43, a vertical drive circuit 44, an electronic shutter drive circuit 45, and the like. It is composed.
[0048]
Here, the boost control circuit 41 performs a boost mode by the low-voltage generation charge pump 42 and the high-voltage generation charge pump 43 based on a boost clock from a timing generation circuit that generates various clock signals for driving the CCD. This is the control circuit.
[0049]
Further, the low-voltage generation charge pump 42 generates a voltage of, for example, “−3VDD” in which the system power supply voltage VDD is boosted to the negative voltage side under the control of the boosting control circuit 41, and converts the same voltage to the high voltage. This is a circuit that supplies a charge pump 43 for generation, a vertical drive circuit 44, and an electronic shutter drive circuit 45.
[0050]
As illustrated in FIG. 6, the charge pump 42 includes four switching transistors TR1, TR2, TR3, TR4, three pumping capacitors C1, C2, C3, an output capacitor Cout, and the like as a basic configuration. It is configured. Further, a timing adjusting circuit 50 for adjusting the timing of the switching transistors TR1, TR2, TR3, and TR4 so that the switching transistors TR1, TR2, TR3, and TR4 are not simultaneously turned on by the applied clock signal, and the transistors TR1, TR2, TR3, and TR3. It has CMOS inverters 1, 2, 3, and 4 for surely maintaining the off state of TR4.
[0051]
Further, a buffer circuit of the type shown in FIG. 1 (hereinafter referred to as an AND / OR type buffer circuit) B1 is provided. Specifically, as shown in FIG. 6, it is provided as a buffer circuit for a pumping clock input to pumping capacitors C1, C2, and C3 externally attached to the present CCD driver. Therefore, even in a circuit such as the low-voltage generation charge pump 42, which operates at a high frequency and consumes a large amount of power due to switching, a reliable operation as a buffer circuit is assured and the through current is prevented. As a result, the power consumption can be reduced.
[0052]
Further, the charge pump 43 for generating a high voltage outputs a predetermined high voltage (positive voltage) for CCD bias from the system power supply voltage VDD and the output voltage of the charge pump 42 for generating a low voltage based on the control of the boosting control circuit 41. And supplies this to the CCD load.
[0053]
The charge pump 43 also basically has a charge pump circuit illustrated in FIG. 6 and includes a switching transistor, a pumping capacitor, an output capacitor, a timing adjustment circuit, a CMOS inverter, and the like. It is provided with. A part of the configuration for generating the positive voltage is different. For example, the switching transistor is constituted by a P-channel MOS transistor.
[0054]
Further, a buffer circuit of the type shown in FIG. 3 (hereinafter referred to as a tr / tf buffer circuit) B2 is provided. Specifically, like the low-voltage generation charge pump 42, the charge pump 42 is provided as a buffer circuit for a pumping clock input to a pumping capacitor C1a externally attached to the present CCD driver. Therefore, even in a circuit such as the high-voltage generation charge pump 43 in which the scale of a constituent transistor itself is large in order to handle a high voltage, only a small circuit configuration is added as a buffer circuit, and the through current is reduced. Can be suitably prevented.
[0055]
In the vertical blanking period, the vertical drive circuit 44 converts the CCD vertical transfer clock signal input from the timing generation circuit to a predetermined level based on the system power supply voltage VDD and the output voltage of the low-voltage generation charge pump 42. (A ternary level including a negative voltage) and supplies this to the CCD load as a vertical transfer pulse. Due to the application of the vertical transfer pulse, the electric charge for one screen generated in the imaging unit of the CCD is transferred to the accumulation unit of the CCD.
[0056]
The vertical drive circuit 44 includes the tr / tf buffer circuit B2 as an output buffer circuit. Therefore, as described above, the through current can be suitably prevented by adding a small circuit configuration as a buffer circuit of a circuit having a relatively low operation frequency, such as in the vertical drive circuit 44.
[0057]
Further, the electronic shutter drive circuit 45 changes the electronic shutter clock signal input from the timing generation circuit to a predetermined level based on the system power supply voltage VDD and the output voltage of the low voltage generation charge pump 42 during the light accumulation period. This is a circuit that converts the signal and supplies it to the CCD load as an electronic shutter pulse. By the application of the electronic shutter pulse, the charge of the CCD imaging unit is discharged to the drain, and a so-called electronic shutter operation is performed.
[0058]
The electronic shutter drive circuit 45 has the tr / tf buffer circuit B2 as its output buffer circuit, similarly to the vertical drive circuit 44. Therefore, as a buffer circuit of a circuit having a low operation frequency, such as the electronic shutter drive circuit 45, the through current can be suitably prevented by adding a slight circuit configuration.
[0059]
According to the driver including the buffer circuit of the present embodiment configured as described above, the following effects can be obtained.
(1) A buffer circuit used for each of the constituent circuits in the driver is selectively used for the AND / OR buffer circuit B1 and the tr / tf buffer circuit B2. Therefore, it is possible to obtain a reliable operation or reduce an increase in the circuit scale while reducing power consumption of a circuit in the driver.
[0060]
The above embodiment can be implemented in the following modes.
The AND / OR buffer circuit B1 and the tr / tf buffer circuit B2 may be used in circuits other than the charge pumps 42 and 42 and the drive circuits 44 and 45 in the driver.
[0061]
The example in which the AND / OR buffer circuit B1 and the tr / tf buffer circuit B2 are applied to a driver for driving a frame transfer CCD has been described. However, the driver including the buffer circuit according to the present invention is an interline CCD. Can be similarly applied to a driver for driving.
[0062]
Further, the driver including the buffer circuit according to the present invention is not limited to the driver for driving the CCD image sensor, and can be applied to any IC including the buffer circuit. That is, a driver having a buffer circuit in which a plurality of functional circuits having different operation frequencies and handled voltages and a buffer circuit performing a predetermined buffer operation in each of the circuits is mounted as a one-chip IC. By using the AND / OR type buffer circuit B1 and the tr / tf type buffer circuit B2 properly according to the operation frequency of the functional circuit, the voltage handled by the functional circuit, and the like, it is possible to obtain the same effects as in the above embodiment.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a first embodiment of a buffer circuit according to the present invention.
FIG. 2 is a timing chart showing the operation of the circuit of the embodiment.
FIG. 3 is a circuit diagram showing a buffer circuit according to a second embodiment of the present invention;
FIG. 4 is a timing chart showing the operation of the circuit of the embodiment.
FIG. 5 is a block diagram schematically showing a configuration of a driver including a buffer circuit according to the present invention as a third embodiment.
FIG. 6 is a circuit diagram showing an example of the charge pump circuit of the embodiment.
FIG. 7 is a circuit diagram showing a configuration of a conventional buffer circuit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Input terminal, 2 ... Output terminal, 3 ... Inverter circuit, 10 ... Output stage CMOS inverter circuit, 20, 30 ... Timing adjustment circuit, 42 ... Low voltage generation charge pump, 43 ... High voltage generation charge pump, 44 … Vertical drive circuit, 45… electronic shutter drive circuit, TRn… N-channel type MOS transistor, TRp… P-channel type MOS transistor.

Claims (3)

A driver including a buffer circuit in which a plurality of functional circuits having different operation frequencies and voltages to be handled and a buffer circuit performing a predetermined buffer operation in each of the circuits are mounted as a one-chip semiconductor integrated circuit device. ,
Among the functional circuits, a functional circuit having a high operation frequency includes, as the buffer circuit, an output stage including a CMOS inverter circuit in which a P-channel MOS transistor and an N-channel MOS transistor are connected in series; A first timing adjustment circuit that generates a switching signal for turning on the P-channel MOS transistor based on the input signal during a period in which the transistor is off;
Among the functional circuits, a functional circuit whose operation frequency is low or whose voltage is high is an output stage including, as the buffer circuit, a CMOS inverter circuit in which a P-channel MOS transistor and an N-channel MOS transistor are connected in series. Delaying the on-timing of the P-channel MOS transistor to make its on-period shorter than the off-period of the N-channel MOS transistor, and delaying the on-timing of the N-channel MOS transistor to reduce its on-period; A driver having a buffer circuit, comprising: a buffer circuit having a second timing adjustment circuit that generates a switching signal shorter than an off period of a P-channel MOS transistor based on an input signal. The first timing adjustment circuit is configured to include a parallel circuit of an AND circuit and an OR circuit that input the input signals to one input terminal and input the other output signals to the other input terminals, respectively. The output signal of the AND circuit is applied to the gate of the N-channel MOS transistor of the corresponding CMOS inverter circuit, and the output signal of the OR circuit is applied to the gate of the P-channel MOS transistor of the CMOS inverter circuit. Yes,
The second timing adjustment circuit includes a first inverter circuit having a large fall time constant at the time of signal inversion to delay the on-timing of the P-channel MOS transistor; driver comprising a buffer circuit according to claim 1 constituted by a second inverter circuit rise time constant at the time of signal inversion in order to delay the timing is set larger. A driver comprising the buffer circuit according to claim 1 or 2 ,
The driver is a device that drives a CCD image sensor,
The frequently operated functional circuit is a first charge pump that generates a pulse voltage of a pulse used for the charge transfer operation of the CCD, and a buffer circuit used for the charge pump is a pump circuit of the charge pump. A circuit that delays the pumping clock input to the capacitor,
The functional circuit whose operation frequency is low or whose voltage is high is a circuit that generates and outputs a pulse used for the charge transfer operation of the CCD, or a second charge pump that boosts and generates a bias voltage of the CCD. A buffer circuit used for a circuit for generating and outputting a pulse used for the charge transfer operation is a circuit for level-converting a separately applied timing clock based on an output voltage of the first charge pump; A buffer circuit used in the charge pump of (1), wherein the buffer circuit delays a pumping clock input to a pumping capacitor of the charge pump.

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