JP2006129127A - Voltage supply circuit and solid-state image pickup device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a voltage supply circuit that operates with low power consumption and has little noise occurrence, and a solid-state image pickup device that uses the voltage supply circuit. <P>SOLUTION: This voltage supply circuit comprises a clock buffer circuit part 200 for buffering a first clock and generating a second clock, a boosting circuit part 100 for boosting input voltage to prescribed voltage under the control of by the second clock and outputting the prescribed voltage as boosting power, a voltage detection circuit part 300 for detecting the level of boosted voltage outputted from the boosting circuit, and a control circuit part 400 for controlling input of the first clock to the clock buffer circuit part in accordance with a detection result by the voltage detection circuit part. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a voltage supply circuit and a solid-state imaging device using the voltage supply circuit.

  Conventionally, charge pump type booster circuits are used in high voltage generation circuits for liquid crystal displays such as video cameras and digital cameras. This charge pump type booster circuit connects a plurality of pumping packets composed of one capacitor and a diode in series, and generates a voltage higher than, for example, the power supply voltage VDD for the LSI chip by boosting each pumping packet. Is.

  For example, FIG. 5 is a block configuration diagram illustrating a configuration example of a general booster circuit. As can be seen from FIG. 5, it has a charge pump type booster circuit composed of capacitors C1 to C4 and diodes D1 to D5, and a clock buffer unit composed of a plurality of inverter type buffer circuits I1 to I5. In each inverter type buffer circuit, VDD indicates a power supply, and VSS indicates a ground.

In such a booster circuit, for example, when a clock signal is input to the capacitor C1, the voltage of the node ND1 is boosted by the voltage VDD (ideal value) by capacitive coupling of the capacitor C1. Ideally, the voltage (V1) of the node ND1 at that time is
V1 = VDD + α
It becomes. Α is the initial potential of the node ND1. In addition, the initial potential α varies depending on changes in threshold voltages of the diodes D1 to D4, initial states, and the like at the nodes ND1 to ND4. Although the case where the positive side voltage is boosted has been described here, when the negative side voltage is boosted (= stepped down), the voltage at each node is knocked down by the same clock buffer unit.

  FIG. 6 is a circuit configuration diagram showing a schematic configuration of a solid-state imaging device using a conventional voltage supply circuit, for example, a solid-state imaging device disclosed in Japanese Patent Laid-Open No. 11-26740. This solid-state imaging device includes a solid-state imaging device (CMOS imager) 10, a voltage supply circuit 20 for supplying a voltage to the solid-state imaging device 10, and an external capacitor C.

Next, a more detailed configuration of the conventional example will be described. Each pixel of the solid-state imaging device 10 (2 × 2 four pixels Pxl11, Pxl12, Pxl21, and Pxl22 in the illustrated example) transfers the photodiode PD that is a photoelectric conversion unit and the signal of the photodiode PD to the detection unit FD. A transistor M1, an amplification transistor M2 for amplifying the detection signal of the photodiode PD, a reset transistor M3 for resetting the detection signal of the detection unit FD, and a row selection transistor M4 for selecting each row. A vertical scanning unit 50, a level shift unit 51, and a horizontal scanning circuit unit 70 for driving the pixels are arranged. In the level shift unit 51, an output VDDH (> VDD) from the voltage supply circuit 20 is connected as a level shifter power source for driving the gate voltage of the row selection transistor M4. That is, in this conventional example, the output of the level shifter for driving the gate of the row selection transistor M4 is a binary value of VDDH / VSS. Signals from the pixels Pxl11 to Pxl22 are output from the amplifier 4 through the vertical signal lines 1 and 2, the noise cancellation circuit 60 for canceling the characteristic variation between the pixels, and the horizontal signal line 3. Here, the voltage supply circuit 20 is constituted by a charge pump type booster circuit having a configuration similar to that shown in FIG. 5, for example, and an external capacitor C for holding a voltage is connected to its output terminal. Further, as described above, the level shifter 51 is connected. By using the voltage supply circuit 20 having such a configuration, a power supply voltage or a voltage other than the ground can be easily supplied to the solid-state imaging device 10.
JP-A-11-26740

  However, in the conventional booster circuit configured as described above, if the capacitor of the booster circuit is knocked up or down using a clock having the VDD voltage width, the VDD width (VDD-VSS) is reached even if the desired potential is reached. Even if the potential change occurs and the voltage is controlled by the regulator, the potential moves with the VDD width. That is, unnecessary power is generated by driving the capacitor and the clock buffer unit unnecessarily. Furthermore, fluctuations in the power supply or ground due to the drive also cause noise in the peripheral circuits.

  The present invention has been made to solve the above-described problems in the conventional voltage supply circuit (boost circuit), and uses a voltage supply circuit with low power consumption and low noise generation, and the voltage supply circuit. An object is to provide a solid-state imaging device.

  In order to solve the above problem, the invention according to claim 1 is directed to a clock buffer unit that buffers the first clock to generate the second clock, and a predetermined voltage under the control of the second clock under the control of the second clock. According to the detection result by the voltage detection unit, the voltage detection unit for detecting the level of the boost or step-down voltage output from the voltage boosting circuit unit, A voltage supply circuit is configured with a control circuit unit that controls input of the first clock to the clock buffer unit.

  According to a second aspect of the present invention, in the voltage supply circuit according to the first aspect, the step-up circuit unit includes a plurality of series-connected diodes in which an input voltage is supplied to an anode and a cathode is connected to an anode of a diode in a subsequent stage. And a plurality of capacitors, one end of which is supplied with the second clock and the other end of which is connected to a node between the series-connected diodes. .

  According to a third aspect of the present invention, in the voltage supply circuit according to the first aspect, the clock buffer unit is connected between the first power supply and the second power supply from one terminal to the other by the voltage applied to the control terminal. Two transistors whose conduction to the terminal is controlled are connected in series, and an output unit that outputs the second clock from a node between the two transistors and the control terminal of the transistor, the 2 And a buffer circuit including two input portions to which the first clocks whose phases are shifted so that two transistors are turned on at different timings are input.

  According to a fourth aspect of the present invention, in the voltage supply circuit according to the first aspect, the voltage detection unit includes a comparator that compares a boosted or stepped-down voltage level output from the booster circuit unit with a reference level. To do.

  According to a fifth aspect of the present invention, in the voltage supply circuit according to any one of the first to fourth aspects, the output of the booster circuit unit is set to a voltage different from the predetermined voltage according to an external input signal. A switching element to be fixed is further provided.

  The invention according to claim 6 is a photodiode formed on a semiconductor substrate, a transfer transistor for transferring a signal of the photodiode, an amplification transistor for amplifying the signal transferred by the transfer transistor, A plurality of unit pixels each having at least an addressing means for activating the amplifying transistor and a reset transistor for discharging the transferred signal are arranged in a matrix, and the pixel unit is driven. The voltage supply circuit according to any one of claims 1 to 5, which supplies the voltage, is formed on one chip to constitute a solid-state imaging device.

  According to a seventh aspect of the present invention, in the solid-state imaging device according to the sixth aspect, at least one of the reset transistor and the transfer transistor has the gate supplied with the boosted or step-down voltage from the voltage supply circuit. It is characterized by.

  The invention according to claim 8 is a photodiode formed on a semiconductor substrate, a transfer transistor for transferring a signal of the photodiode, an amplification transistor for amplifying the signal transferred by the transfer transistor, A plurality of unit pixels each having at least an address transistor that activates the amplification transistor and a reset transistor that discharges the transferred signal are arranged in a matrix, and the pixel unit is driven. The voltage supply circuit according to any one of claims 1 to 5, which supplies the voltage, is formed on one chip to constitute a solid-state imaging device.

  According to a ninth aspect of the present invention, in the solid-state imaging device according to the eighth aspect, at least one of the address transistor, the reset transistor, or the transfer transistor is connected to the gate from the voltage supply circuit. A step-up or step-down voltage is input.

  According to the first aspect of the present invention, it is possible to detect the level of the voltage boosted or stepped down by the booster circuit unit, and to control the supply of the second clock to the booster circuit unit according to the detection result. Therefore, unnecessary boosting or step-down operation in the boosting circuit unit can be suppressed, and reduction of current consumption and generation of noise can be suppressed. According to the invention of claim 2, it is possible to obtain a boosted or step-down voltage by a charge pump method. According to the third aspect of the present invention, since no through current flows through the buffer circuit, current consumption can be reduced. According to the fourth aspect of the present invention, it is possible to control the supply of the second clock to the booster circuit unit in accordance with the boosted or stepped down voltage level output from the booster circuit unit. According to the fifth aspect of the present invention, the output potential of the booster circuit can be stabilized when the operation of the voltage supply circuit is stopped.

  According to the sixth aspect of the invention, a solid-state imaging device with low power consumption and low noise can be realized. According to the seventh aspect of the invention, it is possible to drive at least one of the reset transistor and the transfer transistor with a step-up or step-down voltage different from the power supply voltage. According to the invention of claim 8, it is possible to realize a solid-state imaging device with low power consumption and low noise. According to the ninth aspect of the present invention, it is possible to drive at least one of the address transistor, the reset transistor, and the transfer transistor with a boosted voltage or a reduced voltage different from the power supply voltage.

  Next, the best mode for carrying out the present invention will be described.

  First, an embodiment of a voltage supply circuit according to the present invention will be described. This embodiment corresponds to the embodiment of the invention according to claims 1 to 5, and FIG. 1 is a block diagram showing the configuration of the voltage supply circuit according to this embodiment. The voltage supply circuit according to this embodiment includes a booster circuit unit 100 that boosts an external power supply voltage, and a clock that holds the voltage at a predetermined level by supplying a driving clock as a second clock to the booster circuit unit 100. A buffer circuit unit 200; a voltage detection circuit unit 300 for detecting a boosted voltage level output from the booster circuit unit 100; and a first detection circuit for the clock buffer circuit unit 200 according to a detection result by the voltage detection circuit unit 300. The control circuit unit 400 controls the input of the basic clock, which is the first clock, and the switching element SW for fixing the output of the booster circuit unit 100 when the operation of the voltage supply circuit is stopped.

  Next, a more detailed configuration of the voltage supply circuit of this embodiment will be described. First, the booster circuit unit 100 has a general configuration, for example, a charge pump type booster circuit composed of pumping capacitors C1 to C4 and diodes D1 to D5, like the booster circuit unit shown in FIG. ing. The voltage detection circuit unit 300 monitors the output voltage level of the booster circuit unit 100, and includes a level shift circuit 310 and a comparator 320. Then, the output voltage level of the booster circuit unit 100 is converted to an appropriate level by level shifting by the level shift circuit 310, and the level after this conversion is converted to a desired boosted voltage desired to be obtained by the booster circuit unit 100 by the comparator 320. And a comparison result is output to the control circuit unit 400.

  The control circuit unit 400 is composed of a control logic circuit and controls the input of the basic clock (CK1, CK2 clock) to the clock buffer circuit unit 200 based on the comparison result in the voltage detection circuit unit 300. The clock buffer circuit unit 200 includes two buffer circuits 210 and 220, and drives (pumps) the pumping capacitors C1 to C4 of the booster circuit unit 100. Each of the buffer circuits 210 and 220 includes a plurality of buffers 210a and 210b; 220a and 220b connected in multiple stages, and the configuration of at least the final stage buffers 210b and 220b is, for example, as shown in FIG. The booster circuit unit 100 includes two MOS transistors connected in series whose conduction is controlled between a first power supply VDD and a second power supply VSS by a voltage applied to a gate terminal. 2 is supplied from the control circuit unit 400 to the gate terminal of each MOS transistor so that the two MOS transistors are turned on at different timings and the output unit that outputs the second clock supplied to ), The first clocks CK1-1 (CK2-1) and CK1-2 (CK2-2) whose phases are shifted are input to 210c and 220c. At least the final stage of the buffer 210b of the circuit 210, 220 has a configuration in which no through current flows in the 220b. In this embodiment, the buffer is described as being connected in two stages. However, the gate capacity of the buffers 210b and 220b increases according to the capacity connected to the subsequent stage of the buffer circuits 210 and 220. Thus, the number of buffers 210a and 220a may be increased.

  Furthermore, when the standby mode is set (when the STBY input to the control circuit unit 400 is turned ON), the switching element SW outputs the output by fixing the output of the booster circuit unit 100 to the second voltage. Stabilize. In the standby mode, the power supply voltage VDD itself is supplied to the voltage supply circuit and the subsequent circuit, but the power supply to the subsequent circuit is cut off by stopping the operation of the voltage supply circuit. is there.

  An external capacitor C0 for holding the output voltage is connected to the output side of the voltage supply circuit having this configuration. In this embodiment, an example is shown in which two basic clocks (CK1, CK2) whose phases are shifted are used as the first clock output from the control circuit unit 400. Since is not directly related to the characteristics of the present invention, description thereof is omitted.

  Next, the operation of the voltage supply circuit having the above configuration will be described. The voltage detection circuit unit 300 level-shifts the voltage boosted by the boosting circuit unit 100 by the level shift circuit 310 and then compares the voltage with the reference voltage VREF by the comparator 320, and the comparison result is sent to the control circuit unit 400. Output. When the comparison result indicates that the desired voltage has not been reached, the control circuit unit 400 continues to supply the basic clock to the clock buffer circuit unit 200 and continues the boosting operation by the boosting circuit unit 100. On the other hand, when the comparison result indicates that the desired voltage has been reached, the control circuit 400 stops the supply of the basic clock to be output to the clock buffer circuit unit 200, thereby causing the boosting circuit unit 100 to perform the boosting operation. Stop.

  As described above, in the voltage supply circuit according to the present embodiment, after reaching a desired voltage, the unnecessary pumping operation by the booster circuit unit 100 is stopped, thereby reducing the power consumption and generating less noise. A voltage supply circuit can be realized.

  FIG. 3 is a block diagram showing a configuration example of a booster circuit unit 100 ′ when the voltage supply circuit shown in FIG. 1 is used as a step-down circuit. When it is desired to step down the input voltage (power supply voltage), it is possible to realize a voltage supply circuit having substantially the same circuit configuration and different polarities by changing the step-up circuit unit to the configuration shown in FIG. .

  Next, examples of the solid-state imaging device according to the present invention will be described. This embodiment corresponds to the embodiments of the invention according to claims 6 to 9, and the voltage supply circuit described in the first embodiment is applied as the voltage supply circuit of the solid-state imaging device described in the prior art. It is. FIG. 4 is a block diagram illustrating a configuration of the solid-state imaging device according to the present embodiment. As described in the prior art, this solid-state imaging device includes a solid-state imaging element 10, a voltage supply circuit 20 ', and an external capacitor C. The solid-state imaging element 10 and the voltage supply circuit 20' It is formed on one chip.

  The solid-state imaging device 10 has a configuration similar to that of a general CMOS imager, and includes a photodiode PD which is a photoelectric conversion unit, a transfer transistor M1 for transferring a signal of the photodiode PD to a detection unit FD, and the photo diode A pixel composed of an amplification transistor M2 for amplifying the detection signal of the diode PD, a reset transistor M3 for resetting the detection signal of the detection unit FD, and a row selection transistor M4 for selecting each row (in FIG. 4, for convenience, 2 × 2 four pixels Pxl11, Pxl12, Pxl21, and Pxl22), a vertical scanning circuit unit 50 that outputs signals for driving pixels in each row, and a signal output from the vertical scanning circuit unit 50 A level shift unit 51 for shifting the level to a level necessary for driving each related transistor of each pixel, and a characteristic variation between the pixels. A noise cancel circuit 60 for canceling, a horizontal scanning circuit 70, an amplifier 4.

  The voltage supply circuit 20 ′ supplies the level-shifted voltage VDDH [> VDD (power supply voltage)] to the level shift unit 51 of the solid-state imaging device 10, and here, the gate of the row selection transistor M4. Is used to level-shift the drive voltage applied to the level from VSS (ground voltage) to VDDH.

  In the solid-state imaging device configured as described above, a signal from each pixel is amplified through the vertical signal lines 1 and 2, the noise cancel circuit 60 for canceling the characteristic variation between the pixels, and the horizontal signal line 3. 4 is output.

  By using the voltage supply circuit according to the present invention as a voltage supply source to the solid-state imaging device as in the above embodiment, it is possible to easily supply a voltage other than the power supply voltage VDD or the ground voltage VSS, and to reduce power consumption. It is possible to realize a solid-state imaging device with electric power and less noise.

  In this embodiment, the row selection (address) transistor M4 is used as the address means for activating the amplification transistor. However, the present invention is not limited to this as long as it has an equivalent function. In addition, the terminal for shifting the drive voltage level to the VDDH level has been described as the gate of the row selection transistor M4. Good. Further, although the voltage supplied from the voltage supply unit 20 ′ is set to VDDH at the time of ON, the voltage level after the level shift output from the level shift unit 51 is VDD to VSSL (where VSSL <VSS ) May be configured to generate VSSL and supplied to the level shift unit 51. Further, the level shift unit 51 is not limited to the level shift with respect to the two voltage values of the power supply voltage and the ground voltage, and may be configured to be applicable to the level shift with respect to multiple values (three or more values).

It is a block block diagram which shows the Example of the voltage supply circuit which concerns on this invention. FIG. 2 is a circuit configuration diagram illustrating a configuration of a clock buffer circuit unit in the voltage supply circuit illustrated in FIG. 1 and a waveform diagram for explaining an operation. FIG. 6 is a circuit configuration diagram showing a modification of the booster circuit unit in the voltage supply circuit shown in FIG. 1. It is a circuit block diagram which shows the Example of the solid-state imaging device concerning this invention. It is a block block diagram which shows the structure of the conventional voltage supply circuit (boost circuit). It is a circuit block diagram which shows the structural example of the solid-state imaging device using the conventional voltage supply circuit.

Explanation of symbols

1, 2 Vertical signal line 3 Horizontal signal line 4 Amplifier
10 Image sensor
20, 20 'voltage supply circuit
50 Vertical scanning circuit
51 Level shift section
60 Noise cancellation circuit
70 Horizontal scanning circuit
100, 100 'Booster circuit
200 Clock buffer circuit
210 and 220 buffer circuits
300 Voltage detection circuit
310 Level shift circuit
320 comparator
400 Control circuit

Claims (9)

  A clock buffer unit that buffers the first clock and generates a second clock, and a booster circuit unit that boosts or steps down the input voltage to a predetermined voltage under the control of the second clock and outputs the boosted power A voltage detection unit that detects a level of the boosted or stepped-down voltage output from the booster circuit unit, and controls input of the first clock to the clock buffer unit according to a detection result by the voltage detection unit A voltage supply circuit comprising: a control circuit unit;   The step-up circuit unit is supplied with an input voltage at the anode, a plurality of diodes connected in series with the cathode connected to the anode of the diode in the subsequent stage, the second clock supplied to one end, and the other end connected to the series 2. The voltage supply circuit according to claim 1, which is a charge pump type booster circuit having a plurality of capacitors connected to a node between the connected diodes.   In the clock buffer unit, two transistors whose conduction from one terminal to the other terminal is controlled in series by a voltage applied to a control terminal are connected in series between a first power source and a second power source. An output unit that outputs the second clock from a node between the two transistors; and the two that are supplied to the control terminal of the transistor and that are out of phase so that the two transistors are conductive at different timings. The voltage supply circuit according to claim 1, further comprising: a buffer circuit including an input unit to which the first clock is input.   The voltage supply circuit according to claim 1, wherein the voltage detection unit includes a comparator that compares a boosted or stepped-down voltage level output from the boosting circuit unit with a reference level.   5. The switching device according to claim 1, further comprising a switching element that fixes an output of the booster circuit unit to a voltage different from the predetermined voltage in accordance with an input signal from the outside. Such a voltage supply circuit.   A photodiode formed on a semiconductor substrate, a transfer transistor for transferring a signal of the photodiode, an amplification transistor for amplifying a signal transferred by the transfer transistor, and an address for activating the amplification transistor A plurality of unit pixels each having at least a unit and a reset transistor that discharges the transferred signal, and supplies a driving voltage to the pixel units arranged in a matrix. A solid-state imaging device, wherein the voltage supply circuit according to any one of 1 to 5 is formed on one chip.   7. The solid-state imaging device according to claim 6, wherein at least one of the reset transistor and the transfer transistor receives the boosted or stepped down voltage from the voltage supply circuit at the gate thereof.   A photodiode formed on a semiconductor substrate, a transfer transistor for transferring a signal of the photodiode, an amplification transistor for amplifying a signal transferred by the transfer transistor, and an address for activating the amplification transistor A plurality of unit pixels each including at least a transistor and a reset transistor for discharging the transferred signal supply a plurality of pixel units arranged in a matrix and a voltage for driving to the pixel units. A solid-state imaging device, wherein the voltage supply circuit according to any one of 1 to 5 is formed on one chip.   9. The boosted or stepped down voltage from the voltage supply circuit is input to a gate of at least one of the address transistor, the reset transistor, or the transfer transistor according to claim 8. Solid-state imaging device.

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