JP5157466B2 - Solid-state imaging device and electronic camera - Google Patents

Description

  The present invention relates to a solid-state imaging device and an electronic camera.

  In recent years, electronic cameras such as video cameras and still image still cameras have been widely used. In these electronic cameras, image sensors such as CCD type and amplification type are used. In these image sensors, a plurality of pixels having photoelectric conversion units that generate signal charges according to the amount of incident light are arranged in a matrix in the row direction (generally in the horizontal direction) and in the column direction (generally in the vertical direction). Yes.

  In the amplification type image sensor, the signal charge generated and stored in the photoelectric conversion unit of the pixel is guided to the amplification unit provided in the pixel, and an electric signal corresponding to the signal charge is output from the pixel. The pixels are connected to the vertical signal line for each column. The vertical signal line receives the electrical signal from the pixel and outputs it to the horizontal signal line. The electrical signal transferred to the horizontal signal line is output to the outside of the image sensor via the output amplifier.

  As an amplification type image sensor, for example, an image sensor using a junction field effect transistor in an amplification unit (Patent Document 1), a CMOS image sensor using a MOS transistor in an amplification unit (Patent Document 2), etc. are proposed. ing.

  The image sensor is mounted on an electronic camera after being incorporated into a package or the like to become a solid-state imaging device. As components of the solid-state imaging device, in addition to the image sensor, a component for reducing noise, an electronic component for driving the image sensor, and the like may be incorporated.

  In the amplification type image sensor, a pixel current source that generates a constant current is arranged in each vertical signal line (for example, reference numeral 44 in FIG. 6 and reference numeral 117 in FIG. 2 in Patent Document 2). . As is well known, the pixel resets the accumulated charge and outputs a pixel reset output level. Further, the pixel outputs a pixel signal corresponding to the charge accumulated after being reset. These electric signals change the voltage of the vertical signal line from the pixel reset output level to the pixel signal output level. Due to this variation, the image sensor obtains image information. The pixel current source operates as a load of the source follower amplifier of the pixel, and greatly shortens the time until the voltage of the vertical signal line reaches the pixel reset level or the pixel signal output level. In recent years, the number of pixels of image sensors tends to increase more and more. As the number of pixels increases and the total number of electrical signals read out increases, the technology for shortening this time becomes more and more important. A specific pixel current source circuit and a configuration of a pixel current source control circuit for causing a constant current to flow through the pixel current source are disclosed in Patent Document 3, for example.

  However, such a pixel current source may generate a constant current in principle, but the current value may fluctuate. For this reason, the electric signal from the pixel output to the vertical signal line cannot be read out correctly.

  This is due to fluctuations in the voltage supplied to the pixel current source. For example, in Patent Document 3, a MOS transistor is used as the pixel current source. However, when the gate voltage of the MOS transistor varies, the current flowing through the vertical signal line also varies.

  The factors causing this voltage fluctuation are as follows. First, the influence of noise can be mentioned. Many wirings are arranged around the pixel current source. If noise is included in these wirings, the voltage supplied to the pixel current source may be coupled and fluctuate. In such a case, the obtained image is a low-quality image including horizontal streak-like random noise.

  Second, when an electrical signal from a pixel read out to a certain vertical signal line is relatively large (that is, a signal from a pixel irradiated with light from a bright subject), the pixel arranged in an adjacent vertical signal line It is conceivable that the current value of the electric current source fluctuates. In such a case, smear occurs, and the noise is an image with low image quality that is included in the row direction.

  Therefore, as a means for easily solving by those skilled in the art, a configuration in which a capacitor is added to the wiring of the voltage supplied to the pixel current source can be considered. It is well known to electrical circuit engineers that capacitance absorbs voltage fluctuations. For example, Non-Patent Document 1 discloses a configuration that uses a capacitor to absorb voltage fluctuations.

  That is, voltage fluctuations in the AC component due to noise are absorbed by the capacitance, and thereby a high-quality image with reduced noise can be obtained. Therefore, this capacitance has an effect of “reducing voltage fluctuation” directly, but has an effect of “absorbing AC component noise” substantially.

JP-A-11-177076 JP 2004-129015 A JP-A-8-18866 CMOS analog circuit design course (held on August 24, 2001) 107 Lecturer: Kenji Taniguchi (Osaka University Faculty of Engineering)

  However, in order to absorb the voltage fluctuation in this way, a capacitor having a large capacitance value of about 1 μF is required. When a capacitor having such a large capacitance value is connected to a wiring for supplying a voltage to the pixel current source (hereinafter, this wiring is referred to as a “supply wiring”), from when the electronic camera is turned on until an imaging operation is possible This causes a new problem that the time (shutter time lag) must be lengthened.

  Here, a general single-lens digital camera is considered. Since a single-lens digital camera has an optical viewfinder and is provided with a dedicated sensor for AF (autofocus) and AE (automatic exposure), it is not necessary to always operate the image sensor. For this reason, the image sensor is generally activated after the shutter button is pressed, the imaging operation is performed, and the power supply of the imaging element is stopped after the imaging is completed.

  However, while the capacitor is charged with electric charges, the voltage gradually changes until the voltage of the supply wiring reaches a predetermined voltage. Therefore, the current generated by the pixel current source gradually increases until the voltage of the supply wiring becomes predetermined. Even if an imaging operation is performed during this time, a normal image cannot be obtained. Therefore, it is necessary for the electronic camera to increase the time from when the release button is pressed until the imaging operation is performed. That is, the camera has a long shutter time lag.

  Even if the capacitance value of the capacitor is small, there is an effect of absorbing voltage fluctuations according to the value. However, if the fluctuations in the voltage of the supply wiring described above are reduced to the extent that many users are satisfied, the shutter time lag of the electronic camera becomes longer. In recent years, users of electronic cameras are not sensitive to image quality even if they are not high-end users.

  Thus, the effect of absorbing the voltage fluctuation of the supply wiring and the shortening of the shutter time lag have a trade-off relationship.

  The present invention has been made in view of such a problem, and provides a solid-state imaging device and an electronic camera in which voltage fluctuation of a supply wiring is sufficiently absorbed and a shutter time lag is shortened.

  The inventor has found and invented a configuration in which the time for charging a charge in the capacitor for absorbing voltage fluctuation is extremely shortened.

Therefore, the solid-state imaging device according to the first aspect of the present invention is connected to the pixels for each pixel column, and a plurality of pixels that are arranged two-dimensionally in the row direction and the column direction and output a signal corresponding to the amount of incident light. A plurality of vertical signal lines for receiving the signals from the pixels; a pixel current source provided for each vertical signal line for supplying a constant current to the vertical signal lines; and the pixel current source connected to the pixel current source by a supply wiring A pixel current source control circuit for supplying a first voltage to the first electrode, one electrode is connected to the supply wiring, the first voltage is supplied, and the other electrode is supplied with a ground level voltage. has a capacity large enough to absorb the variation, and a charging circuit of the second voltage is connected to one electrode of the capacitor is supplied to the capacitor to charge said capacitor, said charging circuit, power-on Sometimes of the capacity Position is rapidly charge the capacitance to a substantially equal level to the second voltage, characterized in that it stops its operation after completion of charging.

A solid-state imaging device according to a second aspect of the present invention includes, in the first aspect, an image sensor made of a silicon substrate, wherein at least the pixel, the vertical signal line, the supply wiring, and the pixel current source are The image sensor is provided, and the capacitor is an external component provided outside the image sensor.

The solid-state imaging device according to a third aspect of the present invention is the solid-state imaging device according to the first or second aspect, wherein the pixel generates and stores a charge corresponding to incident light, and the charge is supplied to the gate electrode. And an amplifying unit that outputs a signal corresponding to the potential of the gate electrode, the pixel current source is an NMOS transistor, the supply wiring is connected in common to the gate electrode of each NMOS transistor, and the pixel A current mirror circuit is configured by the current source and the pixel current source control circuit. The pixel current source control circuit generates a constant current, and a voltage corresponding to the constant current is used as the first voltage to gate the NMOS transistors. It supplies to an electrode, It is characterized by the above-mentioned.

In the solid-state imaging device according to the fourth aspect of the present invention, in any one of the first to third aspects, the pixel current source control circuit supplies the first voltage to the pixel current source while the pixel current source control circuit is on. The charging circuit includes a first changeover switch unit that supplies a voltage lower than the first voltage to the pixel current source, and the charging circuit includes the capacitor when the first changeover switch unit shifts from an off state to an on state. The capacitor is charged until the potential becomes a level substantially equal to the second voltage, and the operation is stopped after the charging is completed.

The solid-state imaging device according to a fifth aspect of the present invention is the solid-state imaging device according to any one of the first to fourth aspects, wherein the charging circuit includes the voltage generation circuit that generates the second voltage and the second to the capacitor. And a switch for switching a voltage supply state, and the capacitor is charged by turning on the switch for a predetermined time.

The solid-state imaging device according to a sixth aspect of the present invention is the solid-state imaging device according to the fifth aspect, wherein the charging circuit further includes a comparison circuit that detects a potential of the one electrode of the capacitor, and is detected by the comparison circuit. When the potential becomes a predetermined voltage, the switch is turned off to stop the operation.

An electronic camera according to a seventh aspect of the present invention includes a plurality of pixels that are two-dimensionally arranged in a row direction and a column direction and that output a signal corresponding to the amount of incident light, and are connected to the pixel for each pixel column. A plurality of vertical signal lines received from the pixel signal source, a pixel current source that is provided for each of the vertical signal lines and supplies a constant current to the vertical signal line, and a supply wiring that commonly connects the gate electrodes of the NMOS transistors. A CMOS image sensor having at least a pixel current source control circuit connected to the supply wiring to form a current mirror circuit with the pixel current source and supplying a first voltage to the gate electrode of each NMOS transistor; electrode voltage of the ground level is supplied to said being connected to the supply line first voltage is supplied the other electrode, the power source electric And capacity size to absorb a variation of a charging circuit of the second voltage is connected to one electrode of the capacitor is supplied to the capacitor to charge said capacitor, imaging to output the signal from the pixel It has a control unit, the charging circuit, when the power is turned on, the solid-state imaging potential of the capacitance is the capacitance rapidly charged to a substantially equal level to the second voltage, and stops the operation after completion of charging A device is provided .

An electronic camera according to an eighth aspect of the present invention is the electronic camera according to the seventh aspect, wherein the pixel current source control circuit supplies the first voltage to the pixel current source when the pixel current source control circuit is in an on state, and supplies the pixel current source when the pixel current source control circuit is off. The charging circuit includes a first changeover switch unit that supplies a ground level voltage, and the charging circuit has a potential of the capacitor substantially equal to the second voltage when the first changeover switch unit shifts from an off state to an on state. The capacitor is charged until the level becomes equal, and the operation is stopped after the charging is completed, and the imaging control unit outputs a drive signal for operating the first changeover switch unit and the charging circuit.

  In the solid-state imaging device according to the present invention, the time required for charging a capacitor connected to a wiring for supplying a voltage to the pixel current source and absorbing a fluctuation in voltage is extremely shortened. Therefore, the present invention can provide an electronic camera with a reduced shutter time lag while reducing AC component noise.

  Hereinafter, an image sensor and an electronic camera using the image sensor according to the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a schematic block diagram showing an electronic camera 1 according to the first embodiment of the present invention. A photographing lens 2 is attached to the electronic camera 1. The photographing lens 2 is driven by a lens control unit 2a for focus and diaphragm. In the image space of the photographing lens 2, an imaging surface of an image sensor 30 that is one of the components of the solid-state imaging device 3 is arranged. In addition to the image sensor 30, the solid-state imaging device 3 includes a capacitor for absorbing noise (see reference numeral 50 in FIG. 4) and elements associated therewith, which will be described in detail later.

  The solid-state imaging device 3 is driven by a drive signal output from the imaging control unit 4 and outputs a signal. A signal output from the solid-state imaging device 3 is processed through the signal processing unit 5 and the A / D conversion unit 6 and then temporarily stored in the memory 7. The memory 7 is connected to the bus 8. The bus 8 is also connected with a lens control unit 2a, an imaging control unit 4, a microprocessor 9, a focus calculation unit 10, a recording unit 11, an image compression unit 12, an image processing unit 13, and the like. Although not shown in the drawing, the imaging control unit 4 is configured by a timing generator or the like, and supplies driving pulses and the like to each unit of the solid-state imaging device 3. An operation unit 9 a such as a release button is connected to the microprocessor 9. A recording medium 11a is detachably attached to the recording unit 11 described above.

  FIG. 2 is a schematic circuit diagram showing the configuration of the image sensor 30 mounted on the solid-state imaging device 3. The image sensor 30 is formed of a silicon substrate and is configured as a CMOS type image sensor. The image sensor 30 includes a plurality of pixels 20 that are two-dimensionally arranged in the row direction and the column direction and that output an electrical signal corresponding to the amount of incident light, and a peripheral circuit that outputs a signal from the pixel 20. . In the figure, the number of pixels indicates 16 pixels of 4 rows horizontally and 4 columns vertically. However, it is not limited to this. The pixel 20 outputs a signal in accordance with the drive signal for the peripheral circuit. A region where the pixels are two-dimensionally arranged is a pixel region 31.

  The peripheral circuit includes a vertical scanning circuit 21, a horizontal scanning circuit 22, drive signal lines 23 and 24 connected thereto, a vertical signal line 25 connected to a pixel for each pixel column and receiving an electrical signal from the pixel, a vertical signal A pixel current source 26 which is provided for each line 25 and supplies a constant current to the vertical signal line 25, a pixel current source control circuit (not shown in FIG. 2, see reference numeral 32 in FIG. 4), a pixel current source 26 and a pixel current source control A supply wiring (not shown in FIG. 2; see reference numeral 36 in FIG. 4) for supplying a voltage from the pixel current source control circuit to the pixel current source 26 and correlated double sampling provided for each vertical signal line 25 A circuit (CDS) 27, a horizontal signal line 28 for receiving a signal output from the correlated double sampling circuit 27, an output amplifier 29, and the like. The pixel current source 26 is indicated by a simplified symbol in this drawing, but a more detailed circuit will be described later.

  The vertical scanning circuit 21 and the horizontal scanning circuit 22 output drive signals based on commands from the imaging control unit 4 of the electronic camera 1. Each pixel 20 is driven by receiving a drive signal output from the vertical scanning circuit 21 from a predetermined drive signal line 23, and outputs a signal corresponding to incident light to the vertical signal line 25. There are a plurality of drive signals output from the vertical scanning circuit 21 and a plurality of drive signal lines 23 accordingly.

  The signal output from the pixel 20 is subjected to predetermined noise removal by the correlated double sampling circuit 27. A driving signal is output from the horizontal scanning circuit 22 via the driving signal line 24, and the signal is output to the outside via the horizontal signal line 28 and the output amplifier 29.

  FIG. 3 is a pixel circuit diagram in the image sensor 30. In this embodiment, each pixel 20 includes a transfer transistor Ta, a source follower amplification transistor Tb, a reset transistor Tc, a selection transistor Td, and a photodiode PD, as shown in FIG. Transistors Ta to Td are formed of N-channel MOS transistors. Therefore, when the gate becomes H level (high level), it is turned on, and when the gate becomes L level (low level), it is turned off. VDD is a power source.

  The photodiode PD as the photoelectric conversion unit generates and accumulates electric charges according to the amount of incident light. The accumulated charge is supplied to the gate (electrode) of the amplification transistor Tb when the transfer transistor Ta is turned on. The transfer transistor Ta is turned on / off by a drive signal φTG input to its gate (electrode). The drive signal φTG is output from the vertical scanning circuit 21 and applied to the gate of the transfer transistor Ta via the drive signal line 23. In addition, the charge is actually transferred to the floating diffusion FD that is electrically connected to the gate of the amplification transistor Tb.

  The amplifying transistor Tb generates and outputs an electrical signal corresponding to the potential due to the charge supplied to its gate (electrode).

  The selection transistor Td is turned on to electrically connect the pixel and the vertical signal line. The selection transistor Td outputs the electric signal generated by the amplification transistor Tb to the vertical signal line. The selection transistor Td is turned on / off by a drive signal φS input to its gate (electrode). The drive signal φS is output from the vertical scanning circuit 21 and applied to the gate of the selection transistor Td via the drive signal line 23.

  When the reset transistor Tc is turned on, the charge of the gate (and the floating diffusion portion) of the amplification transistor Tb is discharged, and the reset transistor Tc is reset. The reset transistor Tc is turned on / off by a drive signal φFDR input to its gate (electrode). The drive signal φFDR is output from the vertical scanning circuit 21 and applied to the gate of the reset transistor Tc via the drive signal line 23.

  The gates of the transfer transistors Ta arranged in the pixels 20 are commonly connected in the row direction. Similarly, the gates of the reset transistor Tc and the selection transistor Td are also commonly connected in the row direction. Then, the pixels 20 in the row direction are driven simultaneously. Accordingly, the pixels 20 arranged in the row direction simultaneously output electrical signals to the corresponding vertical signal lines 25.

  The electrical signal output to the vertical signal line 25 is subjected to well-known correlated double sampling in the CDS circuit 27 arranged for each vertical signal line 25, and noise is removed. The CDS circuit 27 is operated by a drive signal input from the horizontal scanning circuit 22 via the drive signal line 24.

  The electric signal after the noise is removed and converted into a true image signal component is sequentially output from the vertical signal line 25 to the horizontal signal line 28 and output to the outside of the image sensor 30 via the output amplifier 29. Although not shown in FIG. 2, a reset unit that actually resets the horizontal signal line 28 is connected to the horizontal signal line 28, and every time a signal is output from the output amplifier 29 to the outside, the horizontal signal line 28. Is reset.

  FIG. 4 is a circuit diagram showing a schematic configuration of the solid-state imaging device 3 according to the first embodiment of the present invention. The solid-state imaging device 3 is an external device in which the image sensor 30, the charging circuit 40, and one electrode 50 a described with reference to FIG. 3 are electrically connected to the image sensor 30 and the other electrode 50 b is grounded. 50. The external capacitor 50 has a capacitance value of 1 μF and has a remarkable effect of absorbing and removing AC component noise (suppressing voltage fluctuation). Note that the capacitance value is not limited to this. The external capacitor 50 arranged in the solid-state imaging device 3 of the present embodiment has a large capacitance value as described above, and is therefore not external to the image sensor 30 due to the large electrode area. This is because the chip area of the image sensor 30 is not increased. However, the present invention is not limited to this, and may be arranged in the image sensor 30.

  By the way, the image sensor 30 has a pixel current source control circuit 32. The pixel current source control circuit 32 is connected to each pixel current source 26 by a supply wiring 36 and supplies a predetermined voltage to the pixel current source 26 (hereinafter, the predetermined voltage may be referred to as Vg). The pixel current source 26 is configured to supply a constant current corresponding to the voltage supplied to Vg to the vertical signal line 25. Note that specific circuit configurations of the pixel current source 26 and the pixel current source control circuit 32 will be described later.

  One electrode 50 a of the external capacitor 50 is electrically connected to a supply wiring 36 that supplies Vg to the pixel current source 26. That is, the wiring 37 that electrically connects the image sensor internal terminal 38 and the supply wiring 36, the capacitance side terminal 51 that is electrically connected to one electrode 50 a of the external capacitor 50, and the terminal 38 and the terminal 51 are electrically connected. The supply wiring 36 and the one electrode 50a are electrically connected to each other by the wire bonding 52 that is electrically connected. Accordingly, the same voltage as the predetermined voltage (Vg) output from the pixel current source control circuit 32 and supplied to the pixel current source 26 is applied to one electrode 50a of the external capacitor 50. Note that the wirings 36 and 37 and the wire bonding 52 have a slight resistance value, and a voltage drop is caused thereby. If this voltage drop is taken into account, the voltage applied to one electrode 50a is not exactly the same as Vg. However, here, even if such a slight voltage drop occurs, it is regarded as substantially the same voltage.

  In the solid-state imaging device 3, the ground is connected to the other electrode 50 b of the external capacitor 50. As a result, a ground level voltage is supplied to the other electrode 50b.

  One electrode 50a of the external capacitor 50 is connected to a charging circuit 40 for rapidly charging the external capacitor 50 to a constant voltage. In the solid-state imaging device 3, when rapidly charging the external capacitor 50 with the voltage (Vg) supplied from the pixel current source control circuit 32 to one electrode 50 a of the external capacitor 50 and the charging circuit 40. The voltage (Vc) supplied to the electrode 50a is set to be the same voltage. Therefore, the external capacitor 50 is rapidly charged by operating the charging circuit 40 when the electronic camera 1 is activated, and thereafter enters a steady state. For this reason, in the electronic camera 1, the shutter time lag is extremely shortened while the noise of the AC component is removed. Hereinafter, this will be described in detail with reference to the drawings.

  FIG. 6 is a schematic circuit diagram illustrating a configuration of a solid-state imaging device according to a comparative example. This figure corresponds to FIG. 4, and the same constituent elements bear the same reference numerals. This solid-state imaging device 140 corresponds to the above-mentioned “means that can be easily solved by those skilled in the art”.

  The solid-state imaging device 140 according to the comparative example is different from the solid-state imaging device 3 of the present embodiment in that the charging circuit 40 connected to the electrode 50a of the external capacitor 50 is removed.

  Before the image sensor 30 mounted on the solid-state imaging device 140 is started, one electrode 50a of the external capacitor 50 is discharged and substantially grounded because no voltage is applied. The other electrode 50b of the external capacitor 50 is grounded by being connected to the ground as described above. When the image sensor 30 is activated, the voltage VG applied to the supply wiring 36 is changed from 0 V to a predetermined voltage Vg. Therefore, Vg is supplied to one electrode 50 a of the external capacitor 50. However, the other electrode 50b of the external capacitor 50 remains grounded. Therefore, a voltage difference is generated between the one electrode 50a and the other electrode 50b, and the external capacitor 50 is charged with an amount of charge corresponding to the voltage difference. While the electric charge is charged, the voltage of the supply wiring varies from Vg as described above, and a shutter time lag occurs in the electronic camera.

  In general, Vg is determined by the threshold voltage of the NMOS transistors 35 and 36, and the value is normally about 1V. The ground voltage is zero volts. The capacitance value of the external capacitor 50 is as large as about 1 μF. For this reason, the shutter time lag becomes longer than 100 milliseconds. This is because the capacitance value of the external capacitor 50 is large, the time required for the pixel current to stabilize is about 100 milliseconds, and the shutter time lag of the electronic camera becomes longer than 100 milliseconds. The shutter time lag of the electronic camera must be longer than the time required to stabilize the pixel current source. The allowable range of the shutter time lag varies depending on the electronic camera, but is said to be within about 40 milliseconds. Then, the time allowed for the stabilization of the pixel current source to realize this is within 20 milliseconds. Of course, in the solid-state imaging device, such an external capacitor may be removed or an external capacitor having a small capacitance value may be used. However, if such a configuration is adopted, noise due to the AC component is not removed.

  In the solid-state imaging device 3 of the present embodiment, a charging circuit 40 that rapidly charges the external capacitor 50 to Vc is connected to the electrode 50 a of the external capacitor 50. And Vg and Vc are substantially made equal. The time required for charging is determined according to a time constant τ determined by the product of the capacity to be charged and the internal resistance of the circuit. By designing the circuit so that the resistance component of the charging circuit 40 becomes small, it is possible to charge rapidly. After the charging is completed, the charging circuit 40 is electrically disconnected from the external capacitor 50 and thereafter stops its operation. Therefore, in the solid-state imaging device 3 of the present embodiment, the shutter time lag generated in the solid-state imaging device 140 of the comparative example is sufficiently shortened. The electronic camera 1 can obtain a high-quality image from which AC component noise has been removed.

  However, even if the charging circuit 40 is provided so that Vg and Vc are equal in design, it is difficult to completely eliminate the shutter time lag due to manufacturing variations and various destabilizing factors when the power is turned on. However, even if these are taken into consideration, the electronic camera of this embodiment can significantly reduce the shutter time lag. As a matter of course, since the external capacitor 50 having a large capacitance value is disposed in the solid-state imaging device 3, noise due to the AC component is removed, and a high-quality image can be obtained.

  In the present embodiment, the charging circuit 40 charges the electrode 50b of the external capacitor 50 with Vc substantially equal to Vg, but the present invention is not limited thereto. If Vc is a voltage closer to Vg than the ground level (that is, zero volts), the shutter time lag is reduced. In this case, when the external capacitor 50 is charged by the charging circuit 40, a potential difference is generated between the voltage Vc supplied to one electrode 50a and the steady-state voltage Vg. After being electrically disconnected from the capacitor 50, the external capacitor 50 is charged by the pixel current source control circuit 32. However, the potential difference is smaller than that of the solid-state imaging device 140 according to the comparative example. For this reason, since the solid-state imaging device 3 requires less charge than the solid-state imaging device 140 according to the comparative example, the time required for charging is shortened. Therefore, in the solid-state imaging device 3 of the present embodiment, the shutter time lag is shortened.

  Here, referring back to FIG. 4, specific circuit configurations of the pixel current source 26, the pixel current source control circuit 32, and the charging circuit 40 will be described. The pixel current source 26 is composed of an NMOS transistor. The NMOS transistor constituting the pixel current source 26 has a source grounded and a drain connected to the vertical signal line 25. The gates (electrodes) of the NMOS transistors constituting the pixel current source 26 are connected to the supply wiring 36 in common. The supply wiring 36 is connected to the pixel current source control circuit 32 as described later.

  The pixel current source control circuit 32 includes a resistor 34, a PMOS transistor 33 that forms a first changeover switch unit, and an NMOS transistor 35 that forms a mirror circuit. The PMOS transistor 33 has a source connected to the power supply voltage (VDD), a drain connected to the resistor 34, and a gate to which the drive signal φstby is applied. VDD is a binary voltage as described later. The NMOS transistor 35 constituting the mirror circuit has its drain connected to the resistor 34 and its gate, and its source grounded. The gate (and drain) of the NMOS transistor 35 is connected to the supply wiring 36, and the same voltage as the gate (and drain) voltage of the NMOS transistor 35 is supplied to the gate of each NMOS transistor constituting the pixel current source 26. The Note that a voltage at a terminal that the pixel current source control circuit 32 supplies to the pixel current source 26 via the supply wiring 36 is VG.

  With these configurations, the current determined by the mirror ratio of the NMOS transistor 35 and the NMOS transistor 26 with respect to the current flowing through the NMOS transistor 35 that constitutes the mirror circuit of the pixel current source control circuit 32 is used as a reference. Flows through the NMOS transistor. That is, the pixel current source 26 and the pixel current source control circuit 32 constitute a current mirror circuit. The pixel current source control circuit 32 receives one VDD voltage (5V in the present embodiment as will be described later) and generates a constant current, and sets each voltage of the pixel current source 26 as a predetermined voltage Vg corresponding to the current. This is supplied to the gate (electrode) of the NMOS transistor. The supply wiring 36 is connected to one electrode 50a of the external capacitor 50, and a voltage substantially the same as VG (Vg if VDD is 5V) is applied to one electrode 50a of the external capacitor 50. Supplied.

  In the solid-state imaging device 3, a PMOS transistor 33 is disposed as a first changeover switch unit for turning off the pixel current source 26 during long-time exposure such as 1 second. It is not necessary to pass a constant current through the vertical signal line 25 during long exposure. That is, in the image sensor 30, the signal from the pixel 20 is not output to the vertical signal line 25 during long-time exposure, and therefore it is not necessary to flow a constant current through the vertical signal line 25. Therefore, it is possible to turn off the pixel current source 26 and place the image sensor 30 in a standby state during long exposure. If this is turned off, it is possible to reduce power consumption, and suppressing the heat generation leads to stabilization of element characteristics. Therefore, the electronic camera 1 applies a high-level drive signal φstby to the gate of the PMOS transistor 33 serving as the first changeover switch unit disposed in the solid-state imaging device 3 during long exposure. As a result, the PMOS transistor 33 is turned off, and the current output from the NMOS transistor 35 constituting the mirror circuit of the pixel current source control circuit 32 is stopped, and accordingly the current flows to the NMOS transistor constituting the pixel current source 26. The current stops. The pixel current source 26 may be turned off for an exposure time of ¼ second or more, or ½ second or more.

  The charging circuit 40 includes a voltage generation circuit 42 and a transfer gate 48. The voltage generation circuit 42 includes a resistor 44, a PMOS transistor 43 that constitutes a second changeover switch unit, a buffer circuit 47, and an NMOS transistor 45 that generates a Vc potential (equivalent to the NMOS transistor 35 that constitutes a mirror circuit). have. The PMOS transistor 43 constituting the second changeover switch section has its source connected to the power supply voltage (VDD), its drain connected to the resistor 44, and its gate to which the drive signal φstby is applied. A φSW pulse is connected to the transfer gate 48. When φSW = H, the transfer gate 48 is turned on. VDD is the same as VDD input to the pixel current source control circuit 32, and is a binary voltage. The NMOS transistor 45 for generating the Vc potential has its drain connected to the resistor 44, its gate, and the buffer circuit 47, and its source is grounded. The buffer circuit 47 is connected to the electrode 50 a of the external capacitor 50 through the transfer gate 48. Let the voltage at this terminal be VC.

  With this configuration, the charging circuit 40 can receive one VDD voltage (5 V in the present embodiment) and supply a voltage equal to VG to the electrode 50 a of the external capacitor 50. Here, Vc is substantially equal to Vg, but may be a voltage closer to Vg than the ground level. In addition, the voltage generation circuit 42 is configured using a circuit equivalent to the pixel current source control circuit 32 here. However, the voltage generation circuit 42 is not limited to this, and for example, a voltage generation circuit combining an electronic volume and a regulator IC may be used. Good. When the electronic volume is used, the voltage cannot be changed more finely than the set step. For this reason, there is a possibility that Vc cannot be matched with Vg. However, if an electronic volume is used, Vc may be set to a voltage closest to Vg. The Vc set in this way, or Vc that substantially matches Vg is defined as “substantially the same” voltage here. Another method is to create a target voltage using a DA converter. Also in this case, Vc may be set to a voltage closest to Vg, as in the case of using the electronic volume. As yet another method, a voltage source dedicated to the charging circuit adjusted to substantially the same voltage as VG (about 1.0 V) may be prepared separately.

  The transfer gate 48 operates as an electrical switch. Immediately after the image sensor 30 is activated, φSW is set to high level and the transfer gate 48 is turned on for a predetermined time. Then, the external capacitor 50 is rapidly charged by the charging circuit 40 in accordance with a time constant τ determined by the size of the capacitance value and the size of the resistance component of the transfer gate 48. For example, when the capacitance value is 1 μF and the resistance component is 1 kΩ, the time constant is determined by τ = CR and is about 1 msec. Therefore, after waiting for 5 × τ, that is, about 5 msec, the external capacitor 50 is charged to 99% of the power supply voltage. Thereafter, if φSW = L and the transfer gate 48 is turned off, the charging circuit 40 is electrically disconnected from the image sensor 30. In this way, the electronic camera 1 has an extremely short shutter time lag while removing AC component noise.

  In order to realize the circuit operation as described above, a dedicated pulse generated by the timing generator in the imaging control unit 4 of the camera 1 shown in FIG. 1 can be output as a φSW pulse. Alternatively, φSW needs to be at H level immediately after the electronic camera 1 is activated and VDD is supplied to the solid-state imaging device 3 and immediately after the φSTBY pulse is inverted from H to L. A circuit that becomes H level for a certain time when the φSTBY pulse fluctuates in a predetermined manner may be used. In the latter case, φSW can be generated from the existing power supply and pulse, so that the timing generator before application of the present invention can be used as it is.

  Here, the voltage generation circuit 42 of the charging circuit 40 is configured to include a buffer circuit 47. However, the present invention is not limited to this. The voltage generation circuit 42 does not include the buffer circuit 47, and these may be configured as separate components. The voltage generation circuit 42 generates Vc and inputs it to the buffer circuit 47, and the buffer circuit 47 supplies Vc to the external capacitor 50 through the transfer gate 48. Alternatively, a level shift circuit is inserted between the voltage generation circuit 42 and the buffer circuit 47 (or the buffer circuit 47 is a buffer circuit having a level shift function), and the voltage generation circuit 42 generates a voltage different from Vc. The buffer circuit 47 may supply Vc to the external capacitor 50 via the transfer gate 48.

[Modification of First Embodiment]
FIG. 5 is a schematic circuit diagram showing a configuration of a modification of the solid-state imaging device 3 in which the charging circuit 40 has a circuit configuration different from that of FIG. The charging circuit 40 shown in this modification has a comparison circuit 49 in addition to the voltage generation circuit 42 and the transfer gate 48 described in FIG. Unlike FIG. 4, the voltage generation circuit 42 does not include the buffer circuit 47 in this modification.

  One input terminal of the comparison circuit 49 is connected to the gate and drain of the NMOS transistor 45 in the voltage generation circuit 42. As a result, the threshold voltage of the NMOS transistor 45 is input to one input terminal of the comparison circuit 49. This threshold voltage is about 1.0 V, which is the same as Vg. The other input terminal of the comparison circuit 49 is connected to the electrode 50 a of the external capacitor 50. As a result, the potential of one electrode 50 a of the external capacitor 50 is detected by the comparison circuit 49. The output from the comparison circuit 49 is input to the transfer gate 48 as φSW.

  The circuit operation in the modification of FIG. 6 will be described. When power is supplied to the solid-state imaging device 3 so that VDD becomes H level and the image sensor 30 is not in the standby state, the charging circuit 40 starts its operation. While the voltage of the electrode 50a of the external capacitor 50 is low, the output of the comparison circuit 49, that is, φSW is at the H level. At this time, since the transfer gate 48 is turned on, VDD is supplied to the electrode 50a of the external capacitor 50, and the external capacitor 50 is charged. After that, when the external capacitor 50 is charged and the voltage of the electrode 50a rises and exceeds the target threshold voltage, the output of the comparison circuit 49, that is, φSW is inverted and becomes L level. Then, the transfer gate 48 is turned off, and the charging circuit 40 is electrically disconnected from the image sensor 30.

  Note that the input of the comparison circuit 49 is a Schmitt trigger input. That is, when the threshold voltage of the NMOS transistor 45 is 1V and the potential of the electrode 50a of the external capacitor 50 exceeds 1V, the output of the comparison circuit 49 is inverted from L to H. However, once inversion occurs, the output of the comparison circuit 49 returns from H to L only after the voltage has decreased to (1−Δ) V. The value of Δ is preferably set sufficiently larger than the fluctuation of the VG potential caused by noise of the image sensor 30 or power supply fluctuation. For example, if Δ = 0.5V, the threshold value for inverting the output of the comparison circuit 49 from L to H is 1.0V, and the threshold value for inverting H to L is 0.5V. Here, the magnitude of VG fluctuation due to noise and power supply voltage fluctuation during normal operation of the image sensor 30 is sufficiently smaller than 0.5V. Therefore, the charging circuit 40 works only when the external capacitor 50 needs to be charged, and the charging circuit 40 can be prevented from operating carelessly at other times.

  In the modification described above, the pulse (φSW) for controlling the charging circuit 40 is automatically generated by the comparison circuit 49, so that it is not necessary to supply it from the outside. Thereby, it is not necessary to output φSW from the timing generator, and the one before application of the present invention can be used as it is.

  FIG. 7 is a timing chart showing the relationship between the drive signal φstby, the control signal φSW and the power supply voltage VDD output from the imaging control unit 4 of the electronic camera 1 according to the present embodiment, and VG and VC generated by the solid-state imaging device 3. is there. Note that VG is a voltage supplied from the pixel current source control circuit 32 to the electrode 50a of the external capacitor 50, and VC is a voltage generated by the voltage generation circuit 42 so that the charging circuit 40 charges the external capacitor 50. . The control signal φSW is a pulse for controlling the operation / non-operation state of the charging circuit 40. The drive signal φstby and the power supply voltage VDD are signals for allowing the pixel current source control circuit 32 and the pixel current source 26 to pass a constant current, and are referred to as “current voltage generation signals” here. It is assumed that the control signal φSW is also included in this current voltage generation signal. (A) shows the case where the exposure time is normal (less than about 1/4 second), and (b) shows the case where the exposure is long time (about 1/4 second or more).

  First, using the timing chart of FIG. 7A, the relationship between the current voltage generation signal and the drive of each changeover switch unit when the exposure time is normal with the operation of the electronic camera 1 will be described. In the initial state up to T1, the power of the electronic camera 1 is turned on, but the image sensor 30 is stopped. The microprocessor 9 (see FIG. 1) outputs a command for stopping the image sensor 30 to the imaging control unit 4.

  The imaging control unit 4 outputs a current voltage generation signal for causing the image sensor 30 to be stopped based on a command from the microprocessor 9. That is, the power supply voltage (hereinafter referred to as VDD) is 0 V, and the drive signal φstby is low level (L). In this state, since power is not supplied to either the image sensor 30 or the charging circuit 40, the image sensor 30 does not operate and is stopped. Therefore, no voltage is applied to the electrode 50a of the external capacitor 50 and the ground level becomes 0V.

  When the shutter button of the electronic camera 1 is pressed at the time T1, the microprocessor 9 turns on the power of the solid-state imaging device 3 to the imaging control unit 4, and the image sensor 30 mounted on the solid-state imaging device 3 is turned on. Outputs a command to bring the machine from the stopped state to the activated state. The imaging control unit 4 outputs a current voltage creation signal based on the command. Note that the imaging control unit 4 also outputs drive signals other than the current-voltage creation signal, but the description thereof is omitted here. The imaging control unit 4 changes the voltage of VDD from 0V to 5V and outputs it to the image sensor 30 based on a command from the microprocessor 9. Further, the imaging control unit 4 continues to output the low level drive signal φstby. At this time, the PMOS transistor 33 configuring the first changeover switch unit is in an on state. When VDD becomes 5V, the pixel current source control circuit 32 operates and a constant current flows. Then, the pixel current source control circuit 32 supplies a predetermined voltage Vg corresponding to the constant current to the supply wiring 36. Here, Vg is 1V. Therefore, VG changes from 0V to 1V.

  At the time T1, the low-level drive signal φstby is output from the imaging control unit 4, so that the PMOS transistor 43 configuring the second changeover switch unit is in the on state. When VDD becomes 5V, the voltage generation circuit 42 outputs a predetermined voltage Vc. Here, Vc is 1V. Therefore, VC changes from 0V to 1V. At this time, the imaging control unit 4 sets the control signal φSW to the H level. Then, the transfer gate 48 is turned on, the charging circuit 40 operates, and Vc (1 V) is supplied to one electrode 50a of the external capacitor 50. Thereby, the external capacitor 50 is charged.

  As described above, when the image sensor 30 changes from the stop state to the start state at the time T1, the voltage VG output from the pixel current source control circuit 32 and the voltage VC output from the voltage generation circuit 42 from the charging circuit 40 Changes rapidly from 0V to 1V. The charging circuit 40 is designed to have a sufficiently small internal resistance, and can quickly charge the external capacitor 50. Therefore, immediately after the power is turned on, charging of the external capacitor 50 is completed, and the voltage VG is supplied to the supply wiring 36 and used for generating a constant current by the pixel current source 26. In addition, AC component noise is absorbed by the external capacitor 50. Therefore, the shutter time lag of the electronic camera 1 is shortened.

  After the electrode 50a becomes a predetermined voltage and the charging of the external capacitor 50 is completed, the imaging control unit 4 lowers φSW to L level. Then, the transfer gate 48 is turned off. As a result, the charging circuit 40 is electrically disconnected from the image sensor 30. As a result, the operation of the charging circuit 40 is stopped after the charging of the external capacitor 50 is completed, and the charging circuit 40 can be prevented from having an unnecessary influence on the operation of the image sensor 30.

  Further, when Vg is supplied to the gate (electrode) of the NMOS transistor constituting the pixel current source 26, the pixel current source 26 starts its operation and causes a constant current to flow through the vertical signal line 25. When the pixel current source 26 operates, the pixel 20 can output an electrical signal corresponding to the amount of incident light to the vertical signal line 25. Thereafter, an electrical signal is output from the pixel 20 in accordance with a drive signal (not shown).

  In the period from T1 to T2, the image sensor 30 generates and accumulates photoelectrically converted charges in a designated exposure time (less than ¼ second). The electronic camera 1 outputs an electrical signal corresponding to the amount of charge photoelectrically converted from the image sensor 30 and performs predetermined processing such as signal processing, image compression, and recording. Then, at time T <b> 2 when these processes are completed, the microprocessor 9 outputs a command for controlling the start state to the stop state to the imaging control unit 4. Based on this command, the imaging control unit 4 changes the VDD to 0 V and outputs it to the image sensor 30. The image sensor 30 is again stopped, and VG and VC are set to 0V.

  Next, using the timing chart of FIG. 7B, the relationship between the current voltage generation signal and the driving of each changeover switch unit when the exposure time is long with the operation of the electronic camera 1 will be described. Note that the period up to T1 and the period after T2 are periods in which the image sensor 30 is in a stopped state, and the description overlaps with FIG. Therefore, here, overlapping description is omitted as much as possible, and a period from T3 to T4 in which driving different from that in FIG.

  At time T1, the imaging control unit 4 changes the voltage from VDD to 0V and outputs it to the image sensor 30 based on a command from the microprocessor 9. The operation at this time is the same as the description of FIG. 7A, and the shutter time lag is shortened by rapidly charging the external capacitor 50.

  A period from T3 to T4 is an exposure period. In FIG. 7B, the exposure time is a long time of 1/4 second or longer, and the image sensor 30 is in a standby state during this period. Here, the standby state of the image sensor 30 means a state in which VDD is maintained at 5 V and the power supply voltage 5 V is applied to the image sensor 30. For this reason, in the standby state, each pixel 20 is maintained in a state in which charges are accumulated by photoelectric conversion.

  At time T3, the microprocessor 9 outputs an instruction to start exposure to the imaging control unit 4 and outputs an instruction to control the image sensor 30 to the standby state to the imaging control unit 4. Based on this command, the imaging control unit 4 causes the image sensor 30 to start exposure. Specifically, the imaging control unit 4 opens the mechanical shutter of the electronic camera 1. Or if an electronic shutter is performed, the imaging control part 4 will discharge the electric charge accumulate | stored in the photodiode.

  Further, the imaging control unit 4 changes the drive signal φstby from the low level (L) to the high level (H) and outputs it to the image sensor 30 while holding VDD at 5V. At this time, in the pixel current source control circuit 32, the PMOS transistor 33 configuring the first changeover switch unit is turned off by receiving the high level drive signal φstby at the gate (electrode). Therefore, VDD is not applied to the drain of the NMOS transistor 35 constituting the mirror circuit. Therefore, the drain of the NMOS transistor 35 changes from 5V to 0V, and the pixel current source control circuit 32 is turned off. Along with this, VG changes from Vg (1 V) to 0 V, and the pixel current source 26 is also turned off. That is, the pixel current source control circuit 32 supplies a voltage of 0 V (ground level), which is a voltage lower than Vg, to the pixel current source 26 when the PMOS transistor 33 configuring the first changeover switch unit is in an OFF state. . Since the pixel current source control circuit 32 and the pixel current source 26 are not operating and no constant current flows through the vertical signal line 25, power consumption is reduced and heat generation is also suppressed. However, since VDD is held at 5 V, the pixel 20 maintains a state of generating and accumulating charges according to incident light while in the standby state.

  At time T4, the microprocessor 9 outputs a command to end the exposure to the imaging control unit 4 and outputs a command to control the image sensor 30 from the standby state to the activated state to the imaging control unit 4. Based on this command, the imaging control unit 4 ends the exposure of the image sensor 30. Specifically, the mechanical shutter of the electronic camera 1 is closed. Alternatively, if the image sensor 30 is configured to enable simultaneous exposure of all pixels as disclosed in Patent Document 1, the transfer transistor is turned on to transfer charges from the photodiode. Further, the imaging control unit 4 changes the drive signal φstby from the high level (H) to the low level (L) and outputs it to the solid-state imaging device 3. In the pixel current source control circuit 32, the PMOS transistor 33 constituting the first changeover switch unit is turned on by receiving a low level drive signal φstby at its gate (electrode). Accordingly, VDD and the pixel current source control circuit 32 are connected. VDD is maintained at 5V. Therefore, the pixel current source control circuit 32 starts its operation, a constant current flows, and supplies a predetermined voltage Vg corresponding to the constant current to the supply wiring 36.

  At this time, in the voltage generation circuit 42 of the charging circuit 40, the PMOS transistor 43 constituting the second changeover switch unit receives the low level (L) drive signal φstby at the gate (electrode) and is turned on. Therefore, the NMOS transistor 45 is in the same operation state as the NMOS transistor 35, and VC output from the voltage generation circuit 42 changes from 0V to Vc (1V). At the same time, the imaging control unit 4 sets φSW to the H level. Then, since the transfer gate 48 is turned on, the charging circuit 40 supplies Vc (1 V) to one electrode 50a of the external capacitor 50 to charge the external capacitor 50. As a result, even if the image sensor 30 changes from the standby state to the activated state, the external capacitor 50 is rapidly charged. As a result, immediately after the image sensor 30 returns from the standby state, the external capacitor 50 is immediately charged. Accordingly, the operation time for the image sensor 30 to return from the standby state is shortened, and the shutter time lag of the electronic camera 1 is shortened.

  When charging of the external capacitor 50 is completed, the imaging control unit 4 lowers φSW to the L level as in the case of T1. Then, the transfer gate 48 is turned off, and the charging circuit 40 is electrically disconnected from the image sensor 30. As a result, the operation of the charging circuit 40 is stopped after the charging of the external capacitor 50 is completed, and the charging circuit 40 can be prevented from having an unnecessary influence on the operation of the image sensor 30.

  As described above, in the period from T3 to T4, unlike the period from T1 to the period after T2, the image sensor 30 is in the standby state while VDD is 5V.

  In the present embodiment, a period from T3 to T4 is an exposure time and a standby state period. However, the present invention is not limited to this, and the period during which the image sensor 30 is in the standby state may be shorter than the exposure time. As described above, even if Vg and Vc are designed to be equal, there is a risk of slight deviation due to manufacturing errors or the like. When Vg and Vc deviate, the external capacitor 50 is charged, and the time required for the image sensor 30 to return from the standby state becomes longer according to the amount of charge to be charged. Therefore, it is preferable that the transition point from the standby state to the start state is set before the exposure end time in consideration of the charging time in consideration of the maximum allowable deviation amount of Vg and Vc. In this way, at the end of exposure, the image sensor 30 is in a state where it can output an electrical signal from each pixel. For this reason, the electronic camera 1 can shorten the shutter time lag.

  Furthermore, in this embodiment, Vg and Vc are substantially the same. However, if Vc is set to a voltage closer to Vg than 0 V, the time required to return from the standby state is obtained from the difference between Vg and Vc and the capacitance value of the external capacitor 50, thereby changing from the standby state to the startup state. What is necessary is just to set the transition time of.

  If the time required to return from the standby state to the start-up state is short, it is only necessary to start the return operation of the pixel current source immediately before starting the pixel signal readout operation, thereby reducing the power consumption and the influence of heat generation. effective.

  In this embodiment, VDD is a binary value of 0V and 5V. However, the present invention is not limited to this, and may be 0V and 6V, for example.

  In the present embodiment, the pixel current source 26 and the pixel current source control circuit 32 are shown with a simple circuit configuration. However, the present invention is not limited to this. FIG. 8 shows a modification of the image sensor mounted on the solid-state imaging device according to the first embodiment of the present invention. The image sensor 60 of the present modification differs from the image sensor 30 in that a pixel current source 66 is arranged instead of the pixel current source 26, and a pixel current source control circuit 62 is arranged instead of the pixel current source control circuit 32. It is only a point.

  The pixel current source 66 includes NMOS transistors 67 and 68 formed of a two-stage cascode circuit. That is, in the upper stage NMOS transistor 67 in the figure, the drain is connected to the vertical signal line 25, the source is connected to the drain of the lower stage NMOS transistor 68, and the gate electrode is connected to the supply wiring 69. In the lower stage NMOS transistor 68 in the figure, the drain is connected to the source of the upper stage NMOS transistor 67, the source is connected to the ground, and the gate electrode is connected to the supply wiring 36. Accordingly, the mirror circuits 65 and 35 of the pixel current source control circuit 62 are configured in two stages. That is, the upper stage load transistor 65 has a drain and a gate connected to the resistor 34 and the supply wiring 69, and a source connected to the drain of the lower stage NMOS transistor 35. The lower stage NMOS transistor 35 has its drain and gate connected to the source of the upper stage NMOS transistor 65 and the supply wiring 36, and its source is grounded.

  The pixel current source 66 and the pixel current source control circuit 62 constitute a current mirror circuit. Such a cascode circuit pixel current source 66 is more preferable because the current flowing through the vertical signal line 25 is more likely to be constant compared to a single-stage current mirror circuit.

  In this modification, the current value of the vertical signal line 25 is determined by the NMOS transistor closer to the ground on the principle of operation of the element. Therefore, one electrode of the external capacitor may be connected to the supply wiring 36 that supplies a voltage to the gate electrode of the NMOS transistor close to the ground. In this way, noise due to the AC component is absorbed by the external capacitor. The voltage generator described in the first embodiment is connected to the other electrode of the external capacitor. Thereby, the shutter time lag is shortened.

[Second Embodiment]
FIG. 9 is a schematic circuit diagram showing the configuration of the solid-state imaging device 63 according to the second embodiment of the present invention. This figure corresponds to FIG. 4, and the same components are denoted by the same reference numerals and description thereof is omitted. The difference between the solid-state imaging device 63 and the solid-state imaging device 3 of the first embodiment is that the charging circuit 40 is provided outside the image sensor 30 in the solid-state imaging device 3 as shown in FIG. In the solid-state imaging device 63, the charging circuit 80 is disposed in the image sensor 70.

  In the circuit of FIG. 9, the charging circuit 80 includes a voltage generation circuit 82 and a transfer gate 88. The voltage generation circuit 82 includes a resistor 84, a PMOS transistor 83 that forms a second changeover switch unit, an NMOS transistor 85 that forms a load transistor, and a buffer circuit 87. The PMOS transistor 83 constituting the second changeover switch section has its source connected to the power supply voltage (VDD), its drain connected to the resistor 84, and its gate to which the drive signal φstby is applied. The drive signals φstby and VDD are also supplied to the pixel current source control circuit 32. VDD is a binary value of 5V and 0V. The NMOS transistor 85 constituting the load transistor has its drain connected to the resistor 84 and its gate, and its source grounded. The drain (and gate) of the NMOS transistor 85 is connected to the wiring 37 via the buffer circuit 87 and the transfer gate 88. That is, the drain of the NMOS transistor 85 is electrically connected to the electrode 50 a of the external capacitor 50 through the buffer circuit 87, the transfer gate 88, the wiring 37, the image sensor internal terminal 38, the wire bonding 52, and the capacitor side terminal 51. Is done.

  If VDD is 5V, the charging circuit 80 sets the VC output from the voltage generation circuit 82 to a constant voltage Vc (here, 1V). When φSW is at the H level, the transfer gate 88 is turned on to supply VC to the electrode 50a of the external capacitor 50, and the external capacitor 50 is rapidly charged. The drive signals φstby, φSW, and VDD, and the operations of the image sensor 70 and the electronic camera 1 are the same as those in the first embodiment, and a description thereof is omitted here.

[Modification of Second Embodiment]
FIG. 10 is a schematic circuit diagram showing a configuration of a modification of the solid-state imaging device 63 in which the charging circuit 80 has a circuit configuration different from that of FIG. The charging circuit 80 shown in this modification has the same configuration as the charging circuit 40 of the solid-state imaging device 3 according to the modification of the first embodiment shown in FIG. That is, in this modification, the charging circuit 80 further includes a comparison circuit 89 in addition to the voltage generation circuit 82 and the transfer gate 88 described in FIG. Unlike FIG. 9, the voltage generation circuit 82 does not include the buffer circuit 87 in this modification.

  Also in this modification, the voltage generation circuit 82, the transfer gate 88, and the comparison circuit 89 are connected in the same connection relationship as the voltage generation circuit 42, the transfer gate 48, and the comparison circuit 49 of FIG. . In this state, the charging circuit 80 is disposed in the image sensor 70.

  When the charging circuit 80 is arranged in the image sensor 70 as in the second embodiment and the modifications described above, the number of assembly parts of the solid-state imaging device 63 can be reduced. For this reason, inventory management of parts constituting the solid-state imaging device 63 is facilitated, and the manufacturing process is simplified.

1 is a schematic block diagram illustrating an electronic camera according to a first embodiment of the present invention. It is a schematic circuit diagram which shows the structure of the image sensor in this solid-state imaging device. It is a pixel circuit diagram in an image sensor. 1 is a schematic circuit diagram illustrating a configuration of a solid-state imaging device according to a first embodiment of the present invention. It is a schematic circuit diagram which shows the structure of the modification of the solid-state imaging device which concerns on 1st Embodiment of this invention. It is a schematic circuit diagram which shows the structure of the solid-state imaging device which concerns on a comparative example. 6 is a timing chart showing the relationship between drive signals φstby, φSW and power supply voltage VDD output by the imaging control unit of the electronic camera according to the present embodiment, and VG and VC generated by the solid-state imaging device. It is a modification of the image sensor mounted in the solid-state imaging device concerning 1st Embodiment of this invention. It is a schematic circuit diagram which shows the structure of the solid-state imaging device which concerns on 2nd Embodiment of this invention. It is a schematic circuit diagram which shows the structure of the modification of the solid-state imaging device which concerns on 2nd Embodiment of this invention.

Explanation of symbols

1 Electronic camera
3, 63, 140 Solid-state imaging device 4 Imaging control unit 9 Microprocessor 20 Pixel 25 Vertical signal line 26, 66 Pixel current source 30, 60, 70 Image sensor 31 Pixel region 32, 62 Pixel current source control circuit 36 Supply wiring 40, 80 Charging circuit 42, 82 Voltage generation circuit 48, 88 Transfer gate 49, 89 Comparison circuit 50 External capacitance

Claims (8)

A plurality of pixels arranged two-dimensionally in a row direction and a column direction and outputting a signal corresponding to the amount of incident light;
A plurality of vertical signal lines connected to the pixels for each pixel column and receiving the signals from the pixels;
A pixel current source provided for each of the vertical signal lines and supplying a constant current to the vertical signal lines;
A pixel current source control circuit connected to the pixel current source by a supply wiring and supplying a first voltage to the pixel current source;
One electrode is connected to the supply wiring and supplied with the first voltage, and the other electrode is supplied with a ground level voltage, and has a capacity large enough to absorb fluctuations in the power supply voltage ;
A charging circuit connected to the one electrode of the capacitor and supplying a second voltage to the capacitor to charge the capacitor ;
The solid-state imaging device , wherein when the power is turned on, the charging circuit rapidly charges the capacitor until the potential of the capacitor becomes a level substantially equal to the second voltage, and stops the operation after the charging is completed . The solid-state imaging device according to claim 1,
It has an image sensor consisting of a silicon substrate,
At least the pixel, the vertical signal line, the supply wiring, and the pixel current source are provided in the image sensor,
The solid-state imaging device according to claim 1, wherein the capacitor is an external part provided outside the image sensor. The solid-state imaging device according to claim 1 or 2 ,
The pixel includes a photoelectric conversion unit that generates and accumulates charge according to incident light, and an amplification unit that outputs a signal according to the potential of the gate electrode when the charge is supplied to the gate electrode,
The pixel current source comprises an NMOS transistor,
The supply wiring is connected in common to the gate electrode of each NMOS transistor,
The pixel current source and the pixel current source control circuit constitute a current mirror circuit,
The pixel current source control circuit generates a constant current and supplies a voltage corresponding to the constant current to the gate electrode of each NMOS transistor as the first voltage. The solid-state imaging device according to any one of claims 1 to 3 ,
The pixel current source control circuit supplies a first voltage to the pixel current source in an on state, and supplies a voltage lower than the first voltage to the pixel current source in an off state. Have
The charging circuit charges the capacitor until the potential of the capacitor reaches a level substantially equal to the second voltage when the first changeover switch unit shifts from an off state to an on state. A solid-state imaging device characterized in that the operation is stopped. In the solid-state imaging device according to any one of claims 1 to 4 ,
The charging circuit includes a voltage generation circuit that generates the second voltage and a switch that switches a supply state of the second voltage to the capacitor, and the capacitor is turned on by turning on the switch for a predetermined time. A solid-state imaging device that is charged. The solid-state imaging device according to claim 5 ,
The charging circuit further includes a comparison circuit that detects a potential of the one electrode of the capacitor,
A solid-state imaging device characterized in that when the potential detected by the comparison circuit becomes a predetermined voltage, the switch is turned off to stop its operation. A plurality of pixels arranged two-dimensionally in a row direction and a column direction and outputting a signal corresponding to an incident light amount; a plurality of vertical signal lines connected to the pixels for each pixel column and receiving the signals from the pixels; A CMOS image sensor having at least a pixel current source including an NMOS transistor provided for each vertical signal line and supplying a constant current to the vertical signal line, and a supply wiring commonly connecting gate electrodes of the NMOS transistors; ,
A pixel current source control circuit connected to the supply wiring to form a current mirror circuit with the pixel current source, and supplying a first voltage to the gate electrode of each NMOS transistor;
One electrode is connected to the supply wiring and supplied with the first voltage, and the other electrode is supplied with a ground level voltage, and has a capacity large enough to absorb fluctuations in the power supply voltage ;
A charging circuit connected to the one electrode of the capacitor and supplying a second voltage to the capacitor to charge the capacitor;
An imaging controller that outputs the signal from the pixel ;
The charging circuit includes a solid-state imaging device that quickly charges the capacitor until the potential of the capacitor reaches a level substantially equal to the second voltage when power is turned on, and stops the operation after the charging is completed. And an electronic camera. The electronic camera according to claim 7 ,
The pixel current source control circuit includes a first changeover switch unit that supplies the first voltage to the pixel current source in an on state and supplies a ground level voltage to the pixel current source in an off state;
The charging circuit charges the capacitor until the potential of the capacitor reaches a level substantially equal to the second voltage when the first changeover switch unit shifts from an off state to an on state. Stop working,
The electronic camera, wherein the imaging control unit outputs a drive signal for operating the first changeover switch unit and the charging circuit.

Images