JPH09163247A - Boosting circuit, solid-state image pickup device mounted with the circuit and bar code reader and camera using the device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress fluctuation in a boosting output voltage when a power supply voltage or a clock frequency is fluctuated. SOLUTION: A potential detection circuit 2 detects a potential of a part using a boosting output voltage Vout and a comparator 3 compares the detected voltage and the boosting output voltage Vout shifted by a prescribed level at a level shifter 4. Then a gate voltage of a 1st stage MOS transistor(TR) of a clock drive type boosting section 1 or an amplitude of a clock pulse is controlled based on the comparison output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a booster circuit, a solid-state imaging device equipped with the booster circuit, and a bar code reader and a camera using the booster circuit. The present invention relates to a battery-operated bar code reader and a camera using the.

[0002]

2. Description of the Related Art FIG. 18 shows a conventional example of a clock drive type booster circuit. In the figure, a so-called diode-connected N-channel type MO whose gate and drain are commonly connected between the positive electrode side of the power supply 101 and the circuit output terminal 102.
SFET (hereinafter simply referred to as NMOS transistor)
The M10n is connected in series in the forward direction from the power supply 101 side toward the circuit output terminal 102 side, for example, in three stages.

The output terminal N11 of the first-stage NMOS transistor M101 has three stages of inverters 103, 104,
Clock pulse φ1 which is sequentially inverted and supplied at 105
Is applied via the capacitor C1. On the other hand, the output terminal N12 of the second-stage NMOS transistor M102 has 4
The clock pulse φ2 which is sequentially inverted and supplied by the inverters 103, 104, 106, 107 of the stages is applied via the capacitor C2. The clock pulse φ1 and the clock pulse φ2 are in opposite phases. A load capacitor CL is connected between the output terminal N13 (circuit output terminal 102) of the third-stage NMOS transistor M103 and the ground.

Next, the boosting operation in the steady state of the conventional boosting circuit having the above configuration will be described with reference to the timing waveform diagram of FIG. First, when the clock pulse φ1 is at “L” level, since the gate and drain of the NMOS transistor M11 are connected to the positive side of the power source 101, the voltage V11 at the output terminal N11 thereof is Vx11 less than the power source voltage Vdd. It's getting low. Where V
x11 is the threshold voltage Vth of the NMOS transistor M101
It is the voltage drop due to.

In this state, when the clock pulse φ1 is input via the capacitor C1, the NMOS transistor M101 is equivalent to the peak value of the clock pulse φ1.
The voltage V11 at the output terminal N11 of is increased. On the other hand, since the clock pulse φ2 has a phase opposite to that of the clock pulse φ1, when the clock pulse φ2 is at the “L” level,
The voltage V1 of the output terminal N12 of the MOS transistor M102
2 is lower than the voltage V11 at the output terminal N11 by Vx12. Here, Vx12 is an NMOS transistor M
This is the amount of voltage drop due to the threshold voltage Vth of 102.

In this state, when the clock pulse φ2 is input via the capacitor C2, the NMOS transistor M102 is equivalent to the peak value of the clock pulse φ2.
The voltage V12 of the output terminal N12 of is increased. The voltage V12 at the output terminal N12 is the same as the NMOS transistor M103.
And is smoothed by the load capacitor CL and is derived from the circuit output terminal 102 as the boosted output voltage Vout. The boosted output voltage Vout is output to the output terminal N12.
It is lower than the voltage V12 by Vx13. Here, Vx13 is a voltage drop due to the threshold voltage Vth of the NMOS transistor M103.

As is clear from the above description, in the clock drive type booster circuit, the clock pulse φ1,
When the peak value of φ2 is Vw, the boosted output voltage Vout is obtained by sequentially boosting the power supply voltage Vdd by (Vw-Vx1n) for each stage. Since Vx1n is a voltage drop caused by the threshold voltage Vth of the MOS transistor, if an enhancement type MOS transistor having a large threshold voltage Vth is used, the voltage drop Vx1n becomes large.

[0008]

However, in the conventional booster circuit having the above configuration, when the power supply voltage Vdd changes, the amplitudes of the clock pulses φ1 and φ2 also change accordingly, so that the boosted output voltage Vout is changed. There was a problem that the value fluctuated greatly. That is, taking the case of the booster circuit for triple boosting shown in FIG. 18, as shown in FIG. 20, when the power supply voltage Vdd increases by ΔVdd, the amplitudes of the clock pulses φ1 and φ2 are also approximately ΔVdd.
Therefore, the fluctuation amount Δ of the boosted output voltage Vout is increased.
Vout is about 3 × ΔVdd. As described above, when the boosted output voltage Vout largely fluctuates by a fluctuation multiple ΔVdd corresponding to the fluctuation of the power supply voltage Vdd, the characteristics of the device or circuit operating at the boosted output voltage Vout of the booster circuit. Will be adversely affected.

Still another problem is that the boosted output voltage Vout has a clock frequency dependency. That is, as shown in FIG. 21, as the clock frequency increases, the boosted output voltage Vout increases (=
Close to the normal boost value when the load current is small). FIG.
2 shows a timing waveform when the clock frequency changes.
This frequency dependence occurs when the current consumption on the load side is larger than or equal to the current capacity of the booster circuit. This current capacity increases the clock frequency and M
It can be increased by increasing the channel width of the OS transistor (increasing the mutual conductance g _m ). Therefore, if the booster circuit is configured to have a sufficient margin for the current consumption on the load side, the clock frequency dependency does not occur.

However, in order to do so, it is necessary to increase the size of the circuit elements such as the MOS transistor and the capacitor that constitute this booster circuit. Therefore, when using this booster circuit for a CCD linear sensor, for example, In some cases, it may be difficult to manufacture the CCD linear sensor on the same substrate (chip) as the sensor array and the charge transfer register, that is, to make it on-chip.

The present invention has been made in view of the above problems, and its object is to stabilize the circuit even when the power supply voltage or the clock frequency fluctuates without enlarging the circuit elements such as the MOS transistor and the capacitor. It is an object of the present invention to provide a booster circuit capable of obtaining a boosted output voltage, a solid-state imaging device equipped with the booster circuit, and a barcode reader and a camera using the same.

[0012]

In the booster circuit according to the present invention, unidirectional elements are connected in series in a forward direction from a power source side to a circuit output terminal side between a power source and a circuit output terminal. In addition, in a booster circuit in which a clock pulse is applied between each stage via a capacitor, at least the first stage of a plurality of stages of unidirectional elements is composed of a MOS transistor, and the gate voltage of this MOS transistor is controlled. The control circuit is configured to operate.

In the booster circuit having the above-mentioned structure, at least the first stage of the unidirectional elements of a plurality of stages is constituted by a MOS transistor, and the gate voltage of this MOS transistor is controlled so that the boosted output voltage depends on the gate voltage. Change. Therefore, a stable boosted output voltage can be obtained by appropriately controlling the gate voltage when the power supply voltage changes or when the clock frequency changes.

In another booster circuit according to the present invention, a plurality of unidirectional elements are connected in series in the forward direction from the power source side to the circuit output terminal side between the power source and the circuit output terminal, and each stage is connected in series. The booster circuit has a configuration in which a clock pulse is applied via a capacitor, and includes a control circuit that controls the amplitude of the clock pulse.

In the booster circuit having the above structure, the boosted output voltage changes according to the amplitude by controlling the amplitude of the clock pulse. Therefore, a stable boosted output voltage can be obtained by appropriately controlling the amplitude of the clock pulse when the power supply voltage changes or the clock frequency changes.

In the solid-state imaging device according to the present invention, a plurality of unidirectional elements are connected in series in the forward direction from the power source side to the circuit output terminal side between the power source and the circuit output terminal, and the interstages are connected to each other. Is equipped with a booster circuit configured to apply a clock pulse via a capacitor, and the booster circuit has a control circuit that controls the boosted output voltage based on the potential of a portion that uses the boosted output voltage. ing.

In the solid-state image pickup device having the above-mentioned structure, the booster circuit mounted therein can control the boosted output voltage based on the potential of the portion utilizing the boosted output voltage, and therefore operates in a manner that follows the potential. . As a result, even if the power supply voltage changes or the clock frequency changes, a stable boosted output voltage can be obtained without being affected by the change. Moreover, the boosted output voltage having the required voltage value can be obtained even with respect to the variation in the potential of the portion that uses the boosted output voltage.

The bar code reader according to the present invention has a structure in which the solid-state image pickup device having the boosting circuit having the above structure is used as an image sensor for reading a bar code. In addition, the camera according to the present invention has a configuration in which the solid-state imaging device equipped with the booster circuit having the above configuration is used as an autofocus sensor.

In the bar code reader and camera having the above structure, the booster circuit mounted on the solid-state image pickup device can obtain a substantially stable boosted output voltage even when the power supply voltage changes or the clock frequency changes. The boosted output voltage is strong against variations in the potential of the portion used, so that a low-voltage power source such as a battery can sufficiently operate.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, a booster unit 1 having a configuration capable of controlling the boosted output voltage Vout from the outside is provided as a main part of the booster circuit according to the present embodiment. FIG. 2 shows an example of a specific circuit configuration of the booster unit 1. FIG.
In between, for example, three MOS transistors M1, M2, M are provided between the power input terminal 11 and the circuit output terminal 12.
3 are connected in series from the power input terminal 11 to the circuit output terminal 12.

That is, the first-stage MOS transistor M
The drain of 1 is connected to the power input terminal 11, and the gate is connected to the control terminal 13. The gate and drain of the second-stage NMOS transistor M2 are connected to the source of the first-stage NMOS transistor M1, and the gate and drain of the third-stage NMOS transistor M3 are connected to the source of the second-stage NMOS transistor M2. The source of the third-stage NMOS transistor M3 is connected to the circuit output terminal 2. A load capacitor CL is connected between the circuit output terminal 12 and the ground.

A clock pulse φ1 which is sequentially inverted and supplied by the inverters 14, 15 and 16 is applied to the output terminal (source) N1 of the first-stage NMOS transistor M1 via the capacitor C1. On the other hand, the second stage NMOS
A clock pulse φ2, which is sequentially inverted by the inverters 14, 17, and 18 and supplied, is applied to the output terminal (source) N2 of the transistor M2 via the capacitor C2.
The clock pulse φ1 and the clock pulse φ2 are in opposite phases.

In the booster 1 having the above-described structure, when the power supply voltage Vdd is applied to the control terminal 13,
The booster circuit has a triple boosting circuit similar to the conventional circuit of FIG. 8, but the boosted output voltage Vout can be changed by changing the voltage Vfb applied to the control terminal 13 to control the gate voltage of the first-stage MOS transistor M1. . Therefore, a stable boosted output voltage Vout can be obtained by appropriately changing the control voltage Vfb applied to the control terminal 13 when the power supply voltage Vdd changes or when the frequencies of the clock pulses φ1 and φ2 change.

FIG. 3 shows the first stage MO of the boosted output voltage Vout.
The dependence on the gate voltage of the S transistor M1, that is, the control voltage Vfb is shown. As an example, when the control voltage Vfb is changed from 0V to 5V, the boosted output voltage Vout changes linearly in the range of 8V to 12V.

Although the gate voltage of the first-stage MOS transistor M1 is changed by the control voltage Vfb in the present embodiment, a MOS transistor is inserted between each stage and the gate voltage of the MOS transistor is changed according to the control voltage Vfb. It is also possible to control. Further, as shown in FIG. 4, the first-stage MOS transistor M1 is diode-connected, and an amplitude control circuit 5 for controlling the amplitude of at least one of the clock pulses φ1 and φ2 is provided, and the control voltage Vfb controls the clock pulses φ1 and φ2. The boosted output voltage Vout can also be controlled by changing the amplitude of at least one of them. In addition, the control voltage Vfb
Thus, it is possible to change both the gate voltage of the first-stage MOS transistor M1 and the amplitudes of the clock pulses φ1 and φ2 in parallel.

In this embodiment, diode-connected MOS transistors M2 and M3 are used as the unidirectional elements in the second and third stages in the circuit diagram of FIG.
A diode element itself may be used instead of the OS transistors M2 and M3, and similar operational effects are obtained. In the circuit diagram of FIG. 4, it is needless to say that the first-stage diode-connected MOS transistor M1 can be replaced with a diode element as in the case of the second- and third-stage diode-connected MOS transistors M2 and M3. Is.

Referring again to FIG. 1, the potential detection circuit 2 is for detecting the potential of the portion utilizing the boosted output voltage Vout. The detection voltage of the potential detection circuit 2 becomes the non-inverting (+) input of the comparator 3. The comparator 3 receives the boosted output voltage Vout shifted by a predetermined level by the level shifter 4 as an inversion (-) input, and calculates the difference between the level-shifted boosted output voltage Vout and the detection voltage of the potential detection circuit 2 as a control voltage Vfb. Is given to the control terminal 13 of the booster unit 1.

An example of a concrete circuit configuration of the potential detection circuit 2 is shown in FIG. In FIG. 5, the MOS transistor M4 is a dummy transistor having a structure in the vicinity of the portion using the boosted output voltage Vout. This MOS
The drain of the transistor M4 is connected to the power supply Vdd,
A predetermined voltage Vg is applied to the gate. Also, M
A MOS is connected between the source of the OS transistor M4 and the ground.
A transistor M5 is connected, and a diode-connected MOS transistor M6, M connected in series between the power supply Vdd and the ground is connected to the gate of the MOS transistor M5.
A bias voltage is applied by 7. The MOS transistor M5 has a function of passing a minute current through the MOS transistor M4.

In the potential detecting circuit 2 having the above structure, a potential value output corresponding to the potential under the gate is derived from the common source / drain connection point of the MOS transistors M4 and M5. Therefore, since the MOS transistor M4 has a structure near the portion using the boosted output voltage Vout, the potential value output of the potential detection circuit 2 has a value corresponding to the potential of the portion using the boosted output voltage Vout. That is,
By this potential detection circuit 2, the boosted output voltage V
The potential of the part using out can be detected.

FIG. 6 shows an example of a concrete circuit configuration of the comparator 4. In FIG. 6, a differential circuit is configured by a pair of MOS transistors M8 and M9 whose sources are commonly connected. The gate of the MOS transistor M8 is an inverting (-) input terminal, and the gate of the MOS transistor M9 is a non-inverting (+). It is the input end. MOS transistor M
MOS transistors M10 and M11 forming a current mirror circuit are connected between the respective drains of the power supply terminals 8 and M9 and the power supply Vdd. Also, the MOS transistors M8 and M9
A MOS transistor M12 is connected between the common connection point of the source and the ground.

A bias voltage is applied to the gate of the MOS transistor M12 by diode-connected MOS transistors M13 and M14 connected in series between the power supply Vdd and the ground. Further, the MOS transistor M1 connected in series between the power supply Vdd and the ground.
An output stage is constituted by 5, and M16, and the gate of the MOS transistor M15 is connected to the drain of the MOS transistor M9. A bias voltage is also applied to the gate of the MOS transistor 16 by the MOS transistors M13 and M14. Then, the comparator output is derived from the common drain connection point of the MOS transistors M15 and M16.

FIG. 7 shows an example of a concrete circuit configuration of the level shifter 4. In FIG. 7, MOS transistors M17 and M18 are connected in series between the power supply Vdd and the ground, and the gate of the MOS transistor M17 is an input terminal and MO.
The common source / drain connection point of the S transistors M17 and M18 serves as an output terminal. A bias voltage is applied to the gate of the MOS transistor M18 by resistors R1 and R2 connected in series between the power supply Vdd and the ground. In this level shifter 4, the shift level is determined by the voltage division level of the resistors R1 and R2, and the input level is shifted (shifted down) by this level in the down direction.

Since this booster circuit is for boosting the power supply voltage Vdd to generate the boosted output voltage Vout, the boosted output voltage Vout is naturally the power supply voltage Vd.
It becomes d or more. Therefore, in the circuit of FIG. 7, it is often necessary to slightly change the portion of the MOS transistor M17 that directly handles the boosted output voltage Vout when actually configuring the circuit. For example, as shown in FIG.
The S-transistor M17 is of a strong enhancement type, or, as shown in FIG. 9, the boosted output voltage Vout is applied to the drain of the MOS transistor M17 instead of the power supply voltage Vdd. This allows
Even if the boosted output voltage Vout is equal to or higher than the power supply voltage Vdd, the level shifter 4 can operate normally.

As described above, the booster 1 is constructed so that the boosted output voltage Vout is variable, and the boosted output voltage Vout is increased.
Is level-shifted by the level shifter 4 by a predetermined level, and then the detection voltage of the potential detection circuit 2 and the comparator 3 are detected.
And the comparison output is fed back to the booster 1 as the control voltage Vfb, so that the potential detected by the potential detection circuit 2 has an offset of a certain level (shift level in the level shifter 4). The boosted output voltage Vout can be obtained.

Here, the potential detected by the potential detection circuit 2 is the potential of the portion utilizing the boosted output voltage Vout, and therefore, with respect to variations in the power supply voltage Vdd and the frequencies of the clock pulses φ1 and φ2,
The booster circuit operates only so as to follow the potential of that portion. Therefore, a stable boosted output voltage Vout can be obtained even when the power supply voltage Vdd changes or the frequencies of the clock pulses φ1 and φ2 change.

In the present embodiment, the level shifter 4 is inserted in the feedback system, but this can be omitted. When the level shifter 4 is omitted, the boosted output voltage Vout equivalent to the potential detected by the potential detection circuit 2 can be obtained. The reason why the boosted output voltage Vout has an offset of a certain level will be described in a specific application example to a CCD linear sensor described later.

The booster circuit having the above-mentioned structure is used in a solid-state image pickup device such as a CCD linear sensor. FIG. 10 shows an example of the configuration of, for example, a CCD linear sensor equipped with the booster circuit according to the present invention. In FIG. 10, a sensor array 2 in which a large number of photoelectric conversion units (pixels) 21 are linearly arranged
2, a read-out gate 23 for reading out the signal charges photoelectrically converted by each photoelectric converter 21 and a CCD analog shift register 24 for transferring the read-out signal charges are provided on one side, and the other side is provided. The shutter gate 25 and the shutter drain 26 are arranged in the.

The CCD analog shift register 24 is provided with externally applied clock pulses φH1 and φH2 of opposite phases.
By being driven by two phases by, the signal charges read from the sensor array 22 are sequentially transferred. Shutter gate 2
When the shutter pulse φSHUT is applied from the outside, the signal 5 is swept away to the shutter drain 26 with the signal charge accumulated in each photoelectric conversion unit 11 of the sensor array 22. C
At the transfer destination end of the CD analog shift register 24,
For example, the charge-voltage converter 27 having a floating diffusion amplifier configuration is provided. The charge-voltage converter 27 converts the signal charge transferred by the CCD analog shift register 24 into a signal voltage. This signal voltage is output to the outside via the buffer 28.

The booster circuit 29 according to this embodiment described above is mounted on the same substrate (chip) as the CCD linear sensor having the above structure. In the booster circuit 29, the clock pulses φH1 and φH2 for the CCD analog shift register 24 are used as the clock pulses φ1 and φ2. As a result, in the circuit of FIG. 2, the clock pulses φH1 and φH2 may be directly applied as the clock pulses φ1 and φ2. Therefore, the circuit configuration of the booster circuit 19 is as follows.
The inverters 14 to 18 in FIG. 2 are unnecessary.

Boosted output voltage Vo by this booster circuit 29
ut is used as a drain voltage of the shutter drain 26, for example. FIG. 11 shows a cross section taken along line XY of FIG.
That is, the lateral cross section near the shutter drain 26 and its potential distribution are shown. Here, the boosted output voltage Vo
Considering the case where the variation of ut is large, the voltage value of the boosted output voltage Vout needs to be set so that the shutter operation is normally performed even when the boosted output voltage Vout is the lowest.

However, conversely, when the boosted output voltage Vout becomes high, the breakdown voltage between the substrate and the shutter drain is increased in the case of the P-type semiconductor substrate, and in the case of the N-type semiconductor substrate as shown in FIG. There arises a problem of punch-through between the substrate and the shutter drain via the well. Therefore, in the end, the power supply voltage range to be used and the operating frequency range have to be set narrower, which is a very inconvenient device from the side of using the device.

On the other hand, in terms of the original purpose of using the boosted output voltage Vout, it suffices if the shutter operation can be performed normally. Therefore, the boosted output voltage Vou is higher than the potential under the shutter gate 25 during the shutter operation.
The higher t is, the better. However, when the conventional booster circuit shown in FIG. 18 is used as the booster circuit for the linear sensor, this conventional circuit does not depend on the potential under the shutter gate 25 even if it depends on the characteristics of the MOS transistor. , Whether the boosted output voltage Vout is set high in consideration of the variation of the potential,
Alternatively, it becomes necessary to set the potential shallow. This results in the loss of design freedom and the problems of withstand voltage and punch-through described above.

However, by using the booster circuit according to this embodiment shown in FIG. 1 as the booster circuit for the linear sensor, and the potential detection circuit 2 detects the potential under the shutter gate 25, the shutter gate It is possible to generate the boosted output voltage Vout depending on the potential under 25. That is, FIG.
In the potential detection circuit 2, the MOS transistor M4 is a dummy transistor having a structure in the vicinity of the portion using the boosted output voltage Vout, that is, a structure of the shutter gate 25 portion. Further, as the gate voltage Vg of the MOS transistor M4, the shutter pulse φ
An ON voltage Von (= Vdd) of the SHUT is applied.

Then, in FIG. 1, the boosted output voltage Vo
After ut is shifted down by a predetermined level by the level shifter 4, the potential under the shutter gate 25 detected by the potential detection circuit 2 is compared by the comparator 3, and the comparison output is fed back to the booster unit 1 as the control voltage Vfb. , A boosted output voltage Vout having a constant level (shift level in the level shifter 4) offset, that is, a boosted output voltage Vou having a voltage value slightly higher than the potential under the shutter gate 25.
t can be obtained.

Here, the reason why the boosted output voltage Vout has an offset of a constant level will be described. As an example, the boosted output voltage Vout is set to 1 V by the level shifter 4.
Assuming that the level shift (level down) of
The boosted output voltage Vout has a voltage value that is approximately 1 V higher than the potential below the shutter gate 25. By implementing such a feedback control system, the boosted output voltage Vo of a voltage value that can always perform the shutter operation against variations in the potential under the shutter gate 25.
ut can be obtained.

Further, the power supply voltage Vdd and the clock pulse φ
Even with respect to the frequency variations of 1 and φ2, only the operation of following the potential under the shutter gate 25 is performed, so that a stable boosted output voltage Vout can be obtained. Of course, if the power supply voltage Vdd rises and the potential under the shutter gate 25 also rises accordingly, the boosted output voltage Vout will also follow it, but due to the action of the feedback control system described above, it will be unnecessarily high. Since it does not increase, the breakdown voltage between the substrate and shutter drain in the case of a P-type semiconductor substrate
The problem of punch-through between substrate and shutter drain does not occur in the case of die-type semiconductor substrate.

The booster circuit according to the present embodiment is a CCD.
Mounted on a linear sensor, the potential detection circuit 2 of FIG.
When the MOS transistor M4 is a dummy transistor having the structure of the shutter gate 25, the MOS transistor M4 may be a depletion type transistor. To address this,
As shown in FIG. 12, a level shifter 6 that shifts the gate voltage of the MOS transistor M4 in the down direction by a predetermined level is inserted in the preceding stage of the potential detection circuit 2. As a result, the MOS transistor M4 does not become a depletion type transistor, and the potential detection circuit 2 operates normally.

An example of a concrete circuit configuration of the level shifter 6 is shown in FIG. 13 together with the potential detection circuit 2. The level shifter 6 has a resistance voltage dividing circuit configuration including, for example, resistors R3 and R4, and has a shutter pulse φSH.
Down-shifting is performed by dividing the power supply voltage Vdd at the same level as the ON voltage Von of the UT, and the shifted voltage is applied to the gate of the MOS transistor M4.
Here, it is ideal to apply a voltage at which the potential under the shutter gate 25 is turned on to the gate of the MOS transistor M4, but in this example, from the viewpoint of circuit operation, a voltage downshifted by 2 V, for example. (Vdd-2
V) shall be applied.

As described above, when the level shifter 6 is inserted in the preceding stage of the potential detection circuit 2, the detection voltage of the potential detection circuit 2 is lowered by 2V as compared with the case of FIG. As shown, it is necessary to insert a level shifter 7 in the feedback system, which lowers the level of the system by 2V. The level shifter 7 may have the same circuit configuration as the level shifter 4, and the two level shifters 4 and 7 may be configured in common and the constants and sizes of the respective circuit elements may be appropriately selected to make a total. It is also possible to adopt a circuit configuration for performing level shift for two circuits.

Incidentally, some CCD linear sensors have a sensor structure in which the photoelectric conversion section is long in the signal charge reading direction in order to improve the sensitivity. Further, in a CCD linear sensor having such a sensor structure, a read afterimage due to read failure due to the sensor length,
Since the afterimage of the shutter due to the imperfect operation of the shutter becomes a problem, as a countermeasure against it, C
There is also a structure in which a shutter structure is arranged on the CD analog shift register side.

FIG. 14 shows a CC having this shutter structure.
It is a block diagram which shows the case where the booster circuit which concerns on this invention is mounted in a D linear sensor, In the figure, the same code | symbol is attached | subjected and shown to the equivalent part to FIG. In FIG. 14, a CCD array shift register 24 side of a sensor array 22 in which a large number of photoelectric conversion units 21 that are long in the signal charge reading direction are linearly arranged, that is, between the readout gate 23 and the CCD analog shift register 24. , A shutter structure including an island-shaped shutter drain 31, a shutter gate 32 provided on the sensor row 22 side, and transfer gates 33a and 33b provided on both sides of the shutter gate 32 has a pair of photoelectric conversion units 21 adjacent to each other. , 21 are provided one by one. Then, the booster circuit 29 according to the present invention is mounted on-chip, and the boosted output voltage Vout is used as the drain voltage of the shutter drain 31.

In the CCD linear sensor having the above structure,
During normal signal charge reading, the signal charges accumulated in each photoelectric conversion unit 21 are read out to the CCD analog shift register 24 via the read-out gate 23 and the transfer gates 33a and 33b, and transferred by the CCD analog shift register 24. The signal voltage is converted into a signal voltage by the charge-voltage converter 27, and then output to the outside via the buffer 28. On the other hand, during the shutter operation, the signal charges accumulated in the photoelectric conversion units 21 for two adjacent pixels are swept out to the shutter drain 31 via the shutter gate 32.

In the CCD linear sensor according to each of the above embodiments, the boosted output voltage Vou of the booster circuit 29 is used.
Although t is used as the drain voltage of the shutter drains 26 and 31, it is not limited to this.
For example, as shown in FIG. 15, a charge-voltage conversion unit 2 having a floating diffusion amplifier configuration including a floating diffusion (FD) 34, a reset gate (RG) 35, and a reset drain (RD) 36.
7, the drain voltage Vd of the reset drain (RD) 36 can also be used.

The CCD linear sensor equipped with the booster circuit 29 according to the present invention described above is an image sensor of a bar code reader which reads bar code information attached to a medium such as a product and outputs it as binarized information. AF (Automatic Focussing) of cameras equipped with an autofocus function
Used for sensors, etc. In particular, since the CCD linear sensor has a booster circuit mounted on-chip, it can be used with a low-voltage power source, and is therefore most suitable for a battery-driven bar code reader or camera. Specific configurations of a battery-driven bar code reader and a camera using the CCD linear sensor having the above configuration will be described below.

FIG. 16 is a block diagram showing an example of a battery-driven bar code reader according to the present invention. In FIG. 16, a bar code (not shown) attached to a medium 41 such as a product is illuminated by a light source 42, and the reflected light is incident on the light receiving surface of a CCD linear sensor 44 via an optical system 43 such as a lens. Read by. As the CCD linear sensor 44, the CCD linear sensor in which the booster circuit according to each of the above embodiments is mounted on-chip is used. Each operation of the CCD linear sensor 44, such as reading of signal charges, transfer, and electronic shutter, is performed based on various timing signals from the timing generator 45.

The output of the CCD linear sensor 44 is supplied to the binarization circuit 46. The binarization circuit 46 extracts a combination of lines having different thicknesses as binarization information and detects the binarization information as bar code information. As an example of this binarization processing, a method of obtaining binarization information while comparing the output voltage of the CCD linear sensor 44 with a predetermined threshold voltage by a comparator is adopted. This binarized signal is sent to the decoder 4
It is decoded at 7 and output as the final read information.

As described above, by using the CCD linear sensor 44 equipped with the booster circuit according to the present invention, the boosted output voltage Vout which is substantially stable is obtained in the booster circuit even when the power supply voltage changes or the clock frequency changes. In addition to being able to obtain the voltage, the potential of the portion that uses the boosted output voltage Vout is also strong, so that the battery can be operated sufficiently even with a battery power supply, and can further cope with lower voltage of the battery power supply. Type barcode reader can be provided.

FIG. 17 is a block diagram showing an example of a battery-driven camera according to the present invention having an autofocus function. In FIG. 17, the AF is provided in the camera body 51.
A CCD linear sensor 52 as a sensor, a peak hold circuit 53 that detects a peak value of an output signal from the CCD linear sensor 52, a timing generator 54 that generates various timing signals for driving the CCD linear sensor 52, and the like are built in. ing.

As an external circuit, an exposure adjusting circuit 55 for adjusting the exposure time by controlling the timing of the timing generator 54 based on the peak hold output PHout from the peak hold circuit 53, and the peak hold circuit 53 as they are. An arithmetic circuit 56 for calculating the focus shift amount based on the output CCD output of the CCD linear sensor 52, and moving the lens 57 in the optical axis direction based on the focus shift amount output from the arithmetic circuit 56. An AF control circuit 58 for performing focus adjustment is provided.

As described above, by using the CCD linear sensor 52 equipped with the booster circuit according to the present invention, the booster output voltage Vout that is substantially stable even when the power supply voltage changes or the clock frequency changes in the booster circuit. In addition to being able to obtain the voltage, the boosted output voltage Vout is strong against variations in the potential of the portion used, so that the autofocus can operate sufficiently even with a battery power supply and can further cope with a lower voltage of the battery power supply. It is possible to provide a battery-powered camera having a function.

[0062]

As described above, in the clock drive type booster circuit according to the present invention, at least the first stage of the unidirectional elements of a plurality of stages is composed of MOS transistors, and the gate voltage of the MOS transistors is controlled. With this configuration, the boosted output voltage can be changed according to the gate voltage. Therefore, when the power supply voltage changes or the clock frequency changes, the gate voltage is appropriately controlled to obtain a stable boosted output voltage. be able to.

In another clock drive type booster circuit according to the present invention, since the boosted output voltage can be changed according to the amplitude of the clock pulse by controlling the amplitude of the clock pulse, the power supply voltage can be changed. A stable boosted output voltage can be obtained by appropriately controlling the amplitude of the clock pulse when the clock frequency fluctuates or when the clock frequency fluctuates.

Further, in the solid-state image pickup device according to the present invention, by mounting the booster circuit capable of controlling the boosted output voltage on the basis of the potential of the portion utilizing the boosted output voltage, the booster circuit outputs the boosted output voltage. Since it operates in a manner that follows the potential of the part used, even if the power supply voltage fluctuates or the clock frequency fluctuates, a stable boosted output voltage can be obtained without being affected by it, and the boosted output voltage It is possible to obtain a boosted output voltage having a required voltage value even with respect to variations in the potential of the portion that uses the.

Further, in the bar code reader according to the present invention, the solid-state image pickup device having the booster circuit having the above-mentioned structure is used as an image sensor for reading a barcode, and in the camera according to the present invention, the booster circuit having the above-mentioned structure is mounted. By using the solid-state imaging device as an autofocus sensor, the booster circuit mounted on the solid-state imaging device can obtain a substantially stable boosted output voltage even when the power supply voltage changes or the clock frequency changes, and Since it also resists variations in the potential of the portion that uses the boosted output voltage, it can operate sufficiently even with a low-voltage power source such as a battery.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a circuit configuration of a booster unit.

FIG. 3 is a characteristic diagram showing dependence of a boosted output voltage on a control voltage.

FIG. 4 is a circuit diagram showing another example of the circuit configuration of the booster unit.

FIG. 5 is a circuit diagram showing an example of a circuit configuration of a potential detection circuit.

FIG. 6 is a circuit diagram showing an example of a circuit configuration of a comparator.

FIG. 7 is a circuit diagram showing an example of a circuit configuration of a level shifter.

FIG. 8 is a circuit diagram showing another example of the circuit configuration of the level shifter.

FIG. 9 is a circuit diagram showing still another example of the circuit configuration of the level shifter.

FIG. 10 is a configuration diagram showing an example of a linear sensor according to the present invention.

11 is a cross-sectional view taken along the line XY of FIG. 10 and its potential diagram.

FIG. 12 is a block diagram showing another embodiment of the present invention.

FIG. 13 is a circuit diagram showing a specific circuit configuration of another embodiment.

FIG. 14 is a configuration diagram showing another example of the linear sensor according to the present invention.

FIG. 15 is a configuration diagram showing another application example of the present invention.

FIG. 16 is a configuration diagram showing an example of a barcode reader according to the present invention.

FIG. 17 is a configuration diagram showing an example of a camera according to the present invention.

FIG. 18 is a circuit diagram showing a conventional example.

FIG. 19 is a timing waveform diagram in a steady state.

FIG. 20 is a timing waveform chart at the time of power supply fluctuation in the conventional example.

FIG. 21 is a characteristic diagram showing clock frequency dependence of a conventional example.

FIG. 22 is a timing waveform chart when the clock frequency changes in the conventional example.

[Explanation of symbols]

 1 Booster 2 Potential Detection Circuit 3 Comparator 4, 6, 7 Level Shifter 21 Photoelectric Converter 22 Sensor Array 23 Readout Gate 24 CCD Analog Shift Register 25 Shutter Gate 26 Shutter Drain

Claims (14)

[Claims] 1. A unidirectional element is connected in series between a power source and a circuit output terminal in a forward direction from a power source side toward a circuit output terminal side, and a clock is provided between each stage via a capacitor. A booster circuit configured to apply a pulse, wherein at least a first stage of a plurality of stages of unidirectional elements is composed of a MOS transistor, and a control circuit for controlling a gate voltage of the MOS transistor is provided. Boost circuit. 2. The control circuit compares a potential detection circuit that detects a potential of a portion that uses the boosted output voltage with a detection voltage of the potential detection circuit and the boosted output voltage, and based on the comparison output. The MOS
The booster circuit according to claim 1, further comprising a comparator that controls a gate voltage of the transistor. 3. The booster circuit according to claim 2, wherein the control circuit further includes a first level shifter that shifts the boosted output voltage by a predetermined level and supplies it to the comparator. 4. The control circuit further comprises a second level shifter for shifting the detection voltage of the potential detection circuit by a predetermined level, and an output voltage of the first level shifter for a shift amount of the second level shifter. 4. The booster circuit according to claim 3, further comprising a third level shifter that shifts only by. 5. A unidirectional element is connected in series in a forward direction from a power source side to a circuit output terminal side in a plurality of stages between a power source and a circuit output terminal, and a clock is provided between each stage via a capacitor. A booster circuit configured to apply a pulse, comprising a control circuit for controlling the amplitude of the clock pulse. 6. The control circuit compares a potential detection circuit for detecting a potential of a portion using the boosted output voltage with a detection voltage of the potential detection circuit and the boosted output voltage, and based on the comparison output. The booster circuit according to claim 5, further comprising a comparator that controls an amplitude of the clock pulse. 7. The booster circuit according to claim 6, wherein the control circuit further includes a first level shifter that shifts the boosted output voltage by a predetermined level and applies the same to the comparator. 8. The control circuit further comprises a second level shifter for shifting the detection voltage of the potential detection circuit by a predetermined level, and an output voltage of the first level shifter for the shift amount of the second level shifter. 8. The booster circuit according to claim 7, further comprising a third level shifter that shifts only by. 9. A unidirectional element is connected in series between a power source and a circuit output terminal in a forward direction from a power source side to a circuit output terminal side, and a clock is provided between each stage via a capacitor. A solid-state imaging device comprising a booster circuit configured to apply a pulse, the booster circuit having a control circuit for controlling the boosted output voltage based on a potential of a portion utilizing the boosted output voltage. . 10. The control circuit compares a potential detection circuit that detects a potential of a portion that uses the boosted output voltage with a detection voltage of the potential detection circuit and the boosted output voltage, and based on a comparison output thereof. 10. The solid-state imaging device according to claim 9, further comprising a comparator that controls the boosted output voltage. 11. The solid-state imaging device according to claim 10, wherein the control circuit further includes a first level shifter that shifts the boosted output voltage by a predetermined level and applies the same to the comparator. 12. The control circuit further comprises a second level shifter for shifting the detection voltage of the potential detection circuit by a predetermined level, and an output voltage of the first level shifter for a shift amount of the second level shifter. 12. The solid-state imaging device according to claim 11, further comprising a third level shifter that shifts only. 13. A unidirectional element is connected in series in a forward direction from a power source side to a circuit output terminal side in a plurality of stages between a power source and a circuit output terminal, and a clock is provided between each stage via a capacitor. A solid-state imaging device equipped with a booster circuit configured to be capable of controlling the boosted output voltage based on the potential of a portion that uses the boosted output voltage while a pulse is applied is used as an image sensor for reading a barcode. Bar code reader characterized by. 14. A camera having an autofocus function, wherein unidirectional elements are connected in series in a plurality of stages in a forward direction from a power source side to a circuit output terminal side between a power source and a circuit output terminal. In addition, a solid-state imaging device equipped with a booster circuit configured such that a clock pulse is applied between each stage via a capacitor and the boosted output voltage can be controlled based on the potential of a portion utilizing the boosted output voltage. , A camera characterized by being used as an autofocus sensor.