JP3552313B2 - Boost circuit and solid-state imaging device using the same - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a booster circuit and a solid-state imaging device using the same, and more particularly, to a clock-driven booster circuit and a solid-state imaging device using the same.
[0002]
[Prior art]
FIG. 6 shows a conventional example of a clock drive type booster circuit. In the figure, a so-called diode-connected N-channel MOSFET (hereinafter simply referred to as an NMOS transistor) M1n having a gate and a drain commonly connected is provided between a positive electrode side of a power supply 101 and a circuit output terminal 102. For example, three stages are connected in series in the forward direction from the side toward the circuit output terminal 102 side.
[0003]
To the output terminal N11 of the first-stage NMOS transistor M11, a clock pulse φ1 which is sequentially inverted and supplied by the three-stage inverters 103, 104 and 105 is applied via the capacitor C1. On the other hand, the output terminal N12 of the second-stage NMOS transistor M12 receives via the capacitor C2 a clock pulse φ2 having a phase opposite to that of the clock pulse φ1 which is sequentially inverted and supplied by the four-stage inverters 103, 104, 106 and 107. Is applied. A load capacitor CL is connected between the output terminal N13 (circuit output terminal 102) of the third-stage NMOS transistor M13 and the ground.
[0004]
Next, a boosting operation in a steady state of the conventional boosting circuit having the above configuration will be described with reference to a timing waveform diagram of FIG. First, when the clock pulse φ1 is at the “L” level, since the gate and the drain of the NMOS transistor M11 are connected to the positive electrode side of the power supply 101, the voltage V11 at the output terminal N11 is Vx11 higher than the power supply voltage Vdd. It is lower. Here, Vx11 is a voltage drop due to the threshold voltage Vth of the NMOS transistor M11. In this state, when the clock pulse φ1 is input via the capacitor C1, the voltage V11 at the output terminal N11 of the NMOS transistor M11 is boosted by the peak value of the clock pulse φ1.
[0005]
On the other hand, since the clock pulse φ2 has an opposite phase to the clock pulse φ1, when the clock pulse φ2 is at the “L” level, the voltage V12 at the output terminal N12 of the NMOS transistor M12 is Vx12 higher than the voltage V11 at the output terminal N11. It is lower. Here, Vx12 is a voltage drop due to the threshold voltage Vth of the NMOS transistor M12. In this state, when the clock pulse φ2 is input via the capacitor C2, the voltage V12 at the output terminal N12 of the NMOS transistor M12 is boosted by the peak value of the clock pulse φ2.
[0006]
The voltage V12 at the output terminal N12 is smoothed by the NMOS transistor M13 and the load capacitor CL, and is derived from the circuit output terminal 102 as the boosted output voltage Vout. The boosted output voltage Vout is lower than the voltage V12 at the output terminal N12 by Vx13. Here, Vx13 is a voltage drop due to the threshold voltage Vth of the NMOS transistor M13. As is apparent from the above description, in the clock-driven booster circuit, when the peak values of the clock pulses φ1 and φ2 are Vw, the power supply voltage Vdd is boosted by (Vw−Vx1n) for each stage. As a result, the boosted output voltage Vout is obtained.
[0007]
[Problems to be solved by the invention]
However, in the conventional booster circuit having the above-described configuration, when the power supply voltage Vdd changes, the amplitudes of the clock pulses φ1 and φ2 also change accordingly. Therefore, there is a problem that the fluctuation of the boosted output voltage Vout is large. Was. That is, in the case of the triple boosting circuit shown in FIG. 6, as shown in FIG. 9, when the power supply voltage Vdd increases by ΔVdd, the amplitudes of the clock pulses φ1 and φ2 also increase by approximately ΔVdd. The variation ΔVout of the boosted output voltage Vout is about 3 × ΔVdd. As described above, when the boosted output voltage Vout greatly fluctuates by a substantially multiple of the fluctuation ΔVdd with the fluctuation of the power supply voltage Vdd, the characteristics of devices and circuits operating at the boosted output voltage Vout of the booster circuit Will have an adverse effect.
[0008]
Still another problem is that the boosted output voltage Vout has a clock frequency dependency. That is, as shown in FIG. 8, as the clock frequency increases, the boosted output voltage Vout increases (= approaches the normal boosted value when the load current is small). FIG. 10 shows a timing waveform when the clock frequency changes. This frequency dependence occurs when the current consumption on the load side is greater than or equal to the current capacity of the booster circuit. The current capacity, or to increase the clock frequency, by the channel width of the MOS transistor is increased (increasing the mutual conductance g _m), it can be increased. Therefore, if the booster circuit is configured to have a sufficient margin for the current consumption on the load side, the clock frequency dependency does not occur.
[0009]
However, in order to do so, it is necessary to increase the size of each circuit element such as a MOS transistor and a capacitor constituting the booster circuit. Therefore, this booster circuit is used to generate a substrate voltage Vsub for a CCD linear sensor, for example. Taking the case of using as a booster circuit as an example, it may be difficult to manufacture (on-chip) on the same substrate (chip) as the sensor array of the CCD linear sensor, the charge transfer register, and the like.
[0010]
The present invention has been made in view of the above problems, and has as its object to reduce the variation ΔVout of the boosted output voltage Vout due to the variation of the power supply voltage Vdd and the clock frequency, and to reduce the power supply voltage and the clock frequency. An object of the present invention is to provide a stable booster circuit resistant to fluctuations and a solid-state imaging device using the same.
[0011]
[Means for Solving the Problems]
The booster circuit according to claim 1, wherein a unidirectional element is connected in series in a plurality of stages in a forward direction from the power supply side to the circuit output terminal side between the power supply and the circuit output terminal, and a clock is provided between each stage. A booster circuit in which a pulse is applied via a capacitor, wherein the booster circuit is connected between the circuit output terminal and a reference potential point, and an output voltage of a power supply connected to the one-way element is applied to a gate. It has a configuration including the name Ru load circuit from at least one of the MOS transistors.
[0012]
3. The booster circuit according to claim 2, wherein a unidirectional element is connected in series in a plurality of stages in a forward direction from the power supply side to the circuit output terminal side between the power supply and the circuit output terminal, and a clock is provided between each stage. pulse is a booster circuit is applied via the capacitor consists of at least two MOS transistors connected in series between the circuit output terminal and a reference potential point, and the gate of the at least two MOS transistors The configuration includes a load circuit to which a clock pulse having the same frequency as the clock pulse is applied.
[0013]
[Action]
In the booster circuit according to claim 1, when the power supply rises, the unidirectional elements in a plurality of stages are in a forward-biased state and thus are in a conductive state. Then, the boosting operation is performed by each one-way element in synchronization with clock pulses having opposite phases. In this state, when the power supply voltage fluctuates, the gate voltage of the MOS transistor in the load circuit also fluctuates, so that the current flowing through the MOS transistor changes according to the voltage fluctuation. Therefore, as a result, the fluctuation of the boosted output voltage with respect to the fluctuation of the power supply voltage is suppressed.
[0014]
In the booster circuit according to the second aspect, when the power supply rises, the unidirectional elements in a plurality of stages are in a forward-biased state and thus are in a conductive state. Then, the boosting operation is performed by each one-way element in synchronization with clock pulses having opposite phases. In this state, when the frequency of the clock pulse fluctuates, the frequency of the gate voltage of at least one MOS transistor of the load circuit also fluctuates, so that the current flowing through the load circuit changes according to the frequency fluctuation. Therefore, as a result, the fluctuation of the boosted output voltage due to the frequency fluctuation of the clock pulse can be suppressed. Further, even when the power supply voltage fluctuates, the current flowing through the load circuit changes, so that the fluctuation of the boosted output voltage with respect to the fluctuation of the power supply voltage can be suppressed.
[0015]
【Example】
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a circuit diagram showing a first embodiment of the present invention. In FIG. 1, an NMOS transistor Mn having a gate and a drain connected in common as a one-way element is provided between the power supply 1 and the circuit output terminal 2 between the positive electrode of the power supply 1 and the circuit output terminal 2. For example, three stages are connected in series in the forward direction. That is, the gate and drain of the first-stage NMOS transistor M1 are wired to the positive electrode side of the power supply 1, the gate and drain of the second-stage NMOS transistor M2 are wired to the source of the first-stage NMOS transistor M1, The gate and drain of the third NMOS transistor M3 are wired to the source of the second NMOS transistor M2, and the source of the third NMOS transistor M3 is wired to the circuit output terminal 2.
[0016]
Then, a clock pulse φ1 which is sequentially inverted and supplied by the inverters 3, 4, and 5 is applied to the output terminal (source) N1 of the first-stage NMOS transistor M1 via the capacitor C1. On the other hand, the output terminal (source) N2 of the second-stage NMOS transistor M2 receives via the capacitor C2 a clock pulse φ2 having a phase opposite to that of the clock pulse φ1 supplied and inverted in order by the inverters 3, 4, 6, and 7. Is applied. A load capacitor CL and a load circuit 8 are connected between the output terminal (source) N3 of the third-stage NMOS transistor M3 wired to the circuit output terminal 2 and the ground.
[0017]
The load circuit 8 includes, for example, an NMOS transistor M4 having a drain connected to the circuit output terminal 2 (the output terminal N3 of the NMOS transistor M3), a source grounded, and a power supply voltage Vdd applied to the gate. In this load circuit 8, the current flowing through the NMOS transistor M4 is set so as to be larger than the total load current flowing through the other portions. Specifically, it is preferable that the current flowing through the NMOS transistor M4 is set to be one digit larger than the sum of the other load currents. Further, the current flowing through the NMOS transistor M4 is set to be equal to about 1/10 with respect to the output current capacity of the booster circuit.
[0018]
Next, a boosting operation in the booster circuit according to the first embodiment having the above configuration will be described with reference to a timing waveform diagram of FIG. First, when the power supply 1 rises, the NMOS transistors M1 to M3 enter a forward-biased state, so that they are turned on (ON). In this state, when the clock pulse φ1 is at the “L” level, the voltage V1 at the output terminal N1 is higher than the power supply voltage Vdd because the gate and drain of the NMOS transistor M1 are connected to the positive electrode of the power supply 1. Vx1. Here, Vx1 is a voltage drop due to the threshold voltage Vth of the NMOS transistor M1.
[0019]
In this state, when the clock pulse φ1 is input via the capacitor C1, the voltage V1 at the output terminal N1 of the NMOS transistor M1 is boosted by the peak value of the clock pulse φ1. On the other hand, since the clock pulse φ2 has an opposite phase to the clock pulse φ1, when the clock pulse φ2 is at the “L” level, the voltage V2 at the output terminal N2 of the NMOS transistor M2 is Vx2 higher than the voltage V1 at the output terminal N1. It is lower. Here, Vx2 is a voltage drop due to the threshold voltage Vth of the NMOS transistor M2.
[0020]
In this state, when the clock pulse φ2 is input via the capacitor C2, the voltage V2 at the output terminal N2 of the NMOS transistor M2 is boosted by the peak value of the clock pulse φ2. The voltage V2 at the output terminal N2 is smoothed by the NMOS transistor M3 and the load capacitor CL, and is derived from the circuit output terminal 2 as the boosted output voltage Vout. The boosted output voltage Vout is lower than the voltage V2 at the output terminal N2 by Vx3. Here, Vx3 is a voltage drop due to the threshold voltage Vth of the NMOS transistor M3.
[0021]
Here, consider the case where the power supply voltage Vdd changes by, for example, ΔVdd to the higher side. When the power supply voltage Vdd increases, a boosting operation for increasing the boosted output voltage Vout is performed according to the variation ΔVdd. At this time, since the power supply voltage Vdd is also applied to the gate of the NMOS transistor M4 of the load circuit 8, the current flowing through the NMOS transistor M4 also increases according to the variation ΔVdd, and as a result, the boosted output voltage Vout Is suppressed.
[0022]
In the load circuit 8, the current flowing through the NMOS transistor M4 is set to be approximately equal to or about 1/10 of the output current capacity of the present booster circuit, as described above. Since the fluctuation positively affects the boosted output voltage Vout and is set to be larger than the total load current flowing through other than the NMOS transistor M4, the fluctuation of the boosted output voltage Vout with respect to the power supply voltage Vdd ΔVout can be minimized.
[0023]
In the first embodiment, the power supply voltage Vdd is directly applied to the gate of the NMOS transistor M4. However, the power supply voltage Vdd may be divided and applied. Although the load circuit 8 is constituted by an N-channel MOS transistor, a P-channel MOS transistor is used, its source is connected to the output terminal N3 of the NMOS transistor M3, its drain is grounded, and its gate is connected to the power supply voltage Vdd or this. It is also possible to adopt a configuration in which a voltage obtained by dividing the voltage is inverted and applied.
[0024]
FIG. 3 is a circuit diagram showing a second embodiment of the present invention. In the figure, the same parts as those in FIG. 1 are denoted by the same reference numerals. In the second embodiment, for example, three stages of a CMOS inverter composed of a PMOS transistor and an NMOS transistor connected in series between the output terminal N3 (circuit output terminal 2) of the NMOS transistor M3 and the ground (reference potential point) are provided. , And a clock pulse φ2 is applied to the input terminal (gate common connection point) of the first-stage CMOS inverter. In this load circuit 8 ', the CMOS inverter has a current characteristic that the average current is proportional to the frequency because the current flows in the transient portion of the input waveform. That is, the load circuit 8 'is a circuit in which current flows with clock frequency dependency.
[0025]
As described above, by connecting the load circuit 8 'through which the current flows as the load with the clock frequency dependency to the circuit output terminal 2 (the output terminal N3 of the NMOS transistor M3), the clock circuit becomes as shown in the timing waveform diagram of FIG. Even if the frequency of the pulses φ1 and φ2 fluctuates, for example, in a direction to increase, the current flowing through the load circuit 8 ′ increases in accordance with the fluctuation of the frequency, so that the fluctuation of the boosted output voltage Vout due to the frequency fluctuation can be suppressed. .
[0026]
The current flowing through the load circuit 8 'is also proportional to a change in the power supply voltage Vdd. That is, when the power supply voltage Vdd changes in a direction to increase, the potential of the output terminal N3 of the NMOS transistor M3 also tends to increase due to the boosting operation. However, the potential of the output terminal N3 increases and flows to the load circuit 8 '. The current increases. Therefore, as a result, the fluctuation of the boosted output voltage Vout with respect to the fluctuation of the power supply voltage Vdd can be suppressed.
[0027]
In the second embodiment, the load circuit 8 'is constituted by three-stage CMOS inverters. However, the present invention is not limited to this, and a structure in which a current proportional to the frequency of the clock pulses φ1 and φ2 flows. I just want it. For example, at least one stage of an NMOS inverter composed of two NMOS transistors or a PMOS inverter composed of two PMOS transistors connected in series between the circuit output terminal 2 and the ground is provided, and a clock is applied to the gate of one of the MOS transistors. Even with a load circuit configured to apply a pulse, a change in the boosted output voltage Vout with respect to a change in the power supply voltage Vdd can be suppressed.
[0028]
FIG. 5 is a configuration diagram showing an example of a solid-state imaging device using the booster circuit according to the above-described first or second embodiment as a Vsub generating booster circuit. In this example, a case where the present invention is applied to a CCD linear sensor as a solid-state imaging device is shown. However, the present invention is not limited to application to a CCD linear sensor, and is applicable not only to a CCD but also to any solid-state imaging device including an area sensor. Things. As shown in FIG. 5, the CCD linear sensor has a sensor array in which a plurality of light receiving units 11 including photodiodes or the like are arranged in a row to convert incident light into signal charges having a charge amount corresponding to the amount of light and accumulate the signal charges. And a charge transfer register 14 composed of a CCD for transferring signal charges read from each light receiving section 11 of the sensor array 12 via a read gate 13.
[0029]
The read gate 13 simultaneously reads the signal charges stored in each light receiving unit 11 of the sensor array 12 to the charge transfer register 14 by applying the read pulse φROG. The charge transfer register 14 transfers signal charges by being driven in two phases by the transfer clocks φH1 and φH2. At the last stage of the charge transfer register 14, a charge-to-voltage conversion unit (charge detection unit) 15 having, for example, a floating diffusion configuration for detecting the transferred signal charge and converting it into a voltage is formed. The output voltage of the charge-voltage converter 15 is derived as a CCD output from an output terminal 17 via a buffer 16.
[0030]
In the CCD linear sensor having the above configuration, the booster circuit according to the present invention is used as the Vsub generation booster circuit 18 that boosts the power supply voltage Vdd to generate the substrate voltage Vsub. The Vsub generation / boost circuit 18 is manufactured (on-chip) on the same substrate (chip) as the sensor array 12, the charge transfer register 14, and the like, and two-phase transfer clocks φH1 and φH2 are used as the clock pulses φ1 and φ2. .
It should be noted that the booster circuit according to the present invention can be used not only as the Vsub generating booster circuit 18 but also as a booster circuit for supplying an operation power supply voltage to other circuits such as the buffer 16.
[0031]
As described above, since the booster circuit according to the present invention is used as the Vsub generating booster circuit 18 and the booster circuit according to the present invention is resistant to power supply voltage fluctuation, even if the power supply voltage Vdd fluctuates, the substrate voltage Vsub Therefore, a stable CCD linear sensor resistant to power supply voltage fluctuations can be provided. In addition, since the number of components of the external circuit can be reduced by forming the booster circuit on a chip, the configuration can be simplified.
[0032]
【The invention's effect】
As described above, according to the first aspect of the present invention, in the clock drive type booster circuit, a load circuit including at least one MOS transistor connected between the circuit output terminal and the reference potential point is provided. Since the output voltage of the power supply connected to the unidirectional element is applied to the gate of the MOS transistor, the current flowing through the MOS transistor changes in accordance with the fluctuation of the power supply voltage. Fluctuations in output voltage can be suppressed.
[0033]
According to the second aspect of the present invention, in the clock-driven booster circuit, a load circuit comprising at least two MOS transistors connected in series between the circuit output terminal and a reference potential point is provided, at least two MOS With the configuration in which a clock pulse having the same frequency as the clock pulse for boosting drive is applied to the gate of the transistor , the current flowing through the load circuit changes in accordance with the fluctuation of the clock frequency and the fluctuation of the power supply voltage. Fluctuations in the boosted output voltage with respect to fluctuations and fluctuations in the power supply voltage can be suppressed.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a first embodiment of the present invention.
FIG. 2 is a timing waveform chart at the time of power supply fluctuation in the first embodiment.
FIG. 3 is a circuit diagram showing a second embodiment of the present invention.
FIG. 4 is a timing waveform chart when a clock frequency fluctuates in a second embodiment.
FIG. 5 is a configuration diagram of a CCD linear sensor according to the present invention.
FIG. 6 is a circuit diagram showing a conventional example.
FIG. 7 is a timing waveform diagram in a steady state in a conventional example.
FIG. 8 is a characteristic diagram showing clock frequency dependency of a boosted output voltage in a conventional example.
FIG. 9 is a timing waveform chart at the time of power supply fluctuation in the conventional example.
FIG. 10 is a timing waveform chart at the time of clock frequency fluctuation in a conventional example.
[Explanation of symbols]
1 Power supply 2 Circuit output terminal 3-7 Inverter 8, 8 'Load circuit

Claims (5)

Between the power supply and the circuit output terminal, is connected from the unidirectional element is the power supply side in a plurality of stages in series in a forward direction toward the circuit output terminal side, and a clock pulse between each stage via a capacitor applied A booster circuit,
Connected between the circuit output terminal and a reference potential point, further comprising a load circuit ing at least one MOS transistor having an output voltage is applied to power source connected to the unidirectional element to the gate Characteristic booster circuit. Between the power supply and the circuit output terminal, a unidirectional element is connected in series in a plurality of stages in a forward direction from the power supply side to the circuit output terminal side, and a clock pulse is applied between each stage via a capacitor. A booster circuit,
A load circuit comprising at least two MOS transistors connected in series between a circuit output terminal and a reference potential point, wherein a clock pulse having the same frequency as the clock pulse is applied to a gate of the at least two MOS transistors. A booster circuit comprising: A sensor section in which a plurality of light receiving sections for converting incident light into signal charges corresponding to the amount of light and storing the signal charges, and a charge for transferring signal charges read from each light receiving section of the sensor section A transfer register, a solid-state imaging device including a charge detection unit that detects signal charges transferred by the charge transfer register, converts the signal charges into electric signals, and outputs the electric signals.
A solid-state imaging device comprising the booster circuit according to claim 1. 4. The solid-state imaging device according to claim 3, wherein a boosted output voltage of said booster circuit is used as a substrate voltage. 4. The solid-state imaging device according to claim 3, wherein the booster circuit is formed on the same substrate as the sensor unit, the charge transfer register, and the charge detection unit.

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