KR100470991B1 - Boost circuit - Google Patents
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- KR100470991B1 KR100470991B1 KR1019970053200A KR19970053200A KR100470991B1 KR 100470991 B1 KR100470991 B1 KR 100470991B1 KR 1019970053200 A KR1019970053200 A KR 1019970053200A KR 19970053200 A KR19970053200 A KR 19970053200A KR 100470991 B1 KR100470991 B1 KR 100470991B1
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- 239000003990 capacitor Substances 0.000 claims abstract description 14
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- 239000004065 semiconductor Substances 0.000 description 2
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/148—Details of power up or power down circuits, standby circuits or recovery circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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Abstract
본 발명은 승압회로를 공개한다. 그 회로는 전원전압 인가단자과 출력단자사이에 직렬 연결된 공통 연결된 게이트 전극과 드레인 전극을 가진 복수개의 MOS트랜지스터들, 상기 복수개의 MOS트랜지스터들중 짝수번째 MOS트랜지스터들 각각의 게이트 전극과 드레인 전극의 공통점과 클럭신호사이 및 홀수번째 MOS트랜지스터들 각각의 게이트 전극과 드레인 전극의 공통점과 반전 클럭신호사이에 연결된 복수개의 캐패시터들, 및 상기 출력단자와 접지전압사이에 연결된 MOS캐패시터로 구성되어 있다. 따라서, 안정된 고전압을 발생할 수 있다.The present invention discloses a boosting circuit. The circuit includes a plurality of MOS transistors having a common connected gate electrode and a drain electrode connected in series between a power supply voltage applying terminal and an output terminal, and a common point of the gate electrode and the drain electrode of each of the even-numbered MOS transistors among the plurality of MOS transistors. A plurality of capacitors are connected between the clock signal and between the common and inverted clock signals of the gate electrode and the drain electrode of each of the odd-numbered MOS transistors, and a MOS capacitor connected between the output terminal and the ground voltage. Therefore, stable high voltage can be generated.
Description
본 발명은 승압회로에 관한 것으로, 특히 반도체 메모리 장치에 사용을 위한 승압회로에 관한 것이다.The present invention relates to a boost circuit, and more particularly to a boost circuit for use in a semiconductor memory device.
일반적으로, 반도체 IC제품은 단일 전원을 사용하나 일부 제품에서는 다레벨(multi-level)의 전원을 사용한다. 이러한 다레벨의 전원을 사용하는 집적회로 제품들은 외부 및 제품내부에서 전원을 발생하여 사용한다.In general, semiconductor IC products use a single power supply, but some products use multi-level power supplies. Integrated circuit products using these multilevel power sources generate and use power from outside and inside the product.
단일 전원으로 집적회로 내부에서 다레벨을 발생하여 사용하면 사용자 입장에서는 매우 편리하게 된다. 단일 전원은 5V 또는 그 이하의 전원을 사용하며, 전기적으로 소거가능하고 프로그램가능한 반도체 메모리 장치(EEPROM; electrically erasable programmable read only memory)는 집적회로에 공급되는 전원전압보다 훨씬 높은 약 20V의 전압을 내부에서 발생하여 셀의 쓰기(write) 및 소거(erase)시에 사용한다. Generating and using multiple levels inside an integrated circuit with a single power source is very convenient for the user. A single power supply uses 5V or less power, and electrically erasable programmable read only memory (EEPROM) internally provides a voltage of about 20V, much higher than the power supply to the integrated circuit. Generated from and used to write and erase cells.
그러나, 약 20V의 발생과정에서 안정하지 못한 고정압이 승압되어 EEPROM 셀이 불완전하게 쓰기/소거가 되며, 불안정한 고전압에 의해 내부 트랜지스터의 파괴와 전압 강하를 발생시킨다.However, during the generation of about 20V, an unstable fixed voltage is boosted, causing the EEPROM cell to be incompletely written / erased, resulting in destruction of the internal transistor and voltage drop due to unstable high voltage.
고전압 승압회로는 충전 캐패시터와 드레인 전극 및 게이트를 접속한 트랜지스터를 소정단 직렬접속한 것으로 트랜지스터의 필드 브레이크-다운(break-down) 전압에 의해서 전압 상승이 제한을 받도록 설계되어 있다. 그러나, 작은 트랜지스터의 필드 브레이크-다운 특성은 전류에 따라 브레이크-다운 전압이 변하는 곡선을 가지므로 고전압의 한계의 산포가 크므로 안정된 고전압을 갖지 못하게 된다.The high voltage boosting circuit is a transistor in which a charging capacitor, a drain electrode and a gate are connected in series, and is designed so that the voltage rise is limited by the field break-down voltage of the transistor. However, the field break-down characteristic of the small transistor has a curve in which the break-down voltage changes with the current, so that the dispersion of the limit of the high voltage is large, so that it does not have a stable high voltage.
이것은 고전압이 통과하는 회로에 손상을 줄 뿐만 아니라, EEPROM 셀의 특성에 영향을 주어 신뢰성을 떨어뜨릴 수 있다.This not only damages the circuit through which the high voltage passes, but also affects the characteristics of the EEPROM cell, thereby reducing its reliability.
본 발명의 목적은 안정된 고전압을 발생할 수 있는 승압회로를 제공하는데 있다.It is an object of the present invention to provide a boosting circuit capable of generating a stable high voltage.
이와같은 목적을 달성하기 위한 본 발명의 승압회로는 전원전압 인가단자과 출력단자사이에 직렬 연결된 공통 연결된 게이트 전극과 드레인 전극을 가진 복수개의 MOS트랜지스터들, 상기 복수개의 MOS트랜지스터들중 짝수번째 MOS트랜지스터들 각각의 게이트 전극과 드레인 전극의 공통점과 클럭신호사이 및 홀수번째 MOS트랜지스터들 각각의 게이트 전극과 드레인 전극의 공통점과 반전 클럭신호사이에 연결된 복수개의 캐패시터들, 및 상기 출력단자와 접지전압사이에 연결된 MOS캐패시터를 구비한 것을 특징으로 한다.According to an embodiment of the present invention, a boost circuit includes a plurality of MOS transistors having a gate electrode and a drain electrode connected in common between a power supply voltage supply terminal and an output terminal, and even-numbered MOS transistors among the plurality of MOS transistors. A plurality of capacitors connected between the common point and the clock signal of each gate electrode and the drain electrode and between the common point and the inverted clock signal of each of the gate and drain electrodes of the odd-numbered MOS transistors, and connected between the output terminal and the ground voltage. An MOS capacitor is provided.
이하, 첨부된 도면을 참고로 하여 본 발명의 승압회로를 설명하기 전에 종래의 승압회로를 설명하면 다음과 같다.Hereinafter, a description will be given of a conventional boosting circuit before explaining the boosting circuit of the present invention with reference to the accompanying drawings.
도1은 종래의 승압회로의 회로도로서, 전원전압(Vcc)과 출력전압(Vpp)사이에 공통 연결된 게이트 전극과 드레인 전극을 가진 NMOS트랜지스터들이 복수개 직렬 연결된 NMOS트랜지스터들(M0, M1, M2, M3, ..., M(n-1), Mn), 및 NMOS트랜지스터들(M0, M1, M2, M3, ..., M(n-1), Mn)들중 짝수번째 NMOS트랜지스터들 각각의 게이트 전극과 드레인 전극의 공통점과 클럭신호(CK)사이에 연결된 캐패시터들(C0, C2, ...C(n-1)), 및 홀수번째 NMOS트랜지스터들(M1, M3, ..., Mn) 각각의 게이트 전극과 드레인 전극의 공통점과 반전 클럭신호(CKB)사이에 연결된 캐패시터들(C1, C3, ..., Cn)로 구성되어 있다.1 is a circuit diagram of a conventional boosting circuit, in which a plurality of NMOS transistors M0, M1, M2, and M3 having a gate electrode and a drain electrode connected in common between a power supply voltage Vcc and an output voltage Vpp are connected in series. , ..., M (n-1), Mn), and each of the even-numbered NMOS transistors among the NMOS transistors M0, M1, M2, M3, ..., M (n-1), Mn. Capacitors C0, C2, ... C (n-1) connected between the common electrode of the gate electrode and the drain electrode and the clock signal CK, and odd-numbered NMOS transistors M1, M3, ..., Mn The capacitors C1, C3, ..., Cn are connected between the common point of each gate electrode and the drain electrode and the inverted clock signal CKB.
상술한 바와 같이 구성된 승압회로는 클럭신호(CK) 및 반전 클럭신호(CKB)를 이용하여 순차적으로 충전하여 출력전압(Vpp)을 20V이상으로 승압한다. EEPROM의 쓰기 동작시에 승압된 전압이 셀의 게이트 전극에 공급되어 데이타 라인으로 부터의 데이타를 셀에 저장하게 된다. 그리고, 읽어내기 동작시에는 셀의 게이트 전극에 전원전압(Vcc)이 그대로 인가되어 셀에 저장된 데이타를 데이타 선으로 전달하게 된다.The boosting circuit configured as described above is sequentially charged using the clock signal CK and the inverted clock signal CKB to boost the output voltage Vpp to 20V or more. During a write operation of the EEPROM, the boosted voltage is supplied to the gate electrode of the cell to store data from the data line in the cell. In the read operation, the power supply voltage Vcc is applied to the gate electrode of the cell as it is to transfer data stored in the cell to the data line.
도2는 도1에 나타낸 회로의 전류 대 브레이크-다운 전압의 변화를 나타내는 곡선이고, 도3은 도1에 나타낸 회로의 출력전압(Vpp) 제한 필드 브레이크-다운을 나타내는 것으로, 작은 트랜지스터의 필드 브레이크-다운 특성은 전류에 따라 브레이크-다운 전압이 변화하게 된다. 그래서, 전류 변화에 일정한 브레이크-다운 전압이 발생하여 안정된 고전압을 얻기 위해서는 매우 큰 폭(width)을 갖는 트랜지스터로 설계해야하며 그럴 경우 칩 사이즈가 매우 커지게 된다는 문제점이 있었다.FIG. 2 is a curve showing a change in current versus break-down voltage of the circuit shown in FIG. 1, and FIG. 3 shows an output voltage (Vpp) limited field break-down of the circuit shown in FIG. The -down characteristic causes the breakdown voltage to change with current. Therefore, in order to generate a stable breakdown voltage due to a constant break-down voltage in the current change, it is necessary to design a transistor having a very large width, in which case there is a problem that the chip size becomes very large.
상술한 종래 기술의 문제점을 위해서 본 발명에서는 브레이크-다운으로 승압 고전압을 제한하기 않고, 전류 변화에 따라 브레이크-다운의 영향이 거의 없는 트랜지스터의 접합 브레이크-다운에 의해 제한되도록 하여 안정한 고전압을 발생하도록 하였다.In order to generate a stable high voltage, the present invention does not limit the boosted high voltage to the break-down, but is limited by the junction break-down of the transistor having little effect of the break-down according to the current change. It was.
도4는 본 발명의 승압회로의 회로도로서, 도1에 나타낸 종래의 회로의 출력전압(Vpp)과 접지전압(GND)사이에 NMOS캐패시터(C)를 추가하여 구성되어 있다. 즉, 출력전압(Vpp) 단에 NMOS캐패시터(C)의 소오스 전극과 드레인 전극을 공통 연결하고 게이트 전극을 접지전압에 추가로 연결하여 구성하였다.Fig. 4 is a circuit diagram of the boosting circuit of the present invention, in which an NMOS capacitor C is added between the output voltage Vpp and the ground voltage GND of the conventional circuit shown in Fig. 1. That is, the source and drain electrodes of the NMOS capacitor C are commonly connected to the output voltage Vpp, and the gate electrode is further connected to the ground voltage.
이와같이 구성함으로써 트랜지스터의 채널 부분의 접합에서 브레이크 다운이 발생하도록 하여 종래의 승압회로의 필드 브레이크-다운에 의해서 브레이크-다운 전압이 제어되는 것이 아니라 추가된 NMOS캐패시터의 접합 브레이크-다운에 의해서 브레이크-다운 전압이 제어된다.In such a configuration, breakdown occurs at the junction of the channel portion of the transistor so that the breakdown voltage is not controlled by the field breakdown of the conventional boost circuit, but instead the breakdown is caused by the junction breakdown of the added NMOS capacitor. The voltage is controlled.
도5는 도4에 나타낸 회로의 전류 대 브레이크-다운 전압의 변화를 나타내는 곡선으로, 전류의 변화에 대하여 브레이크-다운 전압이 일정함을 알 수 있다. 도6은 도4에 나타낸 회로의 출력전압(Vpp) 제한 접합 브레이크-다운을 나타내는 것으로, NMOS캐패시터의 채널 부분의 접합에서 브레이크-다운이 발생하는 것을 나타내었다.FIG. 5 is a curve showing a change in current versus breakdown voltage of the circuit shown in FIG. 4, and it can be seen that the breakdown voltage is constant with respect to the change in current. FIG. 6 shows the output voltage (Vpp) limiting junction break-down of the circuit shown in FIG. 4, showing that break-down occurs at the junction of the channel portion of the NMOS capacitor.
본 발명의 회로는 NMOS캐패시터의 접합 브레이크-다운에 의해서 고전압이 제한되어 뒷단의 회로에 손상을 주기 않을 뿐만아니라 공정의 변화에 안정된 고전압을 얻을 수 있어 EEPROM 셀의 특성 및 신뢰성을 향상시킬 수 있다.In the circuit of the present invention, the high voltage is limited by the junction break-down of the NMOS capacitor, which not only damages the circuit of the rear stage but also obtains a stable high voltage in process changes, thereby improving the characteristics and reliability of the EEPROM cell.
본 발명의 승압회로는 안정된 고전압을 발생하여 뒷단의 회로에 손상을 주지 않을 뿐만아니라 EEPROM 셀의 특성 및 신뢰성을 향상시킬 수 있다.The boosting circuit of the present invention generates a stable high voltage and does not damage the circuit of the rear stage, and can improve the characteristics and reliability of the EEPROM cell.
도1은 종래의 승압회로의 회로도이다.1 is a circuit diagram of a conventional boost circuit.
도2는 도1에 나타낸 회로의 전류 대 브레이크-다운 전압의 변화를 나타내는 곡선이다.FIG. 2 is a curve showing the change in current versus break-down voltage of the circuit shown in FIG.
도3은 도1에 나타낸 회로의 필드 브레이크-다운을 나타내는 것이다.FIG. 3 shows field break-down of the circuit shown in FIG.
도4는 본 발명의 승압회로의 회로도이다.4 is a circuit diagram of a boost circuit of the present invention.
도5는 도4에 나타낸 회로의 전류 대 브레이크-다운 전압의 변화를 나타내는 곡선이다.FIG. 5 is a curve showing the change in current versus break-down voltage of the circuit shown in FIG.
도6은 도4에 나타낸 회로의 접합 브레이크-다운을 나타내는 것이다.FIG. 6 shows the junction break-down of the circuit shown in FIG.
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| KR100470991B1 true KR100470991B1 (en) | 2005-07-11 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06311732A (en) * | 1993-04-22 | 1994-11-04 | Toshiba Corp | Booster circuit |
| JPH08181918A (en) * | 1994-12-22 | 1996-07-12 | Sony Corp | Booster circuit and solid-state image pickup device using same |
| JPH098229A (en) * | 1995-06-26 | 1997-01-10 | Seiko Instr Inc | Semiconductor integrated circuit device and electronic equipment |
| JPH0936307A (en) * | 1995-07-21 | 1997-02-07 | Samsung Electron Co Ltd | Mos capacitor |
-
1997
- 1997-10-17 KR KR1019970053200A patent/KR100470991B1/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06311732A (en) * | 1993-04-22 | 1994-11-04 | Toshiba Corp | Booster circuit |
| JPH08181918A (en) * | 1994-12-22 | 1996-07-12 | Sony Corp | Booster circuit and solid-state image pickup device using same |
| JPH098229A (en) * | 1995-06-26 | 1997-01-10 | Seiko Instr Inc | Semiconductor integrated circuit device and electronic equipment |
| JPH0936307A (en) * | 1995-07-21 | 1997-02-07 | Samsung Electron Co Ltd | Mos capacitor |
Also Published As
| Publication number | Publication date |
|---|---|
| KR19990032217A (en) | 1999-05-15 |
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| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
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