JP2007323684A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit in which a capacity element included in a charge pump circuit of an on-chipped nonvolatile memory can be minimized. <P>SOLUTION: Inside of a semiconductor integration (1), when first power source voltage (Vcc) > second power source voltage (Vddm) > third power source voltage (Vddc) having comparatively different level can be utilized, in a memory power source circuit (33) generating high voltage for changing threshold voltage of a nonvolatile memory (4), relatively low power source voltage (Vddm) is used for the charge pump circuit (51) being required to suppress ripple of output voltage as a driver (51B) of a pump capacitor and area of a smoothing capacitor (53) is reduced, and relatively high level power source voltage (Vcc) is used for the charge pump circuit (52) being necessary current supply capability rather than suppression of ripple as a driver (52B) of the pump capacitor and area of a pump capacitor is reduced. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit including a central processing unit and a nonvolatile memory controlled to be rewritten by the central processing unit, and more particularly to a technology for generating an internal power source for rewriting control, for example, a technology effective when applied to a one-chip microcomputer. About.

  One-chip microcomputer accepts a single power supply such as 5V or 3.3V that is generally used as an external interface from the outside, and lowers this to use it as the operating power supply for the core circuit, thus supporting low-voltage operation To do. There is also a microcomputer that operates by directly receiving an operating power supply of the core circuit from the outside. Here, in a microcomputer in which a nonvolatile memory such as an electrically rewritable flash memory is on-chip, the nonvolatile memory requires a plurality of types of high voltages for erasing and writing. For example, when performing hot electron writing, 10 V is applied to the word line and 6 V is applied to the bit line, and hot electrons generated by flowing a drain current are accumulated in the floating gate. When erasing is performed by the FN tunnel, −10 V is applied to the word line and 6 V is applied to the source line, and electrons are released from the floating gate by the FN tunnel current. Alternatively, erasing can be performed by applying 18 V to the word line and 0 V to the well region. As described above, various high voltages are required for erasing and writing in a nonvolatile memory represented by a flash memory.

  A conventional on-chip flash memory is equipped with a charge pump circuit for generating a high voltage for erasing and writing, as described in Japanese Patent Application Laid-Open No. H10-228707.

JP 2003-77283 A

  The present inventor has examined a charge pump circuit in an on-chip flash memory of a microcomputer. According to a high voltage application target, the present invention requires a current supply capability, generates a high voltage, and generates a voltage. It became clear that a small fluctuation (ripple) was necessary. Generally, in order to ensure current supply, it is necessary to increase the pump capacity that is sequentially phase-inverted and driven at each boosting node. In order to generate a high voltage, the number of boosting stages of the charge pump circuit must be increased. In order to sufficiently reduce the ripple, it is necessary to connect a relatively large smoothing capacitor to the output node of the boosted voltage. In response to such demands, it has been clarified that the pump capacity and the like increase even if an external power source with a high voltage level such as 5V or a core power source with a low voltage level such as 1.5V is used. For example, in a circuit that generates a high voltage using an external power source such as 5 V for the charge pump circuit, a smoothing capacitor having a large area is required to suppress ripple. On the other hand, when a core power supply such as 1.5 V is used, the power generated in the unit capacity value of each pump capacity is small or applied to the first boosting stage because the amplitude of the clock for phase inversion driving of the pump capacity is small Since the boosting start voltage (start voltage) is reduced, the number of boosting stages of the charge pump must be increased, and the circuit area increases due to the pump capacity. The technique of Patent Document 1 does not consider the relationship between the chip area used for the pump capacity and the stabilization capacity used in the charge pump circuit and the operating power supply voltage level of the charge pump circuit.

  An object of the present invention is to provide a semiconductor integrated circuit capable of reducing the capacity element included in a charge pump circuit of an on-chip nonvolatile memory.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application. That is, when the first power supply voltage to the third power supply voltage (first power supply voltage> second power supply voltage> third power supply voltage) having relatively different levels in the semiconductor integrated circuit are available, the threshold value of the nonvolatile memory In a memory power supply circuit that generates a high voltage for changing the voltage, an operating power supply is appropriately allocated to a charge pump circuit or the like. For example, a charge pump circuit that needs to suppress the ripple of the output voltage uses a relatively low power supply voltage as a driver for the pump capacitor to reduce the area of the smoothing capacitor and requires a current supply capability rather than ripple suppression. The charge pump circuit uses a relatively high level power supply voltage as a drive driver for the pump capacity to reduce the area of the pump capacity. The first power supply voltage is used as the start voltage of the charge pump circuit that generates a voltage higher than the first power supply voltage. The form of appropriate allocation of the power supply voltage will be described in detail below.

<< Power supply voltage of the driver that drives the pump capacity >>
A semiconductor device according to the present invention is a non-volatile device having a source and a drain constituting a transistor, a charge storage region and a memory gate, which are stacked on and insulated from each other via an insulating film on a channel formation region therebetween. The nonvolatile memory cell array in which the memory cells are arranged in an array and the second power supply voltage obtained by stepping down the first power supply voltage supplied from the outside of the semiconductor device are supplied, and the first power supply voltage higher than the first power supply voltage is received. 1 and a first charge pump circuit capable of supplying the first high voltage to the memory gate of the nonvolatile memory cell, and receiving the first power supply voltage, the first power supply voltage A second charge pump that generates a higher second high voltage and can supply the second high voltage to the source or drain of the nonvolatile memory cell.

  According to the semiconductor device, since it is difficult to be affected by fluctuations in the first power supply voltage, a stable first high voltage is applied to the memory gate. In addition, since the second high voltage is generated in response to the supply of the first power supply voltage supplied from the outside, it is easy to supply the charge to the source or drain.

  As one specific form of the present invention, the output of the first charge pump circuit has a smoothing capacitive element that stabilizes the output voltage of the first charge pump circuit. In the nonvolatile memory array, When changing the threshold voltage of the nonvolatile memory cell, the number of memory cell gates driven by the output voltage of the first charge pump circuit can be changed. According to this, even if the number of memory cell gates driven by the output voltage of the first charge pump circuit is changed, the first charge pump circuit receives the supply of the second power supply voltage, Since the output is less likely to cause ripples, the area of the smoothing capacitive element can be suppressed.

  As a more specific form of the present invention, a central processing unit for controlling the nonvolatile memory is further provided, and the third power supply voltage, which is lower than the second power supply voltage and lowers the first power supply voltage, is the first power supply voltage. And the second high voltage are generated independently, and this third power supply voltage is supplied to the central processing unit. According to this, since the third power supply voltage is generated independently of the first high voltage and the second high voltage, the central processing unit can be operated without being affected by the fluctuation of the high voltage.

  As a more specific form of the present invention, the change of the threshold voltage for the nonvolatile memory cell includes an erase operation for lowering the threshold voltage and a write operation for increasing the threshold voltage.

  For example, the first charge pump circuit generates a voltage used for the write operation. At this time, the second charge pump circuit forms a voltage to be applied to the drain or source in order to generate hot electrons in the write operation. The first charge pump circuit generates a voltage used for an erase operation.

《Starting voltage of pump capacity first stage》
As another specific mode of the present invention, the memory power supply circuit includes a third charge pump that generates a low-potential-side voltage supplied to the memory gate of the nonvolatile memory cell when the change of the threshold voltage is not selected. It further has a circuit (65). The third charge pump circuit uses the pump capacitor element (Cp) as a start voltage that starts to be boosted as the second power supply voltage (Vddm). The first charge pump circuit (51) uses the pump voltage element (Cp) to start boosting the first power supply voltage (Vcc), that is, a voltage higher in level than the first power supply voltage. A first power supply voltage is used as a start voltage of the first charge pump circuit that generates the second power, and a second voltage is used as the start voltage of the third charge pump circuit that generates a voltage lower than the first power supply voltage. Use the power supply voltage. When generating a voltage lower than the first power supply voltage using the first power supply voltage as the start voltage, the output of the charge pump circuit must be pulled down with a resistor, resulting in a wasteful current leakage and a wasteful pump capacity. Become bigger. In this respect, the third charge pump circuit does not cause useless current leakage, can reduce the pump capacity, and contributes to the reduction of the chip occupation area.

<Combination of step-down circuit>
The memory power supply circuit further includes a step-down circuit (67) that generates a low-potential-side voltage supplied to the memory gate of the nonvolatile memory cell when the change of the threshold voltage is not selected. The clamp circuit uses a second power supply voltage as an operating power supply, and the first charge pump circuit uses a start voltage that starts boosting using a pump capacitor as the first power supply voltage.

<Stabilization of power supply for reference voltage generator>
The charge pump circuit inputs a comparison result (61) for comparing the boosted voltage (Vpp1) and the reference voltage (Vref), and a comparison result by the comparison circuit. When the boosted voltage is below the reference voltage, the capacitor elements are sequentially phased. An external interface circuit that further includes a gate circuit (NOR) that supplies drive clock signals (CLK1pd, / CLK1pd) for inversion drive and stops the supply of the drive clock signal when the boosted voltage exceeds a reference voltage When the first power supply voltage is the operating power supply, the reference voltage generating circuit that generates the reference voltage uses the second power supply voltage as the operating power supply. The reference voltage can be stabilized by using the stable second power supply voltage (Vddm).

<< First to third power supply voltages >>
As other usage forms of the first power supply voltage to the third power supply voltage (first power supply voltage> second power supply voltage> third power supply voltage) having relatively different levels that can be used inside the semiconductor integrated circuit, the first power supply is used. An external interface circuit (6) using a voltage as an operating power supply, and a PLL circuit (7A) using the second power supply voltage as an operating power supply, wherein the central processing unit operates in synchronization with a clock signal generated by the PLL circuit. The third power supply voltage is an operation power supply.

  As a first form of power generation, an external power supply terminal (P1) that receives the first power supply voltage, a step-down circuit (40) that generates the second power supply voltage from the first power supply voltage, and the second power supply voltage And a step-down circuit (41) for generating the third power supply voltage. As a second form, the power supply device includes an external power supply terminal that receives the first power supply voltage, an external power supply terminal that receives the third power supply voltage, and a step-down circuit that generates the second power supply voltage from the first power supply voltage.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. That is, the capacity element included in the charge pump circuit of the on-chip nonvolatile memory can be reduced.

<Microcomputer>
FIG. 2 shows a microcomputer (MCU) 1 which is an example of a semiconductor integrated circuit according to the present invention. The microcomputer 1 is not particularly limited, but is formed on a single semiconductor substrate (semiconductor chip) such as single crystal silicon by a CMOS integrated circuit manufacturing technique or the like. The microcomputer 1 includes an external input such as a central processing unit (CPU) 2, a RAM 3 as a volatile memory, a flash memory (FLASH) 4 as a nonvolatile memory, a bus state controller (BSC) 5, and an input / output port circuit. An output circuit (I / O) 6, a clock generator (CPG) 7, a power supply circuit (PSUP) 8, a system controller (SYSC) 9 and the like are provided, and these circuit modules are connected to an internal bus 10. The internal bus 10 includes signal lines for address, data, and control signals. The CPU 2 includes an instruction control unit and an execution unit, decodes the fetched instruction, and performs arithmetic processing according to the decoding result. The flash memory 4 stores an operation program and data for the CPU 2. The RAM 3 is a work area or a data temporary storage area of the CPU 2. The operation of the flash memory 4 is controlled based on control data set by the CPU 2 in a control register (not shown) of the flash memory. The bus state controller 5 controls internal circuit module access via the internal bus 10 and controls the number of access cycles, wait state insertion, bus width, and the like for the external bus access 10 via the input / output circuit 6. The system controller 9 controls the operation mode of the microcomputer 1 in response to the reset signal RST and the mode signal MD. The clock pulse generator 7 receives the system clock CLK, and the PLL circuit 7A generates an internal clock that is phase-synchronized with the system clock CLK. The generated internal clock signal and its divided clock signal are sent to the internal circuit module as a synchronous clock signal. Supplied.

  The microcomputer, for example, inputs a first power supply voltage Vcc such as 5V from the outside through the external terminal input P1, and steps down this by the power supply circuit 8 to provide a second power supply voltage Vddm such as 3.3V and 1.5V. A third power supply voltage Vddc is generated. In the microcomputer 1, the first to third power supply voltages Vcc, Vddm, and Vddc can be used, and the PLL circuit 7A uses the second power supply voltage Vddm as an operation power supply. The external input / output circuit uses the first power supply voltage Vcc as the main operating power supply, and a level conversion circuit between the third power supply voltage Vddc and the first power supply voltage Vcc is arranged at the interface with the internal bus 10. The The third power supply voltage Vddc is a core power supply and is an operation power supply for other circuits. In particular, the flash memory 4 uses the first and second power supply voltages Vcc and Vddm as operation power supplies for generating a high voltage higher than the first power supply voltage Vcc for erasing and writing. The ground voltage Vss is supplied from the external terminal P2.

《On-chip flash memory》
FIG. 3 shows an example of the flash memory 4. The flash memory 4 has a memory array (MARY) 21 in which a plurality of nonvolatile memory cells MC (MC11 to MCmn) are arranged in a matrix. In the plurality of nonvolatile memory cells MC arranged in a matrix, the memory gate 10 is connected to the memory gate line MGL constituting the word line, the source is connected to the source line SL, and the drain is connected to the bit line BL. The X address decoder (XDEC) and driver (XDRV) 22 decode the X address signal input to the address buffer (ADB) 23. The memory gate line MGL and the source line SL are driven according to the decoding result. The drive mode is determined according to the operation mode (read, erase, write) of the flash memory. The X address signal is supplied from the address bus 10A of the internal bus 10 to the address buffer 23.

  The bit line BL is connected to a write circuit (PGM) 25 on one side. The write circuit 25 includes a write control circuit (PGMCNT) 26 and a data latch circuit (DLAT) 27. The data latch circuit 27 latches write data, and the write control circuit 26 controls the write voltage of the bit line BL according to the latched write data. A Y switch circuit and a Y decoder (YSW / YDEC) 29 are connected to the other side of the bit line BL, and the Y decoder (YDEC) decodes the Y address signal input to the address buffer (ADB) 23. The Y switch (YSW) selects the bit line BL according to the decoding result of the Y decoder (YDEC), and the read data on the selected bit line BL is amplified by the sense amplifier circuit (SAA) 30 and input / output circuit (IO) 31 to the data bus 10D of the internal bus 10. In the write operation, the write data supplied from the data bus 10D of the internal bus 1 to the input / output circuit 31 is supplied to the bit line BL selected by the Y switch (YSW). The selection of the Y switch (YSW) is similarly performed according to the decoding result of the Y decoder (YDEC). The Y address signal is supplied from the address bus 10A of the internal bus 10 to the address buffer 23.

  The memory power supply circuit (MPS) 33 generates a high voltage required for erasing and writing of the nonvolatile memory cell MC. The memory power supply circuit 33 generates a high voltage using the first to third power supply voltages Vcc, Vddm, and Vddc. The control circuit (CONT) 34 performs read, erase, and write control sequences and operation power supply switching control in accordance with control information set in the control register (CREG) 35. The operation power supply switching control is control for appropriately switching the operation power supply of the driver (XDRV) and the write control circuit 26 according to the operation mode in accordance with reading, erasing, and writing. An oscillation circuit (OSC) 36 generates a synchronous clock signal for the memory power supply circuit 33 and the control circuit 34.

  Although not particularly limited, here, the nonvolatile memory cell MC will be described as a stacked gate structure having a floating gate. In the nonvolatile memory cell MC, a channel region is formed between a source connected to the source line SL and a drain connected to the bit line BL, and a floating gate is formed on the channel region via a gate insulating film. A memory gate is formed thereon via an oxide film. The memory gate constitutes a part of a memory gate line (word line) MGL made of, for example, polysilicon. Here, the source in the n-channel nonvolatile memory cell MC is defined as a downstream terminal of a current path formed by being turned on in a read operation, for example. The source and drain in the MOS transistor are relative names determined by the direction of the current of the terminal voltage, and it is not hindered to define the source based on another operation.

  In hot carrier writing to the non-volatile memory cell MC having a stacked gate structure, the write target bit line BL is set to 6V, the source line SL is set to 0V, a channel current is passed, and the write target memory gate line MGL is set to 10V. Hot electrons generated at the drain end of the memory cell are injected into the floating gate. Erasing is performed by setting the memory gate line MGL to 18V, the source line SL and the well region to 0V, and drawing the electrons of the floating gate to the memory gate line MGL.

  FIG. 4 shows an example of the power supply circuit 8 of the microcomputer 1. The power supply circuit 8 steps down the first power supply voltage Vcc to generate the second power supply voltage Vddm, and the power supply circuit 8 steps down the second power supply voltage Vddm to generate the third power supply voltage Vddc. And a step-down circuit (LDS) 41. The step-down circuits 40 and 41 are not particularly shown, but may be constituted by a known level shift circuit or clamp circuit.

  Here, an example is shown in which the third power supply voltage Vddc is generated from the second power supply voltage Vddm, but the third power supply voltage Vcc does not pass through the second power supply voltage Vddm. The voltage Vddc may be generated. The former is more excellent in the stability of the third power supply voltage Vddc because it passes through a two-stage step-down circuit. The memory power supply circuit 33 of the flash memory 4 uses the first power supply voltage Vcc and the second power supply voltage Vddm to generate a high voltage for erasing and writing.

<< Pump capacity drive amplitude in charge pump circuit >>
FIG. 1 shows an example of the memory power supply circuit 33. In the figure, for example, a first charge pump circuit (CPMP1) 51 applicable to generation of a high voltage to be applied to the memory gate line MGL at the time of erasing or writing, and generation of a high voltage to be applied to the bit line BL at the time of writing. The applicable second charge pump circuit (CPMP2) 52 is exemplified. A smoothing capacitor 53 is provided at the output terminal of the first charge pump circuit 51, and the high voltage Vpp 1 generated by the first charge pump circuit 51 is used as an operating power supply for the driver 55. A smoothing capacitor 54 is provided at the output terminal of the second charge pump circuit 52, and the high voltage Vpp 2 generated by the second charge pump circuit 52 is used as an operating power supply for the driver 56. Driver 55 drives memory gate line MGL with high voltage Vpp1 in accordance with a write operation or an erase operation. When the drive voltage of the memory gate line MGL is different between the write operation and the erase operation as described above, there is no particular limitation. However, the higher level higher voltage is stepped down by the clamp circuit, and the lower level higher voltage is applied. A voltage is generated, and any high voltage may be selected and used according to the operation. The driver 56 drives the bit line BL with the high voltage Vpp2 in the write operation. FIG. 1 typically shows one nonvolatile memory cell MC, but the high voltages Vpp1 and Vpp2 are actually used for erasing and writing to a large number of nonvolatile memory cells MC, and the high voltage Vpp1 is nonvolatile. Applied to the memory gate MGL of the memory cell MC, the high voltage Vpp2 is applied to the drain of the nonvolatile memory cell MC. In addition, one driver is also representatively shown, but actually, a plurality of drivers are provided in units of memory gate lines and bit lines. In the nonvolatile memory cell MC of FIG. 1, MG is a memory gate, SND is a floating gate, SOC is a source, DRN is a drain, and CHN is a channel formation region.

  The first charge pump circuit 51 includes a charge pump (PUMP) 51A, a clock driver 51B, and a pump control circuit (PCNT) 51C. The clock driver 51B uses the second power supply voltage Vddm as an operation power supply and pump lock CLKp. The pump drive clocks CLK1pd and / CLK1pd having an amplitude defined by the second power supply voltage Vddm are output in synchronization with the first power supply voltage Vddm. The second charge pump circuit 52 includes a charge pump (PUMP) 52A, a clock driver 52B, and a pump control circuit (PCNT) 52C. The clock driver 52B uses the first power supply voltage Vcc as an operating power supply, and pump lock CLKp The pump drive clocks CLK2pd and / CLK2pd having an amplitude defined by the first power supply voltage Vcc are output in synchronization with the first power supply voltage Vcc. Specific circuit configurations of the first charge pump circuit 51 and the second charge pump circuit 52 are illustrated in FIG. The charge pump 51A has a series circuit of diode-connected n-channel type diode-connected MOS transistors Mdd whose drains are coupled to the gate, and the coupled node of the diode-connected MOS transistors Mdd is a boost node NLU. The drain of the first stage diode-connected MOS transistor Mdd is connected to the first power supply voltage Vcc, and the well region in which each diode-connected MOS transistor Mdd is formed is connected to the circuit ground voltage Vss. One storage electrode of the pump capacitor Cp is coupled to each boosting node NLU. Pump drive clocks CLK1pd and / CLK1pd whose phases are sequentially inverted are supplied from the clock driver 51B to the other storage electrode of the pump capacitor Cp. The clock driver 51B includes a NOR gate NOR and an inverter INV. The NOR gate NOR takes the pump clock CLKp and the output of the pump control circuit 51C as two inputs. The pump control circuit 51C compares the reference voltage Vref generated by the reference voltage generation circuit (VREFG) 60 with the boosted voltage Vpp1 fed back by the comparator (CMP) 61, and converges the voltage level of the boosted voltage Vpp1 to the reference voltage Vref. Negative feedback control is performed. Although not shown in particular, the charge pump circuit 52 may be configured in the same manner as in FIG. When the reference voltage Vref is low, a value obtained by dividing the boost voltage Vpp1 by a resistor circuit or the like may be compared by a comparator. The smoothing capacitors 53 and 54 are capacitive elements for stabilizing the output voltage of the charge pump circuit.

  According to the memory power supply circuit 33 of FIG. 1, since the first charge pump circuit 51 generates the high voltage Vpp1 applied to the memory gate of the nonvolatile memory cell MC, the generation of ripple is suppressed rather than the current supply capability. Is required. Since the second charge pump circuit 52 generates the high voltage Vpp2 supplied to the drain of the non-volatile memory cell MC, it needs current supply capability. At this time, the second power supply voltage Vddm lower than the first power supply voltage Vcc is applied to the former first charge pump circuit 51 as the operating power supply of the clock driver 51B for driving the pump capacitor element Cp in phase. Ripple generation in the output voltage of the pump circuit 51A can be reduced compared to the case where the first power supply voltage Vcc is used. Since the generation of ripples can be reduced, the area SC1 of the smoothing capacitor 53 can be small. On the other hand, since the drive amplitude of the pump capacitor Cp by the pump drive clocks CLK1pd, / CLK1pd is reduced, the number of boosting stages necessary to obtain the required high voltage Vpp1 is increased. S1 increases. If the area decrease of the smoothing capacitor 53 exceeds the area increase of the pump capacitor Cp, the occupied area related to the first charge pump 51 can be reduced as a whole. Here, paying attention to the parasitic load to be driven by the high voltage Vpp1, the number of memory gates that can be driven by the first charge pump 51 is changed according to the size of the area to be erased, and is exemplified in FIG. As described above, there are large and small erase units, and when erasing is performed in a large unit such as the area ARE1 (for example, 16K to 256K bytes), the charge pump circuit 51 must drive a large parasitic load in a short time. Relatively large driving capacity is required. When erasing is performed in such a small unit (for example, 1K to 8K bytes) as in the area ARE2 using such a charge pump circuit 51, the driving capability becomes excessive and a relatively large ripple is generated. As described above, in a charge pump circuit used for driving both a large parasitic load and a small parasitic load, it is necessary to employ a particularly large stabilization capacitance particularly in a memory gate driving application that is not subject to voltage fluctuation. In this way, both the large memory array area where the parasitic load is large and the drive time is shortened (the voltage rise time is shortened) and the small memory array area where the parasitic load is small and the voltage fluctuation must be suppressed are driven. When a target is used, a large capacity is required for the smoothing capacitor, and therefore the effect of reducing the occupied area with respect to the first charge pump circuit 51 appears significantly in that the larger capacitor can be reduced. The driver 55a shown in FIG. 6 generically refers to the driver 55 for each memory gate line in each of the areas AER1 and AER2, and is different from the actual arrangement relationship.

  On the other hand, in the case of the second charge pump circuit 52, since the drain current must be supplied during the write operation, the current supply capability is more important than the suppression of the ripple. Therefore, the pump capacitance Cp is larger than the area SC2 of the smoothing capacitance 54. The total area S2 tends to be larger. At this time, since the first power supply voltage Vcc higher than the second power supply voltage Vddm is applied to the operating power supply of the clock driver 52B that performs phase inversion driving of the pump capacitance element Cp of the second charge pump circuit 52, the ripple is suppressed. Even if the effect is reduced, the number of series stages of the pump capacity Cp can be reduced. The area occupied by the second charge pump circuit 52 can be reduced in that the capacity value of the pump capacity Cp that tends to be relatively larger than the smoothing capacity 54 can be reduced. .

<< Start voltage of charge pump first stage in charge pump circuit >>
FIG. 7 shows another example of the memory power circuit 33 as another embodiment of the present invention. The figure illustrates a configuration that can generate a plurality of high voltages Vpp1 and Vnpp1 as high voltages to be applied to the memory gate line MGL. The charge pump circuit (CPMP1) 51 is used to generate the high voltage Vpp1. A charge pump circuit (CPMP3) 65 is used to generate the high voltage Vnpp1. As illustrated in FIG. 8, high voltages such as Vpp1, Vnpp1, etc. are defined with a relatively large voltage width for matching with the rewrite characteristics of the nonvolatile memory cell MC. When the first charge pump circuit 51 is used to generate the high voltage Vpp1 in the range of the variation upper limit voltage Vccmax of the first power supply voltage Vcc, the first power supply voltage Vcc is used as the start voltage of the charge pump circuit 51. do it. In order to generate the internal power supply voltage Vnpp1 in the range of the variation lower limit voltage Vddmmin of the second power supply voltage Vddm and the variation lower limit voltage Vccmin of the first power supply voltage Vcc, the second power supply voltage Vddm is charged. Used as a start voltage for the pump circuit 65. For example, a high voltage Vpp1 is applied to the memory gate for the non-volatile memory cell MC to be written, but at this time, the non-write high voltage is applied to the memory gate of the non-write non-volatile memory cell. In the case of adopting a control mode in which the voltage Vnpp1 is applied, the voltage Vnpp1 is applied as the high voltage of the write non-selection. As described above, the first power supply voltage Vcc is used as the start voltage of the first charge pump circuit 51 that generates a voltage higher than the first power supply voltage Vcc, and the level is higher than that of the first power supply voltage Vcc. The second power supply voltage Vddm is used as the start voltage of the charge pump circuit 65 that generates a low voltage. When the first power supply voltage Vcc is used as the start voltage of the charge pump circuit 65 to generate a voltage lower than the first power supply voltage, the output of the charge pump circuit 65 is output by a resistor 66 as illustrated in FIG. You may pull down. If the second power supply voltage Vddm is used as the start voltage of the charge pump circuit 65 that generates a voltage lower than the first power supply voltage Vcc as shown in FIG. It is further excellent in that the pump capacity Cp can be reduced because it is not necessary to compensate for the above.

  It goes without saying that the embodiment described with reference to FIGS. 7 to 9 can be combined with the embodiment described above.

<Combination of step-down circuit>
FIG. 10 shows still another example of the memory power supply circuit 33 as still another embodiment of the present invention. In the same figure, as a modification of FIG. 7, a configuration capable of generating a plurality of high voltages Vpp1 and Vnpp1 as high voltages applied to the memory gate lines is illustrated. The charge pump circuit (CPMP1) 51 is used to generate the high voltage Vpp1. A step-down circuit (LDS) 67 is used to generate the high voltage Vnpp1. As illustrated in FIG. 11, when the first charge pump circuit 51 is used to generate the high voltage Vpp1 in the range of the variation upper limit voltage Vccmax of the first power supply voltage Vcc, the first power supply voltage Vcc is The start voltage of the charge pump circuit 51 is the same as in FIG. The difference is that the internal power supply voltage Vnpp1 that is equal to or lower than the variation lower limit voltage Vddmmin of the second power supply voltage Vddm is generated. Step-down circuit 67 is used to generate internal power supply voltage Vnpp1. The step-down circuit 67 includes a clamp circuit that uses the second power supply voltage Vddm as an operating power supply. When a booster circuit is used instead of the step-down circuit 67, the capacitance for stabilizing the voltage phase is increased by the difference between the operation cycle in which the pump operation is performed and the non-operation cycle in which the pump operation is stopped. However, when the step-down circuit 67 is employed, the voltage phase stabilization capacitor 68 can be reduced.

<Stabilization of power supply for reference voltage generator>
FIG. 12 shows a modification of the charge pump circuit 51. The first power supply voltage Vcc is used as the start voltage for the charge pump 51A as described above. The first power supply voltage Vcc is also used as an operating power supply for the external input / output circuit (I / O) 6. The second power supply voltage Vddm is used as the power source of the clock driver 51B for the pump capacitance Cp of the charge pump 51A as described above. The reference voltage generation circuit 60 that generates the reference voltage Vref uses the second voltage Vddm as an operation power supply. The reference voltage Vref can be stabilized by using the second voltage Vddm which is more stable than the voltage Vcc used for driving the I / O 6. When a high voltage is applied when rewriting a nonvolatile memory cell, if the output voltage of the charge pump circuit fluctuates, an overvoltage is applied to the nonvolatile memory cell. As a result, the characteristics of the nonvolatile memory cell deteriorate and the rewriting is performed. This will cause problems such as a decrease in the number of possible times. By using the power supply voltage Vddm having the smaller noise as the operation power supply of the reference power supply generation circuit 60 that determines the boosted line pressure level, it is possible to suppress application of an overvoltage to the nonvolatile memory cell.

  Needless to say, the embodiment described with reference to FIGS. 10 to 12 can be combined with the embodiment described above.

  As described above, the first power supply voltage Vcc, the second power supply voltage Vddm, and the third power supply voltage Vddc having different levels in the microcomputer 1 (first power supply voltage Vcc> second power supply voltage Vddm> first). In the memory power supply circuit 33 that generates a high voltage for changing the threshold voltage of the flash memory 4 when the three power supply voltage Vddc) is available, the charge pump circuit 51 that needs to suppress the ripple of the output voltage is used as a pump. The drive driver of the pump capacitor Cp is used for the charge pump circuit 52 that uses the relatively low power supply voltage Vddm as the driver of the capacitor Cp to reduce the area SC1 of the smoothing capacitor 53 and requires a current supply capability rather than ripple suppression. As a result, the power supply voltage Vcc having a relatively high level is used to reduce the pump capacity area S2. Further, the first power supply voltage Vcc is used as the start voltage of the charge pump circuit 51 that generates the voltage Vpp1 having a level higher than the first power supply voltage Vcc. In the memory power supply circuit 33, the stabilization capacity and the pump capacity of the charge pump circuit are reduced as a whole by appropriately assigning the operation power supply to the charge pump circuit or the like according to the use of the boosted voltage. be able to.

  Since second high voltage Vpp2 is less susceptible to fluctuations in first power supply voltage Vcc, a stable first high voltage is applied to the memory gate. In addition, since the second high voltage is generated in response to the supply of the first power supply voltage supplied from the outside, it is easy to supply the charge to the source or drain.

  Since the first charge pump circuit 51 is supplied with the second power supply voltage Vddm and outputs a voltage, the number of memory cell gates driven by the output voltage of the first charge pump circuit is changed. Since the ripple is hardly generated, the area of the smoothing capacitive element can be suppressed.

  Since the third power supply voltage Vddc is generated independently of the first voltage Vpp1 and the second high voltage Vpp2, the central processing unit can be operated without being affected by fluctuations in the high voltage.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the power supply voltage Vddm is not limited to the internal voltage step-down, and may be directly input from the external power supply terminal of the microcomputer. The specific level of the power supply voltage is not limited to the above description and can be changed as appropriate. The electrically rewritable nonvolatile memory cell is not limited to a stack gate structure having a floating gate. A split gate structure including a selection MOS transistor portion or a structure including a charge trap film such as a silicon nitride film may be used. The configuration of the memory array may be any configuration such as AND, NAND, NOR, and the present invention is not limited to the structure of the memory array. The electrically rewritable nonvolatile memory is not limited to the flash memory, and may be an EEPROM or the like. The semiconductor device according to the present invention is not limited to a microcomputer, and is rewritable electrically by a central processing unit as represented by a communication controller, an image processing controller, an encryption / decryption controller, and the like. The present invention can be widely applied to various semiconductor devices under conditions provided with a nonvolatile memory.

It is a circuit diagram which illustrates the memory power supply circuit which a microcomputer has. It is a block diagram which shows an example of a microcomputer. It is a block diagram which shows an example of flash memory. It is a block diagram which illustrates the power supply circuit of a microcomputer. It is a circuit diagram which shows the specific example of a charge pump circuit. It is explanatory drawing which illustrates the state from which the drive load by the high voltage Vpp1 differs with the magnitude | size of an erasing unit. It is explanatory drawing which shows another example of a memory power supply circuit. It is explanatory drawing which illustrates the electric potential relationship of the high voltage boosted and the multiple power supply voltage used for a pressure | voltage rise. It is a conceptual diagram when producing | generating a voltage lower than a start voltage using a charge pump circuit. FIG. 8 is an explanatory diagram showing a memory power supply circuit according to a modified example of FIG. 7. It is explanatory drawing which shows another example of the electric potential relationship of the high voltage boosted and the multiple power supply voltage used for a pressure | voltage rise. It is explanatory drawing which shows the modification of a charge pump circuit.

Explanation of symbols

1 Microcomputer (MCU)
2 Central processing unit (CPU)
3 RAM
4 Flash memory (FLASH)
5 Bus state controller (BSC)
6 External input / output circuit (I / O)
7 Clock generator (CPG)
7A PLL circuit 8 Power supply circuit (PSUP) 8
9 System controller (SYSC)
10 Internal bus Vcc 1st power supply voltage Vddm 2nd power supply voltage Vddc 3rd power supply voltage 21 Memory array (MARY)
MGL Memory gate line BL Bit line SL Source line 33 Memory power supply circuit (MPS)
34 Control circuit (CONT)
40, 41 Step-down circuit 51 First charge pump circuit (CPMP1)
52 Second charge pump circuit (CPMP2)
53 Smoothing capacity 55 Driver 55
54 Smoothing capacity 56 Driver Vpp1, Vpp2 High voltage 51A Charge pump (PUMP)
51B Clock driver 51B
51C Pump control circuit (PCNT)
CLKp Pump lock CLK1pd, / CLK1pd Pump drive clock NLU Boost node Cp Pump capacity 60 Reference voltage generation circuit (VREFG)
Vvref reference voltage 61 Comparator (CMP)
65 Third charge pump circuit (CPMP3)
67 Step-down circuit

Claims (18)

Nonvolatile memory cells having a source and a drain constituting a transistor, and a charge storage region and a memory gate, which are stacked on and insulated from each other via an insulating film on a channel formation region between them, are arranged in an array. A non-volatile memory cell array;
A first high voltage higher than the first power supply voltage is generated by receiving a second power supply voltage obtained by stepping down the first power supply voltage supplied from the outside of the semiconductor device, and the memory gate of the nonvolatile memory cell A first charge pump circuit capable of supplying the first high voltage;
A second high voltage that is higher than the first power supply voltage in response to the supply of the first power supply voltage and that can supply the second high voltage to the source or drain of the nonvolatile memory cell. And a charge pump. The output of the first charge pump circuit has a smoothing capacitive element that stabilizes the output voltage of the first charge pump circuit,
The number of memory cell gates driven by the output voltage of the first charge pump circuit can be changed when changing the threshold voltage of the nonvolatile memory cell in the nonvolatile memory array. Semiconductor device. A central processing unit for controlling the nonvolatile memory;
The third power supply voltage, which is lower than the second power supply voltage and is obtained by stepping down the first power supply voltage, is generated independently of the first high voltage and the second high voltage,
The semiconductor device according to claim 1, wherein the third power supply voltage is supplied to the central processing unit.   4. The semiconductor device according to claim 3, wherein the change of the threshold voltage for the nonvolatile memory cell is an erase operation for lowering the threshold voltage and a write operation for increasing the threshold voltage.   5. The semiconductor device according to claim 4, wherein the first charge pump circuit forms a voltage used for a data write operation to the memory cell.   6. The semiconductor device according to claim 5, wherein the second charge pump circuit forms a voltage to be applied to the drain or the source in order to generate hot electrons in the data write operation to the memory cell.   5. The semiconductor device according to claim 4, wherein the first charge pump circuit forms a voltage used for an erase operation of data in the memory cell. A third charge pump circuit that generates a voltage on the low potential side that is supplied to the memory gate of the nonvolatile memory cell lower than the voltage generated by the first charge pump circuit when the change of the threshold voltage is not selected. Further comprising
The third charge pump circuit uses the pump capacitor element as the second power supply voltage as a start voltage that starts boosting;
4. The semiconductor device according to claim 3, wherein the first charge pump circuit uses a start voltage started to be boosted by using a pump capacitance element as the first power supply voltage. 5. And a step-down circuit for generating a low-potential-side voltage to be supplied to the memory gate of the nonvolatile memory cell, which is lower than the voltage generated by the first charge pump circuit when the threshold voltage change is not selected. ,
The step-down circuit includes a clamp circuit that uses the second power supply voltage as an operation power supply,
4. The semiconductor device according to claim 3, wherein the first charge pump circuit uses a start voltage started to be boosted by using a pump capacitance element as the first power supply voltage. 5. An external interface circuit using the first power supply voltage as an operation power supply;
The charge pump circuit inputs a comparison result by comparing the boosted voltage with a reference voltage, and a driving clock signal for sequentially phase-inverting the capacitive elements when the boosted voltage is equal to or lower than the reference voltage. A gate circuit for stopping the supply of the drive clock signal in a state where the boosted voltage exceeds a reference voltage;
10. The semiconductor device according to claim 3, wherein the reference voltage generation circuit for generating the reference voltage uses the second power supply voltage as an operation power supply.   An external interface circuit using the first power supply voltage as an operation power supply, and a PLL circuit using the second power supply voltage as an operation power supply, wherein the central processing unit operates in synchronization with a clock signal generated by the PLL circuit, The semiconductor device according to claim 3, wherein the third power supply voltage is used as an operation power supply.   An external power supply terminal that receives the first power supply voltage, a step-down circuit that generates the second power supply voltage from the first power supply voltage, and a step-down circuit that generates the third power supply voltage from the second power supply voltage. Item 12. A semiconductor device according to Item 11.   13. The semiconductor device according to claim 12, further comprising: an external power supply terminal that receives the first power supply voltage; an external power supply terminal that receives the third power supply voltage; and a step-down circuit that generates the second power supply voltage from the first power supply voltage. . A non-volatile memory having a large number of non-volatile memory cells whose threshold voltage can be changed by applying a high voltage higher than a first power supply voltage supplied from the outside of the semiconductor device, and a memory power supply circuit for generating the high voltage And a central processing unit that controls the nonvolatile memory, and a semiconductor that uses a second power supply voltage lower than the first power supply voltage and a third power supply voltage lower than the second power supply voltage as an operation power supply inside the device. In the device
The memory power supply circuit includes: a first charge pump circuit that generates a voltage to be supplied to a gate electrode of the nonvolatile memory cell when the threshold voltage of the nonvolatile memory cell is changed; and a source of the nonvolatile memory cell Or a second charge pump circuit that generates a voltage to be supplied to the drain,
The first charge pump circuit uses a drive clock having an amplitude of the second power supply voltage to drive a pump capacitor coupled to a boost node,
The second charge pump circuit uses a drive clock having an amplitude of the first power supply voltage to drive a pump capacitor coupled to a boost node,
Each of the first and second charge pump circuits is a semiconductor device provided with a smoothing capacitive element at its voltage output node. The memory power supply circuit generates a voltage on a low potential side to be supplied to the memory gate of the nonvolatile memory cell, which is lower than a voltage generated by the first charge pump circuit when the change of the threshold voltage is not selected. A third charge pump circuit;
The third charge pump circuit uses the pump capacitor element as the second power supply voltage as a start voltage that starts boosting;
15. The semiconductor device according to claim 14, wherein the first charge pump circuit uses a start voltage started to be boosted by using a pump capacitance element as the first power supply voltage. The memory power supply circuit generates a voltage on a low potential side to be supplied to the memory gate of the nonvolatile memory cell, which is lower than a voltage generated by the first charge pump circuit when the change of the threshold voltage is not selected. A further step-down circuit;
The step-down circuit includes a clamp circuit that uses the second power supply voltage as an operation power supply,
15. The semiconductor device according to claim 14, wherein the first charge pump circuit uses a start voltage started to be boosted by using a pump capacitance element as the first power supply voltage. An external interface circuit using the first power supply voltage as an operation power supply;
The charge pump circuit inputs a comparison result by comparing the boosted voltage with a reference voltage, and a driving clock signal for sequentially phase-inverting the capacitive elements when the boosted voltage is equal to or lower than the reference voltage. A gate circuit for stopping the supply of the drive clock signal in a state where the boosted voltage exceeds a reference voltage;
17. The semiconductor device according to claim 15, wherein the reference voltage generation circuit that generates the reference voltage uses the second power supply voltage as an operation power supply. A non-volatile memory having a large number of non-volatile memory cells that are electrically rewritable, and a central processing unit that controls the non-volatile memory, the first power supply voltage supplied from the outside, the first power supply voltage In a semiconductor integrated circuit using a second power supply voltage lower than the second power supply voltage and a third power supply voltage lower than the second power supply voltage as an operation power supply,
The non-volatile memory has a first charge pump circuit that generates a voltage applied to the gate electrode of the non-volatile memory cell and a second voltage that generates a voltage applied to the source or drain of the non-volatile memory cell when rewriting. And a charge pump circuit of
The first charge pump circuit includes a plurality of pump capacitors that are sequentially phase-inverted and driven using a drive clock having an amplitude of the second power supply voltage,
The second charge pump circuit has a plurality of pump capacitors that are sequentially phase-inverted using a drive clock having an amplitude of the first power supply voltage,
Each of the first and second charge pump circuits is a semiconductor device provided with a smoothing capacitive element at its voltage output node.

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