CN113824315B - Power supply generating circuit and display device - Google Patents

Power supply generating circuit and display device Download PDF

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Publication number
CN113824315B
CN113824315B CN202111223152.4A CN202111223152A CN113824315B CN 113824315 B CN113824315 B CN 113824315B CN 202111223152 A CN202111223152 A CN 202111223152A CN 113824315 B CN113824315 B CN 113824315B
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China
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circuit
voltage
sub
transistor
charge pump
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CN113824315A (en
Inventor
李�杰
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Nanjing Boe Display Technology Co ltd
BOE Technology Group Co Ltd
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Nanjing Boe Display Technology Co ltd
BOE Technology Group Co Ltd
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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Abstract

The invention discloses a power supply generating circuit and a display device, wherein the power supply generating circuit comprises: a boost sub-circuit and a charge pump sub-circuit; the input end of the boosting sub-circuit is connected with a direct current power supply, the output end of the boosting sub-circuit is connected with the input end of the charge pump sub-circuit so as to boost the initial voltage provided by the direct current power supply into an intermediate voltage, and the intermediate voltage is provided for the charge pump sub-circuit; the output end of the charge pump sub-circuit is connected with a power supply circuit to be powered, so that after the intermediate voltage is boosted by integer times, working voltage is output from the output end to the power supply circuit to be powered. The invention provides a power supply generating circuit with higher power supply efficiency and a display device.

Description

Power supply generating circuit and display device
Technical Field
The present invention relates to the field of display technologies, and in particular, to a power supply generating circuit, a display panel, and a display device.
Background
With the development of display technology, the requirement of high resolution and high brushing becomes the main stream requirement of the display panel, and the requirement of low power consumption of the display panel is more strict.
The efficiency of the current power generation schemes is around 70%, and such inefficient power generation schemes have gradually failed to meet the low power consumption requirements of the display panel.
As can be seen, there is a great need for a more efficient power generation scheme.
Disclosure of Invention
The present invention has been made in view of the above problems, and has as its object to provide a power supply generating circuit, a display panel and a display device which overcome or at least partially solve the above problems.
In a first aspect, there is provided a power supply generating circuit comprising:
a boost sub-circuit and a charge pump sub-circuit;
the input end of the boosting sub-circuit is connected with a direct current power supply, the output end of the boosting sub-circuit is connected with the input end of the charge pump sub-circuit so as to boost the initial voltage provided by the direct current power supply into an intermediate voltage, and the intermediate voltage is provided for the charge pump sub-circuit;
the output end of the charge pump sub-circuit is connected with a power supply circuit to be powered, so that after the intermediate voltage is boosted by integer times, working voltage is output from the output end to the power supply circuit to be powered.
Optionally, the boost sub-circuit includes: the boost control circuit comprises a boost control circuit, a first inductor, a first transistor and a second transistor; the first transistor and the second transistor are connected in series between the output end of the boosting sub-circuit and the ground end; one end of the first inductor is connected with the direct current power supply, and the other end of the first inductor is connected with a series connection node of the first transistor and the second transistor; the boost control circuit is connected with the grid electrodes of the first transistor and the second transistor, and controls the charge and discharge of the first inductor through controlling the switch of the transistor so as to boost the initial voltage.
Optionally, the charge pump sub-circuit includes a first reference terminal, and the output terminal of the charge pump sub-circuit includes a first output terminal; the first working voltage output by the first output end is the sum of a first reference voltage and a first boosted voltage, the first reference voltage is the voltage received by the first reference end, and the first boosted voltage is the voltage obtained by boosting the intermediate voltage by integer times by the charge pump sub-circuit.
Optionally, the charge pump sub-circuit includes: the charge pump control circuit and N groups of positive coupling capacitance circuits, wherein N is a positive integer; each set of the positive coupling capacitance circuits includes: a positive coupling capacitor and two MOS transistors; the two MOS tubes are connected in series; one end of the positive coupling capacitor is connected with the output end of the boosting sub-circuit, and the other end of the positive coupling capacitor is connected with a series connection node of the two MOS tubes; the N groups of positive coupling capacitance circuits are connected in series between the first output end and the first reference end in a serial manner that MOS tubes in the two groups of positive coupling capacitance circuits are connected in series; the charge pump control circuit is connected with the grid electrode of each MOS tube in the N groups of positive coupling capacitance circuits so as to control the intermediate voltage to be boosted by N times.
Optionally, the charge pump sub-circuit further includes a second reference terminal, and the output terminal of the charge pump sub-circuit further includes a second output terminal; the second working voltage output by the second output end is a check value of subtracting a second boosted voltage from a second reference voltage, the second reference voltage is a voltage received by the second reference end, and the second boosted voltage is a voltage obtained by boosting the intermediate voltage by integer multiples of the charge pump sub-circuit.
Optionally, the charge pump sub-circuit further includes: m groups of negative coupling capacitance circuits, M being a positive integer; each set of the negative coupling capacitance circuits includes: a negative coupling capacitor and two MOS tubes; the two MOS tubes are connected in series; one end of the negative coupling capacitor is connected with the output end of the boosting sub-circuit, and the other end of the negative coupling capacitor is connected with a series connection node of the two MOS tubes; the M groups of negative coupling capacitance circuits are connected in series between the second output end and the second reference end in a serial manner that MOS tubes in the two groups of negative coupling capacitance circuits are connected in series; and the charge pump control circuit is connected with the grid electrode of each MOS tube in the M groups of positive coupling capacitance circuits so as to control the medium voltage to be boosted by M times.
Optionally, the circuit further comprises: the input end of the voltage reducing sub-circuit is connected with a direct current power supply, and the output end of the voltage reducing sub-circuit is connected with the first reference end so as to reduce the initial voltage provided by the direct current power supply to the first reference voltage and provide the first reference voltage to the charge pump circuit.
Optionally, the step-down sub-circuit includes: the step-down control circuit, the second inductor, the third transistor and the fourth transistor; the third transistor and the fourth transistor are connected in series between a direct current power supply and a ground terminal; one end of the second inductor is connected with the output end of the voltage dropping sub-circuit, and the other end of the second inductor is connected with a series connection node of the third transistor and the fourth transistor; the step-down control circuit is connected with the gates of the third transistor and the fourth transistor, and controls the charge and discharge of the second inductor by controlling the switch of the transistor so as to step down the initial voltage.
Optionally, the first reference terminal is connected to any one of the following: the output end of the step-down sub-circuit, the output end of the step-up sub-circuit and the ground end.
Optionally, a voltage stabilizing capacitor is disposed between the output end of the boost sub-circuit and the ground end, and between the output end of the charge pump sub-circuit and the ground end.
In a second aspect, a display device is provided, including the power supply generating circuit of the first aspect.
The technical scheme provided by the embodiment of the invention has at least the following technical effects or advantages:
according to the power generation circuit and the display device provided by the embodiment of the invention, the boosting sub-circuit and the charge pump sub-circuit are arranged in cascade connection to improve the power generation efficiency. Specifically, the input end of the voltage boosting sub-circuit is connected with a direct current power supply, and the output end of the voltage boosting sub-circuit is connected with the input end of the charge pump sub-circuit so as to boost the initial voltage provided by the direct current power supply into an intermediate voltage. Because the smaller the boosting amplitude of the boosting circuit is, the higher the corresponding power conversion efficiency is, the boosting module is firstly adopted to convert the direct current voltage into the intermediate voltage, and the efficiency can be ensured because the direct boosting is not required to be greatly and directly boosted into the working voltage. And then a charge pump is adopted to provide working voltage for a circuit needing power supply after the intermediate voltage is boosted by an integer. Because the charge pump has highest efficiency when boosting in integer multiples, different working voltage demands can be met through the arrangement of the intermediate voltage, and the efficiency can be further improved through boosting in integer multiples.
The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the teachings of the present invention in order that the same may be more clearly understood and to make the same and other objects, features and advantages of the present invention more readily apparent.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:
FIG. 1 is a block diagram of a power generation circuit in an embodiment of the invention;
FIG. 2 is a schematic diagram of N groups of positive coupling capacitor circuits according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of M groups of negative coupling capacitor circuits according to an embodiment of the invention;
fig. 4 is a schematic diagram of a second embodiment of the invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The invention provides a power generation circuit, please refer to fig. 1, which is a block diagram of a power generation circuit 01 in an embodiment of the invention, comprising:
a boost sub-circuit 10 and a charge pump sub-circuit 20;
the input end of the boosting sub-circuit 10 is connected with a direct current power supply DC, the output end of the boosting sub-circuit 10 is connected with the input end of the charge pump sub-circuit 20 so as to boost the initial voltage provided by the direct current power supply DC into an intermediate voltage, and the intermediate voltage is provided to the charge pump sub-circuit 20;
the output terminal of the charge pump sub-circuit 20 is connected to a power supply circuit to boost the intermediate voltage by an integer multiple, and then outputs an operating voltage from the output terminal to the power supply circuit.
It should be noted that the power supply generating circuit provided in the present application may be used for power supply of a display panel of a type such as a liquid crystal display (Liquid Crystal Display, LCD), an Organic Light-Emitting Diode (OLED), or an Organic Light-Emitting Diode (LED), and may also be used for power supply of a device having a low power consumption requirement such as a flat panel detector, a photodetector, etc., which are not listed herein, but are not limited thereto. The direct current power supply DC may be in the power supply generation circuit or may be an external power supply, and is not limited in this regard.
When the power supply generating circuit provided by the application is used for supplying power to the display panel, the corresponding power supply circuit can be a driving array circuit on the display panel array substrate, and the provided working voltage can be a gate driving voltage serving as the driving array circuit.
The specific circuit configuration and operation principle of the power supply generating circuit are further described below.
First, the boost sub-circuit 10 is described, and as shown in fig. 1, the boost sub-circuit 10 may include a boost control circuit 11, a first inductance L1, a first transistor M1, and a second transistor M2.
The first transistor M1 and the second transistor M2 are connected in series between the output terminal of the boost sub-circuit 10 and the ground terminal GND. The specific series connection mode is as follows: the first transistor M1 is commonly drain-connected to the second transistor M2, the source of the first transistor M1 is connected to the output terminal, and the source of the second transistor M2 is connected to the ground terminal GND. Of course, the source and drain of each transistor may be alternately connected, and the present invention is not limited thereto.
One end of the first inductor L1 is connected to the direct current power supply DC, and the other end is connected to a series connection point of the first transistor M1 and the second transistor M2, wherein the series connection point is the drains of the first transistor M1 and the second transistor M2.
The boost control circuit 11 is connected to the gates of the first transistor M1 and the second transistor M2, and controls the charge and discharge of the first inductor L1 by controlling the switching of the transistors to boost the initial voltage supplied from the direct current power supply DC. The boost control circuit 11 may be a pulse width modulation circuit or a processor, and is not limited thereto.
Taking this boost control circuit 11 as an example of a pulse width modulation circuit, the boost control circuit 11 includes: the power supply end of the external direct current power supply is connected with the input end for receiving the time sequence signals, and the external direct current power supply further comprises two output ends which are respectively connected with the grid electrodes of the first transistor M1 and the second transistor M2, and after the time sequence signals are subjected to pulse width modulation, control signals are output from the output ends to control the on and off of the first transistor M1 and the second transistor M2. The step of boosting the boost sub-circuit 10 is to set the boost control circuit 11 to control the second transistor M2 to be turned on first and synchronously control the first transistor M1 to be turned off, so that the direct current power supply DC is turned on through the path from the first inductor L1 to the ground GND, and the charging of the first inductor L1 is started. After charging, the boost control circuit 11 controls the first transistor M1 to be turned on, and synchronously controls the second transistor M2 to be turned off, so that the direct current power supply DC is turned on through a path from the first inductor L1 to the output end, and the direct current power supply DC and the first inductor L1 charge the charge pump sub-circuit 20 connected to the rear end of the output end at the same time, thereby realizing boost.
The intermediate voltage output after boosting by the boosting sub-circuit 10 is:wherein Vx is an intermediate voltage, dx is a duty ratio of the second transistor M2, and Vdc is an output voltage of the direct current power supply DC. The value of Dx can be adjusted by selecting the parameter setting the second transistor M2, thereby adjusting the value of the intermediate voltage Vx output by the boost sub-circuit 10.
Of course, the booster sub-circuit 10 is not limited to the above-described circuit configuration, and a booster function may be realized by using a conventional booster circuit Boost. The first transistor M1 and the second transistor M2 in the booster sub-circuit 10 may be a transistor, a thyristor, or the like, and are not limited herein.
Specifically, since the smaller the step-up width of the step-up circuit is, the higher the corresponding power conversion efficiency is, if the step-up sub-circuit 10 is directly used to step up the operating voltage, the step-up efficiency is often about 70%, and power consumption is often caused. According to the voltage boosting sub-circuit 10, the intermediate voltage with smaller voltage value is obtained, and according to detection, the voltage boosting efficiency of the voltage boosting sub-circuit 10 can reach more than 93%, so that the efficiency is greatly improved.
Next, the charge pump sub-circuit 20 is described, and as shown in fig. 1, an input terminal of the charge pump sub-circuit 20 receives the intermediate voltage Vx supplied from the voltage boosting sub-circuit 10, and an operating voltage is obtained after boosting Vx by an integer multiple. The operating voltage may be equal to the voltage obtained by boosting Vx by an integer multiple, or may be equal to the voltage obtained by adjusting the voltage obtained by boosting Vx by an integer multiple using the reference voltage.
Specifically, the charge pump sub-circuit 20 may be arranged to comprise a first reference terminal 21, and the output terminal of the charge pump sub-circuit 20 comprises a first output terminal 22. The voltage received by the first reference terminal 21 is a first reference voltage, and the voltage obtained by boosting the intermediate voltage Vx by an integer multiple of the charge pump sub-circuit 20 is a first boosted voltage. The first operating voltage output by the first output terminal 22 is the sum of the first reference voltage and the first boost voltage.
The first reference terminal 21 may be connected to the output terminal of the boost sub-circuit 10, i.e. with the intermediate voltage Vx as the first reference voltage. The first reference terminal 21 may also be connected to the ground GND, i.e. the first reference voltage is 0V. The first reference terminal 21 may also be connected to the remaining set voltage supply terminals, for example, the output terminal of the step-down sub-circuit 30 shown in fig. 1, the first reference voltage being set by the step-down sub-circuit 30. By setting the first reference terminal 21, the first reference voltage received by the first reference terminal 21 can be set or adjusted as required, so that the obtained working voltage can have more selectable values, and the application scene of the power supply generating circuit is enriched.
In an alternative embodiment, as shown in fig. 2, the charge pump sub-circuit 20 may include: a charge pump control circuit 23 and N groups of positive coupling capacitance circuits 24, N being a positive integer.
The N groups of positive coupling capacitor circuits 24 are connected in series between the first output end 22 and the first reference end 21 in a manner of connecting the MOS transistors in the two groups of positive coupling capacitor circuits in series. Each set of positive coupling capacitance circuits 24 includes: a positive coupling capacitor 241 and two MOS transistors connected in series. The specific series connection mode is as follows: in each set of positive-coupling capacitor circuits 24, the drain electrode of one MOS transistor is connected to the high-voltage end (the high-voltage end may be the first output end 22, or a previous stage of positive-coupling capacitor circuit connected closer to the first output end 22), and the source electrode is connected to the drain electrode of another MOS transistor. The source of the other MOS transistor is connected to a low voltage terminal (the low voltage terminal may be the first reference terminal 21, or a positive coupling capacitor circuit of a subsequent stage connected closer to the first reference terminal 21). Of course, the source and drain of each MOS transistor may be alternatively connected, which is not limited herein.
One end of the positive coupling capacitor 241 is connected to the output end of the boost sub-circuit 10, and the other end is connected to the series connection node of the two MOS transistors. The series connection node of the two MOS tubes is the source-drain connection node of the two MOS tubes.
The charge pump control circuit 23 is connected to the gates of the MOS transistors in the N groups of positive-coupling capacitor circuits 24, so as to control the intermediate voltage Vx to be boosted N times by controlling the voltage of the gates.
For example, as shown in fig. 1 and 2, N is equal to 2 in fig. 2, i.e., 2 sets of positive coupling capacitance circuits 24 are connected in series. The positive coupling capacitors 241 (i.e., CH1 and CH 2) in each set of positive coupling capacitor circuits 24 are connected to the output of the boost sub-circuit 10 to receive the intermediate voltage Vx. The series connected 2 groups of positive coupling capacitor circuits 24 are connected between the first output terminal 22 and the first reference terminal 21. When N is equal to 1, 3 or 4, the connection is made in series as shown in fig. 2.
In the implementation process, the two MOS transistors in fig. 2 may also use devices such as diodes, which are not limited herein. Specifically, the use of the MOS transistor in the positive coupling capacitor circuit 24 can effectively eliminate the consumption of conversion efficiency caused by voltage drop on two sides of the device when the diode and other devices are used, further improve the efficiency, and the highest conversion efficiency can reach about 98% when the MOS transistor is used.
The charge pump sub-circuit 20 outputs a first operating voltage vgh=n×vx+vbase-h after boosting by the N groups of positive coupling capacitor circuits 24. Wherein VGH is a first working voltage; n is the positive voltage coefficient of the charge pump sub-circuit 20, i.e., the number of groups of the positive coupling capacitance circuits 24, and N is the number of the configured positive coupling capacitances 241; vbase-h is the first reference voltage.
Of course, the Charge Pump sub-circuit 20 is not limited to the above-described circuit configuration, and a conventional Charge Pump circuit Charge Pump may be used to realize the boosting function. The MOS transistors in the charge pump sub-circuit 20 may be transistors, diodes, or the like, and are not limited herein.
Specifically, because the efficiency is highest when the charge pump circuit carries out integral multiple boosting, and the efficiency of non-integral multiple boosting is lower, the output working voltage value is regulated through the intermediate voltage obtained by the boosting sub-circuit 10, so that the boosting efficiency of the charge pump sub-circuit 20 can reach more than 94%, different working voltage requirements can be met, and the efficiency is greatly improved.
In an alternative embodiment, two output terminals are required when the power generating circuit 01 is used to supply an operating voltage to a power requiring circuit requiring two operating voltages. For example, as shown in fig. 1, when power is supplied to a driving array circuit on an array substrate, it is necessary to supply a first operating voltage VGH as an on voltage and also to supply a second operating voltage VGL as an off voltage.
Specifically, the charge pump sub-circuit 20 may be arranged to include a second reference terminal 25 in addition to the first reference terminal 21, and the output terminal of the charge pump sub-circuit 20 may include a second output terminal 26 in addition to the first output terminal 22. The voltage received by the second reference terminal 25 is a second reference voltage, and the voltage obtained by boosting the intermediate voltage Vx by an integer multiple of the charge pump sub-circuit 20 is a second boosted voltage. The second operating voltage output by the second output terminal 26 is the difference of the second reference voltage minus the second boost voltage.
The second reference terminal 25 may be connected to the ground terminal GND, i.e. the second reference voltage is 0V. The second reference terminal 25 may also be connected to a voltage supply terminal of the rest of the arrangement, for example, an output terminal of the step-down sub-circuit 30 shown in fig. 1, the second reference voltage being set by the step-down sub-circuit 30. By setting the second reference terminal 25, the second reference voltage received by the second reference terminal 25 can be set or adjusted as required, so that the obtained working voltage can have more selectable values, and the applicable scene of the power supply generating circuit is enriched.
In an alternative embodiment, as shown in fig. 3, the charge pump sub-circuit 20 may further include, in addition to the charge pump control circuit 23 and N sets of positive coupling capacitor circuits 24: m groups of negative coupling capacitance circuits 27, M being a positive integer.
The M groups of negative coupling capacitor circuits 27 are connected in series between the second output end 26 and the second reference end 25 in a manner that MOS transistors in the two groups of negative coupling capacitor circuits 27 are connected in series. Each set of negative coupling capacitance circuits 27 includes: a negative coupling capacitor 271 and two MOS transistors connected in series. The specific series connection mode is as follows: in each set of negative coupling capacitor circuits 27, the drain of one MOS transistor is connected to the high voltage terminal (the high voltage terminal may be the second reference terminal 25, or a previous stage of negative coupling capacitor circuit connected closer to the second reference terminal 25), and the source is connected to the drain of another MOS transistor. The source of the other MOS transistor is connected to a low voltage terminal (the low voltage terminal may be the second output terminal 26, or a negative coupling capacitor circuit of a subsequent stage connected closer to the second output terminal 26). Of course, the source and drain of each MOS transistor may be alternatively connected, which is not limited herein.
One end of the negative coupling capacitor 271 is connected to the output end of the boost sub-circuit 10, and the other end is connected to the series connection node of the two MOS transistors. The series connection node of the two MOS tubes is the source-drain connection node of the two MOS tubes.
The charge pump control circuit 23 is connected to the gates of the MOS transistors in the M groups of positive-coupling capacitor circuits 27, so as to control the voltage of the gates to boost the intermediate voltage Vx by M times.
For example, as shown in fig. 1 and 3, M is equal to 1, i.e., includes 1 set of negative coupling capacitance circuits 27. The negative coupling capacitances 271 (i.e., CL) in each set of negative coupling capacitance circuits 27 are connected to the output terminal of the booster sub-circuit 10, receiving the intermediate voltage Vx. A negative coupling capacitance circuit 27 is connected between the second output terminal 26 and the second reference terminal 25. When M is equal to 2 or 4, please refer to the serial connection when m=3 shown in fig. 4.
In the implementation process, the two MOS transistors in fig. 3 may also use devices such as diodes, which are not limited herein. Specifically, the use of the MOS transistor in the negative coupling capacitor circuit 27 can effectively eliminate the consumption of the conversion efficiency caused by the voltage drop on both sides of the device when the diode and other devices are used, further improve the efficiency, and the highest conversion efficiency can reach about 98% when the MOS transistor is used.
The charge pump sub-circuit 20 outputs a first operating voltage vgl=vbase-l-M Vx after boosting by the M groups of negative coupling capacitance circuits 27. Wherein VGL is the second working voltage; m is the negative pressure coefficient of the charge pump sub-circuit 20, i.e. the number of groups of negative coupling capacitance circuits 27, and M is the number of negative coupling capacitances 271 configured; vbase-l is the second reference voltage.
Of course, the Charge Pump sub-circuit 20 is not limited to the above-described circuit configuration, and a function of supplying two operating voltages may be implemented by using a conventional Charge Pump circuit Charge Pump. The MOS transistors in the charge pump sub-circuit 20 may be transistors, diodes, or the like, and are not limited herein.
Specifically, because the efficiency is highest when the charge pump circuit carries out integral multiple boosting, and the efficiency of non-integral multiple boosting is lower, the output two working voltage values are regulated through the intermediate voltage obtained by the boosting sub-circuit 10, so that the boosting efficiency of the charge pump sub-circuit 20 can reach more than 94%, the two groups of different working voltage requirements can be met, and the efficiency is greatly improved.
Next, a step-down sub-circuit 30 for providing the first reference voltage and/or the second reference voltage is described. As shown in fig. 1, an input terminal of the step-down sub-circuit 30 is connected to a direct current power supply DC, and an output terminal of the step-down sub-circuit 30 is connected to a reference terminal (including the first reference terminal 21 and/or the second reference terminal 25) of the charge pump sub-circuit 20 to step down an initial voltage provided by the direct current power supply DC to a reference voltage Vb (including the first reference voltage and/or the second reference voltage) and provide the reference voltage to the charge pump circuit 20.
The step-down sub-circuit 30 may include: the step-down control circuit 31, the second inductance L2, the third transistor M3, and the fourth transistor M4.
The third transistor M3 and the fourth transistor M4 are connected in series between the direct current power supply DC and the ground GND. The specific series connection mode is as follows: the source of the third transistor M3 is connected to the drain of the fourth transistor M4, the drain of the third transistor M3 is connected to the DC power source DC, and the source of the fourth transistor M4 is connected to the ground GND. Of course, the source and drain of each transistor may be alternately connected, and the present invention is not limited thereto.
One end of the second inductor L2 is connected to the output terminal of the voltage-reducing sub-circuit 30, and the other end is connected to the series connection node of the third transistor M3 and the fourth transistor M4.
The step-down control circuit 31 is connected to the gates of the third transistor M3 and the fourth transistor M4, and controls the charge and discharge of the second inductor L2 by controlling the switching of the transistors to provide an initial voltage step-down to the direct current power supply DC. The step-down control circuit 31 may be a pulse width modulation circuit or a processor, and is not limited thereto.
The step of step-down of the step-down sub-circuit 30 is to set the step-down control circuit 31 to control the third transistor M3 to be turned on first and to synchronously control the fourth transistor M4 to be turned off, so that the direct current power supply DC is turned on through the path from the second inductor L2 to the ground GND, and the charging of the second inductor L2 is started. The step-down control circuit 31 controls the fourth transistor M4 to be turned on after charging, and synchronously controls the third transistor M3 to be turned off, so that the ground end GND is turned on through the path from the second inductor L2 to the output end, and the second inductor L2 charges the charge pump sub-circuit 20 connected to the rear end of the output end separately, thereby realizing step-down.
The reference voltage output after the step-down sub-circuit 30 steps down is: vb=db×vdc. Where Vb is a reference voltage (i.e., a first reference voltage and/or a second reference voltage), db is a duty cycle of the third transistor M3, and Vdc is an output voltage of the direct current power supply DC. The value of Db may be adjusted by selecting a parameter for setting the third transistor M3, thereby adjusting the value of the reference voltage Vb output from the voltage-reducing sub-circuit 30.
Of course, the step-down sub-circuit 30 is not limited to the above-described circuit configuration, and a step-down function may be realized by using a conventional step-down circuit Buck. The third transistor M3 and the fourth transistor M4 in the voltage-reducing sub-circuit 30 may be a transistor, a thyristor, or the like, and are not limited thereto.
Specifically, the voltage-reducing sub-circuit 30 is provided to provide a reference voltage to regulate the working voltage output by the charge pump sub-circuit 20, so that the selectable range of the working voltage can be enriched and the circuit application scene can be increased on the basis of ensuring the integral multiple high-efficiency voltage boosting of the charge pump sub-circuit 20.
In an alternative embodiment, voltage stabilizing capacitors, such as Cx, cb, cgh and Cgl in fig. 1, may also be provided between the output of the boost sub-circuit 10 and ground GND, between the output of the buck sub-circuit 30 and ground GND, and between the output of the charge pump sub-circuit 20 and ground GND. And the output voltage of each port is stabilized through the arrangement of the voltage stabilizing capacitor.
The manner in which the remaining key parameters are set according to the desired operating voltage is described in the following with reference to fig. 1: the power supply generation circuit is assumed to include: a boost sub-circuit 10, a charge pump sub-circuit 20, and a buck sub-circuit 30. The power supply generating circuit outputs a first operating voltage VGH as an on voltage and also provides a second operating voltage VGL as an off voltage.
For example, if the first operating voltage VGH of 24V is required, the second operating voltage VGL of-14V is required. According to vgh=n×vx+vbase-h, vgl=vbase-l-m×vx, then: the intermediate voltage Vx of the boost output of the boost sub-circuit 10 is 7V, the positive voltage coefficient n=3 of the charge pump sub-circuit 20, the negative voltage coefficient m=2 of the charge pump sub-circuit 20, the first reference voltage Vbase-h is 3V, and the second reference voltage Vbase-l is 0V. The first operating voltage vgh=3×7+3=24v and the second operating voltage vgl=0-2*7 = -14V.
For another example, if the first operating voltage VGH of 20V is required, the second operating voltage VGL of-8V is required. Then it may be set that: the intermediate voltage Vx of the boost output of the boost sub-circuit 10 is 8.5V, the positive voltage coefficient n=2 of the charge pump sub-circuit 20, the negative voltage coefficient m=1 of the charge pump sub-circuit 20, the first reference voltage Vbase-h is 3V, and the second reference voltage Vbase-l is 0V. The first operating voltage vgh=2×8.5+3=20v and the second operating voltage vgl=0-1×8.5= -8.5V.
For another example, if the first operating voltage VGH of 20V is required, the second operating voltage VGL of-10V is required. Then it may be set that: the intermediate voltage Vx of the boost output of the boost sub-circuit 10 is 10V, the positive voltage coefficient n=2 of the charge pump sub-circuit 20, the negative voltage coefficient m=1 of the charge pump sub-circuit 20, the first reference voltage Vbase-h is 0V, and the second reference voltage Vbase-l is 0V. The first operating voltage vgh=2×10+0=20v and the second operating voltage vgl=0-1×10= -10V.
It can be seen that different operating voltage requirements can be met by the arrangement of the boost sub-circuit 10, the charge pump sub-circuit 20 and the buck sub-circuit 30. The efficiency of obtaining the intermediate voltage by the first stage boosting of the boosting sub-circuit 10 can reach more than 93% and the efficiency of obtaining the working voltage by the second stage boosting of the charge pump sub-circuit 20 can reach more than 94% through the cascade arrangement of the boosting sub-circuit 10 and the charge pump sub-circuit 20. The efficiency of the power supply generating circuit for generating the working voltage can reach more than 90% through the combination.
The embodiment of the invention also provides a display device which comprises the power supply generating circuit 01. Also has the same structure and advantageous effects as those of the power supply generation circuit 01 provided previously.
It should be noted that the display device may be a display panel such as an LCD, an OLED, or an LED, or may be any product or component with a display function such as a mobile phone, a liquid crystal panel, an OLED panel, electronic paper, a tablet computer, a television, a display, a notebook computer, a digital photo frame, or a navigator.
Since the power generation circuit included in the display device according to the embodiment of the present invention has been described in the foregoing, based on the power generation circuit according to the embodiment of the present invention, a person skilled in the art can understand the specific structure and effect principle of the display device, and therefore, the description thereof is omitted herein. All display devices including the power supply generating circuit according to the embodiments of the present invention belong to the scope of the present invention.
The technical scheme provided by the embodiment of the invention has at least the following technical effects or advantages:
according to the power generation circuit and the display device provided by the embodiment of the invention, the boosting sub-circuit and the charge pump sub-circuit are arranged in cascade connection to improve the power generation efficiency. Specifically, the input end of the voltage boosting sub-circuit is connected with a direct current power supply, and the output end of the voltage boosting sub-circuit is connected with the input end of the charge pump sub-circuit so as to boost the initial voltage provided by the direct current power supply into an intermediate voltage. Because the smaller the boosting amplitude of the boosting circuit is, the higher the corresponding power conversion efficiency is, the boosting module is firstly adopted to convert the direct current voltage into the intermediate voltage, and the efficiency can be ensured because the direct boosting is not required to be greatly and directly boosted into the working voltage. And then a charge pump is adopted to provide working voltage for a circuit needing power supply after the intermediate voltage is boosted by an integer. Because the charge pump has highest efficiency when boosting in integer multiples, different working voltage demands can be met through the arrangement of the intermediate voltage, and the efficiency can be further improved through boosting in integer multiples.
In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be construed as reflecting the intention that: i.e., the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
Those skilled in the art will appreciate that the modules in the apparatus of the embodiments may be adaptively changed and disposed in one or more apparatuses different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component and, furthermore, they may be divided into a plurality of sub-modules or sub-units or sub-components. Any combination of all features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or units of any method or apparatus so disclosed, may be used in combination, except insofar as at least some of such features and/or processes or units are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
Furthermore, those skilled in the art will appreciate that while some embodiments herein include some features but not others included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the following claims, any of the claimed embodiments can be used in any combination.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The use of the words first, second, third, etc. do not denote any order. These words may be interpreted as names.

Claims (8)

1. A power supply generation circuit, comprising:
a boost sub-circuit and a charge pump sub-circuit;
the input end of the boosting sub-circuit is connected with a direct current power supply, the output end of the boosting sub-circuit is connected with the input end of the charge pump sub-circuit so as to boost the initial voltage provided by the direct current power supply into an intermediate voltage, and the intermediate voltage is provided for the charge pump sub-circuit;
the output end of the charge pump sub-circuit is connected with a power supply circuit to be powered, so that after the intermediate voltage is boosted by integer times, working voltage is output from the output end to the power supply circuit to be powered;
the input end of the voltage reducing sub-circuit is connected with a direct current power supply, the output end of the voltage reducing sub-circuit is connected with a first reference end so as to reduce the initial voltage provided by the direct current power supply to a first reference voltage, and the first reference voltage is provided for the charge pump sub-circuit;
the charge pump sub-circuit comprises a first reference terminal, and the output terminal of the charge pump sub-circuit comprises a first output terminal;
the first working voltage output by the first output end is the sum of a first reference voltage and a first boosted voltage, the first reference voltage is the voltage received by the first reference end, and the first boosted voltage is the voltage obtained by boosting the intermediate voltage by integer times by the charge pump sub-circuit;
the charge pump sub-circuit further comprises a second reference terminal, and the output terminal of the charge pump sub-circuit further comprises a second output terminal;
the second working voltage output by the second output end is a difference value of a second reference voltage minus a second boosting voltage, the second reference voltage is a voltage received by the second reference end, and the second boosting voltage is a voltage obtained by boosting the charge pump sub-circuit and the intermediate voltage by integer multiples.
2. The circuit of claim 1, wherein the boost sub-circuit comprises:
the boost control circuit comprises a boost control circuit, a first inductor, a first transistor and a second transistor;
the first transistor and the second transistor are connected in series between the output end of the boosting sub-circuit and the ground end;
one end of the first inductor is connected with the direct current power supply, and the other end of the first inductor is connected with a series connection node of the first transistor and the second transistor;
the boost control circuit is connected with the grid electrodes of the first transistor and the second transistor, and controls the charge and discharge of the first inductor through controlling the switch of the transistor so as to boost the initial voltage.
3. The circuit of claim 1, wherein the charge pump sub-circuit comprises:
the charge pump control circuit and N groups of positive coupling capacitance circuits, wherein N is a positive integer;
each set of the positive coupling capacitance circuits includes: a positive coupling capacitor and two MOS transistors; the two MOS tubes are connected in series; one end of the positive coupling capacitor is connected with the output end of the boosting sub-circuit, and the other end of the positive coupling capacitor is connected with a series connection node of the two MOS tubes;
the N groups of positive coupling capacitance circuits are connected in series between the first output end and the first reference end in a serial manner that MOS tubes in the two groups of positive coupling capacitance circuits are connected in series;
the charge pump control circuit is connected with the grid electrode of each MOS tube in the N groups of positive coupling capacitance circuits so as to control the intermediate voltage to be boosted by N times.
4. The circuit of claim 1, wherein the charge pump sub-circuit further comprises:
m groups of negative coupling capacitance circuits, M being a positive integer;
each set of the negative coupling capacitance circuits includes: a negative coupling capacitor and two MOS tubes; the two MOS tubes are connected in series; one end of the negative coupling capacitor is connected with the output end of the boosting sub-circuit, and the other end of the negative coupling capacitor is connected with a series connection node of the two MOS tubes;
the M groups of negative coupling capacitance circuits are connected in series between the second output end and the second reference end in a serial manner that MOS tubes in the two groups of negative coupling capacitance circuits are connected in series;
the charge pump control circuit is connected with the grid electrode of each MOS tube in the M groups of negative coupling capacitance circuits so as to control the medium voltage to be boosted by M times.
5. The circuit of claim 1, wherein the buck sub-circuit comprises:
the step-down control circuit, the second inductor, the third transistor and the fourth transistor;
the third transistor and the fourth transistor are connected in series between a direct current power supply and a ground terminal;
one end of the second inductor is connected with the output end of the voltage dropping sub-circuit, and the other end of the second inductor is connected with a series connection node of the third transistor and the fourth transistor;
the step-down control circuit is connected with the gates of the third transistor and the fourth transistor, and controls the charge and discharge of the second inductor by controlling the switch of the transistor so as to step down the initial voltage.
6. The circuit of claim 5, wherein the first reference terminal is connected to either:
the output end of the step-down sub-circuit, the output end of the step-up sub-circuit and the ground end.
7. A circuit as claimed in any one of claims 1 to 6, wherein:
and voltage stabilizing capacitors are arranged between the output end of the boost sub-circuit and the ground end and between the output end of the charge pump sub-circuit and the ground end.
8. A display device comprising the power supply generating circuit according to any one of claims 1 to 7.
CN202111223152.4A 2021-10-20 2021-10-20 Power supply generating circuit and display device Active CN113824315B (en)

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