JPH08181918A - Booster circuit and solid-state image pickup device using same - Google Patents

Abstract

PURPOSE: To obtain a stable booster circuit immune to fluctuation in a power supply voltage and a clock frequency by reducing a fluctuation component ΔVout in a booster output voltage Vout attended with the fluctuation in a power supply voltage Vdd and a clock frequency. CONSTITUTION: This booster circuit is a clock drive type booster circuit with the configuration such that, for example, three NMOS transistors(TRs) M1-M3 whose gates and drains are connected in common respectively are connected in series between a positive side of a power supply 1 and a circuit output terminal 2 in a positive polarity from the power supply 1 toward the circuit output terminal 2 and clock pulses ϕ1, ϕ2 inverse to each other are applied to output terminals N1, N2 of a 1st and 2nd stage NMOS TRs M1, M2 via capacitors C1, C2 respectively. Then a load circuit 8 comprising a MOS TR M4 whose drain is connected to the circuit output terminal 2 and whose source is connected to the ground is provided and the power supply voltage Vdd is applied to the gate of the MOS TR M4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a booster circuit and a solid-state image pickup device using the booster circuit, and more particularly to a clock-driven booster circuit and a solid-state image pickup device using the booster circuit.

[0002]

2. Description of the Related Art A conventional example of a clock drive type booster circuit is shown in FIG. In the figure, between the positive side of the power supply 101 and the circuit output terminal 102, a so-called diode-connected N-channel type MOS whose gate and drain are commonly connected is provided.
FET (hereinafter simply referred to as NMOS transistor) M
1 n are connected in series in the forward direction from the power supply 101 side toward the circuit output terminal 102 side, for example, in three stages.

The output terminal N11 of the first-stage NMOS transistor M11 has three stages of inverters 103, 104, 1
The clock pulse φ1 which is sequentially inverted and supplied at 05 is applied via the capacitor C1. On the other hand, the second N
A clock pulse φ1 having a phase opposite to that of the clock pulse φ1 which is sequentially inverted and supplied by the four-stage inverters 103, 104, 106 and 107 is applied to the output terminal N12 of the MOS transistor M12 via the capacitor C2. A load capacitor C is provided between the output terminal N13 (circuit output terminal 102) of the third-stage NMOS transistor M13 and the ground.
L is connected.

Next, the boosting operation in the steady state of the conventional booster circuit having the above-mentioned structure will be described with reference to the timing waveform chart of FIG. First, the clock pulse φ1 is “L”
At the time of the level, since the gate and drain of the NMOS transistor M11 are connected to the positive side of the power supply 101, the voltage V11 at the output terminal N11 thereof is the power supply voltage Vd.
It is Vx11 lower than d. Here, Vx11 is a voltage drop amount due to the threshold voltage Vth of the NMOS transistor M11. In this state, when the clock pulse φ1 is input via the capacitor C1, the peak value of the clock pulse φ1 is applied to the NMOS transistor M1.
The voltage V11 at the output terminal N11 of No. 1 is boosted.

On the other hand, since the clock pulse φ2 has a phase opposite to that of the clock pulse φ1, when the clock pulse φ2 is at the "L" level, the NMOS transistor M12.
Of the output terminal N12 is equal to the voltage V12 of the output terminal N11.
It is Vx12 lower than 11. Where Vx12
Is a voltage drop due to the threshold voltage Vth of the NMOS transistor M12. In this state, the capacitor C2
When the clock pulse φ2 is input via the clock pulse φ2, the NMOS transistor M
The voltage V12 at the 12 output terminals N12 is boosted.

The voltage V12 at the output terminal N12 is NMO.
Smoothed by the S-transistor M13 and the load capacitor CL, the boosted output voltage Vo is output from the circuit output terminal 102.
It is derived as ut. The boosted output voltage Vou
t is lower than the voltage V12 of the output terminal N12 by Vx13. Here, Vx13 is an NMOS transistor M
This is the voltage drop due to the threshold voltage Vth of 13. As is apparent from the above description, in the clock drive type booster circuit, the peak value of the clock pulses φ1 and φ2 is Vw.
Then, with respect to the power supply voltage Vdd, (Vw-V
The boosted output voltage Vout is obtained by sequentially boosting by x1n).

[0007]

However, in the conventional booster circuit having the above configuration, when the power supply voltage Vdd changes, the amplitudes of the clock pulses φ1 and φ2 also change accordingly, so that the boosted output voltage Vout is changed. There was a problem that there was a large fluctuation. That is, in the case of the triple boosting circuit shown in FIG. 6, when the power supply voltage Vdd increases by ΔVdd, the amplitudes of the clock pulses φ1 and φ2 also increase by approximately ΔVdd, as shown in FIG. The variation ΔVout of the boosted output voltage Vout is about 3
× ΔVdd. As described above, when the boosted output voltage Vout largely fluctuates by a fluctuation multiple ΔVdd corresponding to the fluctuation of the power supply voltage Vdd, the characteristics of the device or circuit operating at the boosted output voltage Vout of the booster circuit. Will be adversely affected.

Still another problem is that the boosted output voltage Vout has a clock frequency dependency. That is, as shown in FIG. 8, when the clock frequency increases, the boosted output voltage Vout increases (= closes to the regular boosted value when the load current is small). Figure 10
Shows the timing waveform when the clock frequency changes. This frequency dependence occurs when the current consumption on the load side is larger than or equal to the current capacity of the booster circuit. This current capacity increases the clock frequency and M
It can be increased by increasing the channel width of the OS transistor (increasing the mutual conductance g _m ). Therefore, if the booster circuit is configured to have a sufficient margin for the current consumption on the load side, the clock frequency dependency does not occur.

However, in order to do so, it is necessary to increase the size of each circuit element such as the MOS transistor and the capacitor that constitute the booster circuit. Therefore, the booster circuit generates the substrate voltage Vsub of the CCD linear sensor, for example. For example, when used as a Vsub generating booster circuit, it is manufactured (on-chip) on the same substrate (chip) as the sensor array of the CCD linear sensor, the charge transfer register, and the like.
Sometimes it is difficult to do.

The present invention has been made in view of the above problems, and an object of the present invention is to reduce the fluctuation amount ΔVout of the boosted output voltage Vout due to the fluctuations of the power supply voltage Vdd and the clock frequency to reduce the power supply voltage and An object of the present invention is to provide a stable booster circuit that is resistant to fluctuations in the clock frequency and a solid-state imaging device using the same.

[0011]

According to a first aspect of the present invention, there is provided a step-up circuit in which a unidirectional element is serially connected in a plurality of stages in a forward direction from a power source side to a circuit output terminal side between a power source and a circuit output terminal. A booster circuit connected to each stage through which a clock pulse is applied via a capacitor, which is composed of at least one MOS transistor whose source or drain is connected to a circuit output terminal, and which has a gate connected to this MOS transistor. It has a configuration including a load circuit to which a power supply voltage is applied.

According to another aspect of the booster circuit of the present invention, between the power source and the circuit output terminal, unidirectional elements are connected in series in a plurality of stages in the forward direction from the power source side toward the circuit output terminal side, and each stage is connected in series. A booster circuit to which a clock pulse is applied via a capacitor, which is composed of at least two MOS transistors connected in series between a circuit output terminal and a reference potential point, and at least one of these two MOS transistors. A load circuit is provided in which a clock pulse having the same frequency as the clock pulse is applied to one gate.

[0013]

In the booster circuit according to the first aspect, when the power source is turned on, the unidirectional elements in a plurality of stages are in a forward bias state, and are therefore in a conducting state. Then, the boosting operation is performed by each unidirectional element in synchronization with clock pulses having opposite phases. In this state, if the power supply voltage changes,
Since the gate voltage of the MOS transistor of the load circuit also changes, the current flowing through the MOS transistor changes according to the voltage change. Therefore, as a result, the fluctuation of the boosted output voltage with respect to the fluctuation of the power supply voltage is suppressed.

In the booster circuit according to the second aspect of the present invention, when the power source is turned on, the unidirectional elements in a plurality of stages are in a forward bias state, and are therefore in a conducting state. Then, the boosting operation is performed by each unidirectional element in synchronization with clock pulses having opposite phases. In this state, if the frequency of the clock pulse fluctuates, at least one MOS of the load circuit
Since the frequency of the gate voltage of the transistor also changes, the current flowing through the load circuit changes according to the frequency change. Therefore, as a result, the fluctuation of the boosted output voltage with respect to the frequency fluctuation of the clock pulse is suppressed. Further, even when the power supply voltage changes, the current flowing through the load circuit changes, so that the change in the boosted output voltage with respect to the change in the power supply voltage can be suppressed.

[0015]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a circuit diagram showing a first embodiment of the present invention. In FIG. 1, a gate and a drain are commonly connected between the positive side of the power supply 1 and the circuit output terminal 2.
The MOS transistor Mn serves as a unidirectional element, and the power source 1
From the side toward the circuit output terminal 2 side, for example, three stages are connected in series in the forward direction. That is, the gate and drain of the first-stage NMOS transistor M1 are wired to the positive side of the power supply 1, the gate and drain of the second-stage NMOS transistor M2 are wired to the source of the first-stage NMOS transistor M1, and the third-stage The gate and drain of the second NMOS transistor M3 are the second-stage NMOS transistor M
The source of the third stage NMOS transistor M3 is wired to the circuit output terminal 2.

The first-stage NMOS transistor M
Inverters 3, 4, 5 are connected to the output terminal (source) N1 of
The clock pulse φ1 which is sequentially inverted and supplied at is applied via the capacitor C1. On the other hand, the second NMO
To the output terminal (source) N2 of the S-transistor M2, a clock pulse φ2 having a phase opposite to that of the clock pulse φ1 which is sequentially inverted and supplied by the inverters 3, 4, 6 and 7 is applied via the capacitor C2. A load capacitor CL and a load circuit 8 are connected between the output terminal (source) N3 of the third-stage NMOS transistor M3 wired to the circuit output terminal 2 and the ground.

In the load circuit 8, for example, the drain is connected to the circuit output terminal 2 (the output terminal N3 of the NMOS transistor M3), the source is grounded, and the gate is the power supply voltage Vd.
It is constituted by an NMOS transistor M4 to which d is applied. In the load circuit 8, the current flowing through the NMOS transistor M4 is set to be larger than the total load current flowing through the rest. In particular,
It is preferable to set the current flowing through the NMOS transistor M4 to be one digit larger than the total load current.
Further, the current flowing through the NMOS transistor M4 is set to be equal to about 1/10 with respect to the output current capacity of the booster circuit.

Next, the boosting operation in the boosting circuit according to the first embodiment having the above configuration will be described with reference to the timing waveform chart of FIG. First, when the power supply 1 starts up,
Since the NMOS transistors M1 to M3 are in a forward bias state, they are in a conductive (on) state. In this state,
When clock pulse φ1 is at "L" level, NMOS
Since the gate and drain of the transistor M1 are connected to the positive electrode side of the power supply 1, the voltage V
1 is Vx1 lower than the power supply voltage Vdd.
Here, Vx1 is a voltage drop amount due to the threshold voltage Vth of the NMOS transistor M1.

In this state, when the clock pulse φ1 is input via the capacitor C1, the voltage V1 at the output terminal N1 of the NMOS transistor M1 is boosted by the peak value of the clock pulse φ1. On the other hand, since the clock pulse φ2 has an opposite phase to the clock pulse φ1, when the clock pulse φ2 is at the “L” level, the NMOS
The voltage V2 at the output terminal N2 of the transistor M2 is
It is lower than the voltage V1 of 1 by Vx2. Here, Vx2 is the threshold voltage Vt of the NMOS transistor M2.
This is the voltage drop due to h.

In this state, when the clock pulse φ2 is input via the capacitor C2, the voltage V2 at the output terminal N2 of the NMOS transistor M2 is boosted by the peak value of the clock pulse φ2. The voltage V2 at the output terminal N2 is smoothed by the NMOS transistor M3 and the load capacitor CL, and is derived from the circuit output terminal 2 as the boosted output voltage Vout. The boosted output voltage Vout is lower than the voltage V2 at the output end N2 by Vx3. Here, Vx3 is a voltage drop amount due to the threshold voltage Vth of the NMOS transistor M3.

Now, consider a case where the power supply voltage Vdd changes by, for example, ΔVdd to the higher side. Power supply voltage V
When dd increases, a boosting operation is performed to increase the boosted output voltage Vout according to the variation ΔVdd.
At this time, since the power supply voltage Vdd is also applied to the gate of the NMOS transistor M4 of the load circuit 8, the current flowing through the NMOS transistor M4 also varies by ΔV.
Since it increases with dd, the boosted output voltage V
The rise of out is suppressed.

In the load circuit 8, the current flowing through the NMOS transistor M4 is set to be approximately equal to 1/10 of the output current capacity of the booster circuit, as described above. The fluctuation of the current flowing through the positive transistor positively affects the boosted output voltage Vout, and the NMOS transistor M
It is set to be larger than the total load current flowing except for 4, so that the boosted output voltage Vou with respect to the power supply voltage Vdd is set.
It is possible to suppress the variation ΔVout of t as small as possible.

In the first embodiment, the power supply voltage Vdd is directly applied to the gate of the NMOS transistor M4, but the power supply voltage Vdd may be divided and applied. Although the load circuit 8 is composed of N-channel type MOS transistors, P-channel type MOS transistors are used and its source is NM.
It is also possible to connect to the output terminal N3 of the OS transistor M3, ground the drain, and invert and apply the power supply voltage Vdd or a voltage obtained by dividing the power supply voltage Vdd to the gate.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention. In the figure, the same parts as those in FIG. 1 are designated by the same reference numerals. In the second embodiment, a CMOS inverter including a PMOS transistor and an NMOS transistor connected in series between the output terminal N3 (circuit output terminal 2) of the NMOS transistor M3 and the ground (reference potential point) has, for example, three stages. A load circuit 8'connected to the above is used to apply, for example, a clock pulse φ2 to the input terminal (gate common connection point) of the first-stage CMOS inverter. In this load circuit 8 ', the CMO
The S inverter has a current characteristic that the average current is proportional to the frequency because a current flows in the transient portion of the input waveform. That is, the load circuit 8'becomes a circuit in which current flows with clock frequency dependence.

As described above, by connecting the load circuit 8'where the current flows as a load with clock frequency dependence to the circuit output terminal 2 (the output terminal N3 of the NMOS transistor M3), as shown in the timing waveform diagram of FIG. To
Even if the frequency of the clock pulses φ1 and φ2 fluctuates, for example, the current flowing through the load circuit 8 ′ increases according to the fluctuation of the frequency, so that the fluctuation of the boosted output voltage Vout due to the frequency fluctuation can be suppressed. it can.

The current flowing through the load circuit 8'is also proportional to the change in the power supply voltage Vdd. That is, the power supply voltage V
If dd fluctuates in the direction of increasing, NM will be generated by the boosting operation.
Although the potential of the output terminal N3 of the OS transistor M3 also tries to rise, the current flowing through the load circuit 8'becomes larger as the potential of the output terminal N3 rises. Therefore, as a result, the boosted output voltage V
The fluctuation of out can be suppressed.

In the second embodiment, the CMO of three stages is used.
Although the load circuit 8'is configured by the S inverter, the present invention is not limited to this, and the clock pulses φ1, φ2
Any configuration may be used as long as the current flows in proportion to the frequency. For example, an NMOS inverter composed of two NMOS transistors or a P composed of two PMOS transistors connected in series between the circuit output terminal 2 and the ground.
Providing at least one MOS inverter,
Even in the load circuit configured to apply the clock pulse to the gate of one MOS transistor of the inverter, it is possible to suppress the fluctuation of the boosted output voltage Vout with respect to the fluctuation of the power supply voltage Vdd.

FIG. 5 is a block diagram showing an example of a solid-state image pickup device using the booster circuit according to the first or second embodiment described above as a Vsub generation booster circuit. In this example, a case where the solid-state imaging device is applied to a CCD linear sensor is shown, but the application is not limited to the CCD linear sensor, and the solid-state imaging device is not limited to the CCD and can be applied to all solid-state imaging devices including an area sensor. It is a thing. As shown in FIG.
The D linear sensor is a sensor array 1 in which a plurality of light receiving portions 11 including photo diodes for converting incident light into signal charges having a charge amount corresponding to the light amount and accumulating the signal charges are arranged in a line.
2 and a CCD for transferring the signal charge read from each light receiving portion 11 of the sensor array 12 through the read gate 13.
And a charge transfer register 14 composed of.

The read gate 13 has a read pulse φRO.
When G is applied, each light receiving unit 1 of the sensor array 12
The signal charges stored in 1 are read out all at once to the charge transfer register 14. The charge transfer register 14 has a transfer clock φ.
The signal charges are transferred by being driven in two phases by H1 and φH2. At the final stage of the charge transfer register 14, a charge-voltage converter (charge detector) 15 having, for example, a floating diffusion configuration that detects the transferred signal charge and converts it into a voltage is formed. The output voltage of the charge-voltage converter 15 is derived as a CCD output from the output terminal 17 via the buffer 16.

In the CCD linear sensor having the above structure,
The booster circuit according to the present invention is used as the Vsub generation booster circuit 18 that boosts the power supply voltage Vdd to generate the substrate voltage Vsub. The Vsub generation boosting circuit 18 is manufactured (on-chip) on the same substrate (chip) as the sensor array 12, the charge transfer register 14, etc., and the clock pulse φ
Two-phase transfer clocks φH1 and φH2 are used as 1 and φ2. The booster circuit according to the present invention can be used not only as the Vsub generation booster circuit 18 but also as a booster circuit that supplies an operating power supply voltage to other circuits such as the buffer 16.

As described above, since the booster circuit according to the present invention is used as the Vsub generation booster circuit 18 because the booster circuit according to the present invention is resistant to fluctuations in the power supply voltage, even if the power supply voltage Vdd changes, Since the variation ΔVsub of the substrate voltage Vsub can be suppressed to be small, it is possible to provide a stable CCD linear sensor that is resistant to power supply voltage variations. Further, since the booster circuit is on-chip, the number of parts of the external circuit can be reduced, so that the configuration can be simplified.

[0032]

As described above, according to the first aspect of the invention, in the clock driving type booster circuit, the load circuit including at least one MOS transistor having the source or the drain connected to the circuit output terminal is provided. By providing the configuration in which the power supply voltage is applied to the gate of the MOS transistor, the current flowing through the MOS transistor changes according to the change in the power supply voltage, so that the change in the boosted output voltage with respect to the change in the power supply voltage can be suppressed. it can.

According to the second aspect of the invention, in the clock drive type booster circuit, a load circuit comprising at least two MOS transistors connected in series is provided between the circuit output terminal and the reference potential point. Since the clock pulse having the same frequency as the boost driving clock pulse is applied to at least one of the gates of the two MOS transistors, the current flowing through the load circuit changes according to the fluctuation of the clock frequency and the fluctuation of the power supply voltage. For,
It is possible to suppress the fluctuation of the boosted output voltage due to the fluctuation of the clock frequency and the fluctuation of the power supply voltage.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a timing waveform chart at the time of power supply fluctuation in the first embodiment.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a timing waveform chart when the clock frequency changes in the second embodiment.

FIG. 5 is a configuration diagram of a CCD linear sensor according to the present invention.

FIG. 6 is a circuit diagram showing a conventional example.

FIG. 7 is a timing waveform diagram in a steady state in a conventional example.

FIG. 8 is a characteristic diagram showing the clock frequency dependence of the boosted output voltage in the conventional example.

FIG. 9 is a timing waveform diagram at the time of power supply fluctuation in the conventional example.

FIG. 10 is a timing waveform diagram when the clock frequency changes in the conventional example.

[Explanation of symbols]

 1 power supply 2 circuit output terminals 3 to 7 inverter 8,8 'load circuit

Claims (5)

[Claims] 1. A unidirectional element is connected in series between a power source and a circuit output terminal in a forward direction from a power source side to a circuit output terminal side, and a clock pulse has a capacitor between each stage. A booster circuit applied through the MOS transistor, which comprises at least one MOS transistor whose source or drain is connected to a circuit output terminal,
A booster circuit comprising a load circuit in which a power supply voltage is applied to the gate of an S transistor. 2. A unidirectional element is connected in series in a forward direction from a power source side to a circuit output terminal side between a power source and a circuit output terminal, and a clock pulse has a capacitor between each stage. A voltage booster circuit applied via the clock pulse terminal, comprising at least two MOS transistors connected in series between a circuit output terminal and a reference potential point, and having at least one gate of the two MOS transistors connected to the clock pulse. A booster circuit comprising a load circuit to which a clock pulse having the same frequency as that of 1. 3. A sensor unit in which a plurality of light receiving units for converting incident light into a signal charge having a charge amount corresponding to the amount of light and storing the signal charges are arranged, and a signal read from each light receiving unit of the sensor unit. 3. A solid-state imaging device comprising: a charge transfer register that transfers charges; and a charge detection unit that detects the signal charges transferred by the charge transfer register, converts the signal charges into an electric signal, and outputs the electric signal. A solid-state imaging device comprising the above described booster circuit. 4. The solid-state imaging device according to claim 3,
A solid-state imaging device, wherein a boosted output voltage from the booster circuit is used as a substrate voltage. 5. The solid-state imaging device according to claim 3,
A solid-state imaging device, wherein the booster circuit is formed on the same substrate as the sensor unit, the charge transfer register, and the charge detection unit.