JPH01140810A - Switched capacitor circuit - Google Patents

Abstract

PURPOSE:To realize the improvement of an output characteristic with simple constitution by preventing the switching control of other switch elements when a switch element connected to the virtual ground input of an operational amplifier circuit is in an ON state. CONSTITUTION:When input signal charges are fetched into input side capacitors C1-Cn, the switch elements Q1-Qn connected to the capacitors are turned on or off according to the input digital signal values of bits corresponding to respective capacitors. Thus, respective capacitors are discharged according to the input digital signal values, and charged up by a reference voltage VR. When the signal charges of the capacitors C1-Cn are transmitted to an output side capacitor CO provided between the virtual ground input terminal and an output terminal Vout in the operational amplifier circuit OP, the control of the switch elements Q1-Q6 connected to the capacitors C1-Cn is stopped and only switch elements 7 and 8 are turned on.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a switched capacitor circuit, and relates to a technique that is effective when applied to, for example, a D/A conversion circuit using a switched capacitor circuit.

[Conventional technology]

The switched capacitor circuit uses two-phase non-overlapping clock pulses: a sampling clock pulse φ1 and an output or integration clock pulse φ2. Regarding a switched capacitor circuit using such non-overlapping clock pulses φ1 and φ2, there is, for example, Japanese Patent Laid-Open No. 149417/1983.

[Problem that the invention seeks to solve]

The inventor's research has revealed that even when non-overlapping two-phase clock pulses are used as described above, the following problems occur. That is, when the switch element provided between the input-side capacitor and the inverting input terminal, which is the virtual ground of the operational amplifier circuit, is turned on, in other words, the charge on the input-side capacitor is transferred to the operational amplifier circuit. When transmitting information to the output side (integration) capacitor provided between the inverting input terminal and the output terminal, there are some cases in which other switching elements are also controlled at the same time, and due to the small phase shift, it is difficult to control the switch. The clock pulse passes through the parasitic capacitance between the gate and channel or source and drain of the transmission gate MO8FET that constitutes the switching element, and switching noise is transmitted to the output side.

As a result, when a D/A conversion circuit is configured using a switched capacitor circuit, for example, linearity and S/N (signal-to-noise ratio) deteriorate due to the feedthrough and noise.

An object of the present invention is to provide a switched capacitor circuit that achieves improved output characteristics with a simple configuration.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, when a switch element coupled to a virtual ground input of an operational amplifier circuit is in an on state among a plurality of switch elements constituting a switched capacitor circuit, switching control of other switch elements is not performed.

(Function) According to the above means, when the switch element that transmits the signal charge of the input side capacitor to the output side capacitor is turned on, switch control of other switch elements is not performed. Feedthrough and switching noise generated in the output capacitor are not transmitted to the output capacitor, thereby improving characteristics.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment in which the present invention is applied to a D/A conversion circuit.

Each circuit element and circuit block in the figure is a well-known 0MO3
(Complementary MO3) Depending on the integrated circuit manufacturing technology, it is formed on a single semiconductor substrate such as, but not limited to, single crystal silicon.

In the figure, a P-channel MOSFET is distinguished from an N-channel MOSFET by an arrow added to its channel (back gate) portion.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single-crystal P-type silicon. N channel MOS
The FET has a source region, a drain region formed on the surface of the semiconductor substrate, and a gate made of polysilicon formed on the surface of the semiconductor substrate between the source region and the drain region with a thin gate insulating film interposed therebetween. Consists of electrodes. The P-channel MOSFET is formed in an N-type well region formed on the surface of the semiconductor substrate.

Thereby, the semiconductor substrate constitutes a common substrate gate for a plurality of N-channel MOSFETs formed thereon. The N-type well region constitutes the substrate gate of the P-channel MOSFET formed thereon. Although not particularly limited, the semiconductor substrate is given a circuit ground potential, and the substrate gate of the P-channel MOSFET, that is, N
The type well region is coupled to a positive power supply terminal VCC.

A P-channel MOSFET QI and an N-channel MOSFET 7 are connected between the reference voltage VR and one electrode of the input capacitor C1.
A CMOS switch circuit consisting of a 1zMOSFETQ2 is provided. Clock pulse φ□ is supplied to the gate of N-channel MOSFET Q2, and P-channel MOSFET
The clock pulse φAl is inverted and supplied to the gate of ETQI by an inverter circuit N1. As a result, when the clock pulse φA+ is at a high level, the MO
SFETs QI and Q2 are both turned on and transmit the reference voltage VR to one electrode of the capacitor CI.

A CMOS switch circuit including a P-channel MOSFET Q3 and an N-channel MOSFET Q4 is provided between one electrode of the capacitor C1 and the ground potential point of the circuit. A clock pulse φ31 is supplied to the gate of the N-channel MOSFET Q4, and the clock pulse φ□ is inverted and supplied to the gate of the P-channel MOSFET Q3 by an inverter circuit N2. As a result, when the clock pulse φ,1 is at a high level, the MOSFETs Q3 and Q4 are both turned on, and the ground potential of the circuit is transmitted to one electrode of the capacitor C1.

A P-channel MOSFET Q5 and an N-channel MOSFET Q5 are connected between the other electrode of the capacitor C1 and the ground potential point of the circuit.
A CMOS switch circuit consisting of an OSFETQ6 is provided. Clock pulse φ is applied to the gate of N-channel MOSFET Q6. is supplied, P-channel MO5FET
The clock pulse φ is inverted and supplied to the gate of Q5 by an inverter circuit N3. This causes the clock pulse φ. When is at high level, the above MOSFET
Q5 and Q6 are both turned on, transmitting the circuit's ground potential to one electrode of capacitor CI.

A CMOS switch circuit including a P-channel MOSFET Q7 and an N-channel MOSFET QB is provided between the other electrode of the capacitor C1 and the inverting input terminal - (virtual ground terminal) of the operational amplifier circuit OP. A clock pulse φ is supplied to the gate of N-channel MOSFET Q8, and the clock pulse φ is supplied to the gate of P-channel MOSFET Q7. is inverted and supplied by an inverter circuit N4. As a result, when the clock pulse φ is at a high level, the MOSFETs Q7 and Q8 are both turned on, and the input side capacitor and the output side capacitor CO, which will be explained next, are connected to transfer charge between the capacitors. .

The non-inverting input terminal + of the operational amplifier circuit OP is given the ground potential point of the circuit, and the inverting input terminal - and the output terminal V
An output side (integration) capacitor CO is provided between the output side and the output side (integration) capacitor CO. This capacitor CO includes a P-channel inter-channel O3FETQ9 and an N-channel MOSFET in parallel.
A CMOS switch circuit for reset consisting of QIO is provided. A reset pulse φ is supplied to the gate of the N-channel MOSFET QIO, and the voltage between the P-channels O3
The reset pulse φ is inverted and supplied to the gate of FETQ9 by an inverter circuit N5. As a result, when the reset pulse φ is at a high level, the above MOS
Both FETQ9 and QIO are turned on to discharge (reset) the charge in the output side capacitor CO.

A plurality of input circuits similar to those described above are provided to perform digital/analog conversion operations. That is, the above MO
SFETCI to Q8 and inverter circuits N1 to N4
A plurality (n) of circuits similar to the capacitor C1 and the capacitor C1 are provided. In the figure, a circuit corresponding to the capacitor C1 and an n-th circuit are exemplarily shown as representatives. The clock pulses supplied to the nth circuit are as follows: φAn, φlln. However, the MOSFET constituting the n-th switch circuit
The circuit symbols of the inverter circuit and the inverter circuit are omitted.

The capacitance values of the capacitors CI to Cn are weighted in accordance with the digital values based on the capacitance value of the output side capacitor CO. For example, capacitor C1
The capacitance value of capacitor c.

, the capacitance value of the n-th capacitor Cn is set to a capacitance value such as C0X2'. This results in a digital/analog conversion circuit that converts a digital signal consisting of n bits into an analog signal.

The operation of this embodiment circuit will now be described with reference to the operational waveform diagram of FIG.

Prior to the digital/analog conversion operation, the reset pulse φ8 is set to high level. This allows MOSF
ETQ9 and QIO are turned on and the output side capacitor CO is reset.

Input signal charge is taken in as follows.

While the input signal charge is being taken in, the clock pulse φ0 is set to a high level and the corresponding CMOS switch circuit is turned on, so that the ground potential of the circuit is applied to the other electrode side of the capacitors 01 to Cn. At this time, the clock pulse φ. is set to a low level, the corresponding CMOS switch circuit is turned off, and the input side capacitors C1 to Cn and the output side capacitor CO are separated. The above clock pulse φ. andφ. are non-overlapping clock pulses, and both lock pulses φC and φ. Both CMOS switch circuits corresponding to the above are not turned on.

For example, if the least significant bit is logic "O", clock pulse φ4. is set to low level, and clock pulse φ1 is set to high level. Therefore, since MOSFETs Ql and 02 are turned off and MOSFETs Q3 and Q4 are turned on, the ground potential of the circuit is supplied to the corresponding picture electrode of the capacitor C1, thereby discharging the capacitor C1.

On the other hand, if the most significant bit is logic "1", clock pulse φA,l goes to low level and clock pulse φh
is raised to a high level. Therefore, the above MOSFET
The CMOS switch circuits corresponding to QI and Q2 are turned on, and the CM corresponding to the above MOS FETQ3 and Q4 is turned on.
Since the OS switch circuit is turned off, the corresponding capacitor Cn is charged up with the reference voltage VR.

Then, when transmitting the charges taken into the capacitors 01 to Cn in response to the input digital signal as described above to the output side capacitor CO, a clock pulse φ is applied. In synchronization with the change of clock pulse φ6. to low level, the clock pulse φ6. and φA,1 is changed from high level to low level.

That is, the clock pulse φ. and the clock pulse for taking in the input signal (in the above example, φ3. and φA, . . . ) are made to be signals in the same phase.

The clock pulse for output is divided into two.

That is, the clock pulses φAl and φ□ or φAn and φ used to capture input charges are non-overlapping signals with opposite phases, and in the above example, the clock pulse φ□ corresponds to the clock pulse φ□. After non-overlap, the clock pulse φl rises to high level.
lr+ rises to high level after non-overlap in response to clock pulse φ.

In this way, the clock pulses φ□~φ□ and φ□~φ are the logic “O” and logic “O” of the corresponding input digital signals.
The clock pulse φ changes its phase according to the change in the clock pulse φ1 to φB7, which should be set to high level as described above, after a certain period of time has elapsed. be brought to a high level.

As a result, the capacitors 01 to Cn are coupled to the inverting input terminal - of the operational amplifier circuit OP of virtual ground via the CMOS switch circuit which is turned on in response to the high level of the clock pulse φD. Therefore, charges are exchanged between the capacitors 01 to C11 and C○.

When the capacitor C1 has no charge as described above, the clock pulse φ4. Since the reference voltage VR is supplied to one electrode in response to the high level of , a charge such as -VR-CI is required there. Capacitor Cn has VRX
A charge of Cn (=VRxC1x2'') is accumulated.The other bits are also connected to the above-mentioned Q and dopasitor CI due to the logic “O”.
Assuming that there is no charge in the same manner as above, each of the capacitors requires a charge like the above-mentioned capacitor C1, so the output voltage Vout is obtained from the combination of the charges in each of the capacitors CI to Cn as described above, and C1 =GO, so Vout =VR(2°-21-...-2n-
1+2m). In this way, the output signal Vout
is the VR (
-2'-2'-...-2"-'-2") to VR (+2°
+21 +...+21%-1+211), which is an analog voltage that changes up to the maximum voltage.

Note that when entering the next charge capture period, after the clock pulse φD changes from high level to low level, the clock pulses φAl and φ, which have been set to high level,
is set to low level. Then, if the next digital/analog converted signal is added to the analog converted signal and output, synchronize with the change of the clock pulse φ to high level to capture the input signal charge.
For example, clock pulses φ□, φ□, etc. are changed to high level in response to the input digital signal.

FIG. 3 shows a circuit diagram of an embodiment of a clock pulse generation circuit for forming the above-mentioned clock pulses. This clock pulse generation circuit will be explained with reference to the operational waveform diagram shown in FIG.

The basic clock pulse φ is supplied to one input of one NAND gate circuit G1.

The clock pulse φ is supplied to one input of the other Nant gate circuit G2 via an inverter circuit N6. The output signal of the one Nant gate circuit G1 is supplied to the other input of the other Nant gate circuit G2 through series delay circuits DLI and DL2. The output signal of the other Nant gate circuit G2 is supplied to the other input of the one Nant gate circuit G1 through series delay circuits DL3 and DL4. Thereby, the Nant gate circuits G1 and 02 constitute a type of flip-flop circuit.

When the basic tarock pulse φ is at a low level (logic "O"), the output signal A of one Nant gate circuit G1 is set at a high level. The other Nant's gate circuit G2 has the output of the inverter circuit N6 at a high level and the above-mentioned Nant's gate circuit Gl through the delay circuits DLI and DL2.
Since the output is at a high level, an output signal B at a low level is formed.

In this state, when the clock pulse φ changes from low level to high level, the output signal of inverter circuit N6 changes from high level to low level accordingly. Therefore, the output signal B of the Nant gate circuit G2 changes from low level to high level. The change from the low level to the high level of the Nant gate circuit G2 is delayed by the delay circuits DL3 and DL4.
is transmitted to the other input. Therefore, the output signal A of the Nant gate circuit G1 is output from the delay circuits DL3 and DL4.
After a delay time (DL3+DL4), the level changes from high to low.

Furthermore, when the clock pulse φ changes from high level to low level in the above state, the output signal A of the Nant gate circuit G1 changes from low level to high level accordingly. In response to the low level of the clock pulse φ, the output signals of the inverter circuits F and FN6 change from low level to high level. However, the above Nant gate circuit G1
The high level output signals to the delay circuits DLI and DL2
Since the transmission is delayed through the Nant gate circuit G2
The output signal of is maintained at a high level. and,
Delay time (DL) of the above delay circuit T)Lj,,r)L2
l-1-T)L? , ) Later, when the high level of the above signal is transmitted to the other input of the Nant gate circuit G2, the output signal B of the Nant gate circuit G2 changes from high level to low level.

By this, if we pay attention to the changes in the output signals A and B of the Nant gate circuits G1 and 62, when the clock pulse φ changes from low level to high level, the output signal B of the Nant gate circuit C2 changes to high level first. After the above delay time (DL3+DL4) has elapsed, the Nant gate circuit G
When the output signal A of the Nant gate circuit G1 changes to low level and the clock pulse φ changes from high level to low level, the output signal A of Nant gate circuit G1 changes from high level to low level and the delay time (DL1+DL2) is increased. After the elapse of time, the output signal B of the Nant gate circuit G2 changes to low level. This means that the low level is a logic "1'"
In terms of negative logic, the output signals A and B are output from the delay circuits DLL, DL2, DL3 . DL4 delay time (DLL
+DL2) and (DL3+DL4) are two-phase clock pulses with non-overramp times.

In this embodiment, substantially three-phase clock pulses φ1 . φ. and φ. and φ8, each clock pulse is formed through a gate circuit as follows.

The signals on the input and output sides of the delay circuit DLL that receive the output signal of the Nant gate circuit G1 are input to the Nant gate circuit G5 via the inverter circuits Nil and N12, respectively, and the signals are input to the Nant gate circuit G5 via the inverter circuit N13, although they are not particularly limited. clock pulse φ4. φ. is output. Since the Nant gate circuit G5 and the inverter circuit N13 substantially constitute an AND gate circuit, the clock pulses φ^ and φ. is the delay time (DL
This is a clock pulse that rises with a delay of I) and falls in synchronization with the rise of the output signal A. Instead of this configuration, the clock pulses φ, φ, may be output directly from the output of the inverter circuit Nil.

In this case, clock pulse φ4. φ0 is an inverted signal of the signal A described above.

The input and output signals of the delay circuit DLI which receives the output signal B of the Nant gate circuit G2 are the clock pulse φ. 3 with the above-mentioned phase difference between and φ.
NOR gate circuit G3 through inverter circuits N7 and N8, respectively, to provide phase clock pulses.
are input to the Nant gate circuit G4, and the clock pulses φ3 . φD
is output. The NOR gate circuit G3 and the inverter circuit 9 substantially constitute an OR gate circuit, and the NOR gate circuit G4 and the inverter circuit NIO substantially constitute an AND gate circuit. Therefore, the clock pulse φ is a clock pulse that rises in synchronization with the fall of the output signal B and falls with a delay of the delay time (DL3) of the delay circuit DL3 with respect to the rise. In contrast, the clock pulse φ. In other words, rises with a delay of the delay time (DL3) of the delay circuit DL3 with respect to the falling edge of the output signal B, in other words, with respect to the rising edge of the clock pulse φ, and is synchronized with the rising edge of the output signal B. In other words, For example, the delay time (DL3) with respect to the falling edge of the clock pulse φ,
It is considered as a lock pulse if the signal falls in front of the pulse. This causes the clock pulse φ. While this clock pulse φ is at high level. The clock pulse φ, which is in phase with , does not change. Also, other clock pulses φ1 and φ
, are also not changed by the non-overrough setting of 1 hour as described above.

Clock pulses φ1 and φ8 formed as above
For digital/analog conversion as mentioned above,
The clock pulses are converted into the clock pulses φAl and φ□ shown in FIG. 1 through the following selection circuit.

The clock pulse φ1 is supplied to one input of the AND gate circuit G6. The clock pulse φ is supplied to one input of the AND gate circuit G7. The other input of the AND gate circuit G6 is supplied with the digital signal 2° corresponding to the least significant bit, and the other input of the AND gate circuit G7 is supplied with the digital signal 2°.
° is inverted and supplied by an inverter circuit N13.

The output signals of the AND gate circuits G6 and G7 are outputted as clock pulses φ corresponding to the digital signal 20 through the OR gate circuit.

A selection circuit consisting of an AND gate circuit and an OR gate circuit (circuit symbols omitted) similar to those described above is provided corresponding to clock pulse φ11. However, the digital signal 20
is supplied in reverse to the above case.

As a result, for example, the digital signal 2° becomes high level (
When the logic is "1"), the AND gate circuit G6 opens the gate, and the clock pulse φ^ becomes the clock pulse φ, .
is output as Further, in response to the high level of the digital signal 2°, the AND gate circuit that receives the clock pulse φ opens its gate, and the clock pulse φ, l is outputted through the OR gate circuit.

Conversely, digital signal 2" is low level (logic "0")
At this time, as shown in the operational waveform diagram of digital/analog conversion in FIG. 2, the AND gate circuit G7 opens the gate and the clock pulse φ is outputted as the clock pulse φAl. Also, digital signal 2°
The AND gate circuit that receives the clock pulse φ1 opens its gate in response to the low level of the clock pulse φ1, and the clock pulse φ1 is outputted through the OR gate circuit. in this way,
Corresponding to the logic “1” or logic “O” of the digital signal 2°, the clock pulse φ is switched and output as the clock pulse φ□ or φ□, and the clock pulse φ
8 is switched and output as a clock pulse φ□ or φ□. This means that the clock pulses φ^2, φ corresponding to the digital signals 2' to 2'' of other bits
B! The same applies to φk1% and φ.

In this way, clock pulse φ1 becomes clock pulse φ, or φ, depending on the state, in other words, depending on the input digital signal. The clock pulse φ□ always has a negative phase relationship with the clock pulse φA1. However, the clock pulse φ. The clock pulse φI or φ^, which has an in-phase relationship with , is changed with a phase according to the delay time (DL3) as described above. In addition, clock pulses φ□ and φ3. is made into the two-phase clock pulse with non-overlap. Instead of the gate circuit as described above, a CMOS switch circuit as shown in FIG. 1 may be used to switch the clock pulse in the same manner as described above in response to the input digital signal 2°. In this case, the number of circuit elements can be reduced.

As mentioned above, when the switch element coupled to the inverting input terminal - which is the virtual ground of the operational amplifier circuit constituting the switched capacitor circuit is in the on state, switch control of other switch elements is not performed. It is possible to prevent feedthrough and switching noise from appearing in the output signal Vout. This makes it possible to improve the linearity and S/N of the output signal Vout.

The effects obtained from the above examples are as follows. That is, (1) Among the plurality of switching elements constituting the switched capacitor circuit, when the switching element coupled to the virtual ground input of the operational amplifier circuit is in the on state, switching control of other switching elements is not performed. Make it. As a result, when the switch element that transmits the signal charge of the input capacitor to the output capacitor is turned on, switch control of other switch elements is not performed, so feedthrough and switching noise occur during switch control. is not transmitted to the output side capacitor, resulting in the effect that the characteristics can be improved.

(2) When an analog/digital conversion circuit is constructed using the above-mentioned switched capacitor circuit, it is possible to prevent the generation of feedthrough and switching noise as described above, so that the accuracy and linearity can be improved. can get.

(3) Divide the delay circuit in the clock pulse generation circuit that forms two-phase non-overlapping clock pulses into two, and use the input and output signals of the input-side delay circuit to effectively With a simple configuration of supplying to the AND gate circuit and the OR gate circuit ((1)
The effect is that substantially three-phase clock pulses satisfying conditions such as 1 can be formed.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above-mentioned Examples, and it goes without saying that various changes can be made without departing from the gist thereof. Nor. For example, in addition to the above-mentioned digital/analog conversion circuit, the configuration of a swissotide capacitor circuit is to input an input signal in the form of a charge into the input capacitor, in other words, to sample the input voltage and convert it into the form of a charge. Any switched capacitor circuit may be used as long as it captures the signal and transmits it to a capacitor on the output side or exchanges it with the capacitor on the output side. Furthermore, the digital/analog conversion circuit described above may be used to configure an analog/digital conversion circuit. Further, in FIG. 3, the Nant gate circuits G1 and 02 can be replaced with gate circuits such as NOR gate circuits. Accordingly, inverter circuits N7 to N12 can be omitted. in this way,
The circuit for forming clock pulses φ4 to φ can take various embodiments.

This invention can be widely used as a switched capacitor circuit.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, when a switch element coupled to a virtual ground input of an operational amplifier circuit is in an on state among a plurality of switch elements constituting a switched capacitor circuit, switching control of other switch elements is not performed. As a result, when the switch element that transmits the signal charge of the input side capacitor to the output side capacitor is turned on, switch control of other switch elements is not performed.
Feedthrough and switching noise generated during switch control are not transmitted to the output side capacitor, making it possible to improve characteristics.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of a digital/analog conversion circuit to which the present invention is applied, Fig. 2 is a waveform diagram for explaining an example of its operation, and Fig. 3 is a clock pulse generation A circuit diagram showing an example of the circuit; FIG. 4 is a waveform diagram for explaining an example of its operation; FIG. 5 is a circuit showing an example of a clock pulse conversion circuit corresponding to an input digital signal. It is a diagram.

Claims (1)

[Claims] 1. A switch consisting of a plurality of devices that captures a signal charge into an input-side capacitor in accordance with a clock pulse and transfers the signal charge to an output-side capacitor provided between a virtual ground input and an output of an operational amplifier circuit. A switched capacitor comprising a plurality of switch elements, wherein when a switch element coupled to the virtual ground input is in an on state, among the plurality of switch elements, switching control of other switch elements is not performed. circuit. 2. The plurality of switch elements described above include a first switch element that transmits a reference voltage to one electrode of the input capacitor, and a first switch element that is provided between one electrode of the input capacitor and the ground potential point of the circuit. a third switch element provided between the other electrode of the input capacitor and a ground potential point of the circuit; a virtual ground input of the operational amplifier circuit and the other electrode of the input capacitor; and a fourth switch element provided between the third and fourth switch elements, the third and fourth switch elements are switch-controlled by non-overlapping clock pulses, and the first switch element Claim 1, characterized in that the switch is controlled so that the second switch element has an in-phase relationship with the third or fourth switch element, and the second switch element has an opposite phase relationship with the first switch element. The switched capacitor circuit according to item 1. 3. The switched device according to claim 1 or 2, wherein each of the switch elements is a CMOS switch circuit consisting of an N-channel MOSFET and a P-channel MOSFET arranged in parallel. capacitor circuit.