JP2564212Y2 - Charge transfer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a charge transfer device in which a charge transfer section and a sample and hold circuit for sampling and holding a signal from the charge transfer section are formed on the same chip.

[Conventional technology]

A CCD output signal from a CCD imager usually includes a transfer clock component, reset noise, and the like.To remove such noise, the CCD output signal is processed by a sample-and-hold circuit. ing.

Conventionally, the sample-and-hold circuit has been configured by a separate chip from the CCD imager, but recently, on-chip implementation of forming the CCD imager and the sample-and-hold circuit on the same chip has been promoted.

[Problems to be solved by the invention]

However, when a CCD imager and a sample-and-hold circuit are formed on the same chip, only the sample-and-hold output signal that has been sampled and held is output. Therefore, for a user who performs special signal processing, for example, when processing signals by correlated double sampling (CDS) or changing the method of taking a reference level, the sample and hold output signal is used. There is a problem that it is difficult to do so.

In view of the above-mentioned problem, an object of the present invention is to provide a charge transfer device having a structure capable of selecting and outputting not only a sample-hold output signal but also a charge transfer output signal.

[Means for solving the invention]

In order to achieve the object described above, the charge transfer device according to the present invention includes a charge transfer unit, a sample-and-hold capacitor, and a first switching element that performs switching between the sample-and-hold capacitor and the charge transfer unit. The first
A sample-and-hold circuit having a second switching element connected in parallel to the switching element and sampling and holding a signal from the charge transfer unit;
A signal generation circuit for generating a sample and hold pulse signal to be supplied to the switching element, and a switching circuit that can be switched by an external control signal for selecting the presence or absence of the sample and hold. A sample and hold pulse signal supplied from the signal generation circuit is supplied to the first and second switching elements, and the first and second switching elements are supplied to the first and second switching elements when the sample and hold is not performed. And a driving unit for driving the first and second switching elements by supplying a signal for constantly turning on the same is provided on the same chip.

[Action]

The charge transfer device according to the present invention supplies a sample and hold pulse signal to the first and second switching elements constituting the sample and hold circuit when performing the sample and hold based on the external control signal, and supplies the sample and hold pulse signal when not performing the sample and hold. The first and second switching elements are driven by supplying a signal for constantly turning on the first and second switching elements to the first and second switching elements. As a result, the first and second switching elements constituting the sample and hold circuit function simply as a signal transfer path, and the charge transfer output signal is output without being sampled and held.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the entire CCD imager of the present embodiment. As shown in FIG. 1, on the CCD chip 1, a charge transfer section 9 for supplying a required drive pulse and transferring charges is provided. The charge transfer unit 9 is connected to an image pickup unit 10 in which photo sensors are arranged in a matrix or a line, for example, and signal charges are transferred from the image pickup unit 10 to the charge transfer unit 9. The charge transfer unit 9 outputs an output according to the transferred charge, and the output from the charge transfer unit 9 is supplied to the first-stage buffer 6 having a source follower configuration. The output of the first-stage buffer 6 is supplied to one of the source and drain of a pMOS transistor 3 as a first switching element and an nMOS transistor 4 as a second switching element, which constitute a sample-and-hold switch. These pMOS transistor 3 and nMOS transistor 4 are commonly connected so that their sources and drains constitute a CMOS switch. Further, a control signal to be described later is switched and supplied to each gate of the pMOS transistor 3 and the nMOS transistor 4. Therefore, each MO
The S transistors 3 and 4 function as a sample and hold switch for performing a sample and hold operation, or function as a simple signal transfer path. The other of the source and the drain of the pMOS transistor 3 and the other of the source and the drain of the nMOS transistor 4 are connected to the input terminal of the output buffer 7 and to one end of the sample hold capacitor 8. The sample hold capacitor 8 is for maintaining the signal level,
It may be a parasitic capacitance such as wiring. The output terminal of the output buffer 7 is taken out of the chip, and one of the charge transfer output signal CCDout and the sample / hold output signal S / Hout is selectively output from the external terminal 21. Here, the charge transfer output signal CCDout is a signal obtained by directly amplifying the signal level of, for example, the floating diffusion region of the charge transfer unit 9 and can perform signal processing such as CDS.
The sample / hold output signal S / Hout is a signal obtained by digitizing the charge transfer output signal CCDout with a required sample / hold pulse signal.

Next, a circuit configuration for sending a control signal to the pMOS transistor 3 and the nMOS transistor 4 will be described.
On the CCD chip 1, a signal generation circuit 5 is provided. The signal generation circuit 5 generates sample and hold pulse signals ΦS / H1 and ΦS / H2. The sample / hold pulse signal ΦS / H1 is a control signal for causing the pMOS transistor 3 to perform a sample / hold operation, and the sample / hold pulse signal ΦS / H2 is a control signal for causing the nMOS transistor 4 to perform a sample / hold operation. These sample and hold pulse signals ΦS / H1 and ΦS / H2 have opposite phases to each other and are both supplied to the switching circuit 2. The switching circuit 2 receives the sample and hold pulse signal ΦS /
H1 and ΦS / H2 are output as they are, and a signal for constantly turning on the MOS transistors 3 and 4 is also output. The switching circuit 2 is supplied with an external control signal ΦSW from an external terminal 22. The output of the switching circuit 2 is switched between the sample-and-hold pulse signals ΦS / H1 and ΦS / H2 and the signal to be always turned on in accordance with the level of the external control signal ΦSW while the pMOS transistor 3 is switched. It is supplied to the gate of the nMOS transistor 4 respectively.

Here, the configuration of the switching circuit 2 will be further described with reference to FIG. First, the switching circuit 2 is provided with inverters 16 and 17, and the inverters 16 and 17 have the sample and hold pulse signal ΦS /
H1 and ΦS / H2 are supplied. One of the source and the drain of the nMOS transistor 11 is connected to the output terminal of the inverter 16. One of a source and a drain of the nMOS transistor 12 is connected to an output terminal of the inverter 17.
The inverted external control signal ΦSW is supplied to the gates of the nMOS transistors 11 and 12 via the inverter 15. The other of the source and the drain of the nMOS transistor 11 is connected to the gate of the pMOS transistor 3 via the inverter 18. The other of the source and the drain of the nMOS transistor 12 is connected via an inverter 19 to the gate of the nMOS transistor 4. Therefore, if the nMOS transistors 11 and 12 are on, the sample and hold pulse signals ΦS / H1 and ΦS / H2 from the signal generation circuit 5 are supplied to the pMOS transistor 3 and the nMOS transistor 4, respectively.

The external control signal Φ supplied to the inverter 15
SW is also supplied to the gates of the nMOS transistors 13 and 14. n
The power supply voltage Vcc from the power supply 20 is supplied to the drain of the MOS transistor 13. The power supply 20 may be internal or external. n
The source of the MOS transistor 14 is supplied with the ground voltage GND. The source of the nMOS transistor 13 whose drain is supplied with the power supply voltage Vcc is connected to the gate of the pMOS transistor 3 via the inverter 18. Ground voltage GND at source
Is supplied to the gate of the nMOS transistor 4 via the inverter 19. Therefore, if the nMOS transistors 13 and 14 are both on, the gate level of the nMOS transistor 3 is set to a low level (for example, 0 V), and at the same time, the gate level of the nMOS transistor 4 is set to a high level via the nMOS transistor 14 and the inverter 19. (For example, 5 V), and as a result, each of the MOS transistors 3 and 4 is turned on.

The operation of the switching circuit 2 having such a circuit configuration is such that the external control signal ΦSW selectively switches between the sample and hold pulse signals ΦS / H1 and ΦS / H2 and the signal that is always turned on, and switches each of the MOS transistors 3 and Supply 4

First, the level of the external control signal ΦSW is low (for example,
0V), the nMOS transistors 13 and 14 are turned off, and the external control signal Φ inverted through the inverter 15
The nMOS transistors 11 and 12 to which SW is supplied are turned on. Therefore, the sample-and-hold pulse signal ΦS / H1 from the signal generation circuit 5 is supplied to the gate of the pMOS transistor 3 via the inverter 16, the nMOS transistor 11, and the inverter 18, and causes the pMOS transistor 3 to perform a sample-hold operation. Similarly, the sample hold pulse signal ΦS / H2 from the signal generation circuit 5 is connected to the inverter 17, nMO
The nMOS transistor 4 is supplied to the gate of the nMOS transistor 4 via the S transistor 12 and the inverter 19,
A sample hold operation is performed in synchronization with the pMOS transistor 3. Therefore, the signal output from the external terminal 21 is a pMOS
The result is a sample / hold output signal S / Hout sampled and held using the transistor 3 and the nMOS transistor 4.

Next, the level of the external control signal ΦSW is set to a high level (for example,
9V), the nMOS transistors 13 and 14 are turned on, and the external control signal ΦSW inverted through the inverter 15
Are supplied, the nMOS transistors 11 and 12 are turned off.
For this reason, the power supply voltage Vcc
Is supplied to the input terminal of the inverter 19 and the ground voltage GN
D is supplied. Therefore, the output of the inverter 18 is at a low level (for example, 0 V), and the output of the inverter 19 is at a high level (for example, 5 V). Then, since the gate voltage of the pMOS transistor 3 is at a low level, the pMOS transistor 3 is turned on. Since the gate voltage of the nMOS transistor 4 is at a high level, the nMOS transistor is also turned on. As described above, since the MOS transistors 3 and 4 are always turned on by the external control signal ΦSW, the signal from the first-stage buffer 6 passes through the MOS transistors 3 and 4 to reach the output buffer 7, and the output buffer 7 And the external terminal 21 outputs a charge transfer output signal CCDout that has not been sampled and held.

At this time, since the MOS transistors 3 and 4 are connected in parallel, the ON resistance of each of the MOS transistors 3 and 4 to which the charge transfer output signal is transferred is reduced.

As described above, in the CCD imager of this embodiment, the charge transfer output signal CCDout and the sample hold output signal S / Hout are selectively output from the external terminal 21 by the external control signal ΦSW. For this reason, a signal output method suitable for signal processing set by a user can be adopted.

In the above embodiment, the external control signal ΦSW is directly applied to the external terminal 22.However, a constant voltage may be supplied to the external terminal 22 via a high resistance. Even when no voltage is supplied, it is possible to output one of the sample-and-hold pulse signal and the signal to be always turned on from the switching circuit 2. Further, although the first switching element and the second switching element of the sample-and-hold switch are each configured by the pMOS transistor 3 and the nMOS transistor 4, the switching elements may be configured by other switching elements.

[Effect of the invention]

In the charge transfer device according to the present invention, when the control unit controls the operation of the first and second switching elements based on the external control signal and performs the sample and hold, the control unit controls the first and second switching elements to perform the sample and hold operation. When a pulse signal is supplied and the sample and hold is not performed, a signal for constantly turning on the first and second switching elements is supplied to the first and second switching elements. This makes it possible to selectively output the sample hold output signal and the charge transfer output signal, and to reduce the on-resistance of the switching element to which the charge transfer output signal is transferred when the sample hold is not performed. Therefore, it is possible to satisfy a user's request for performing various kinds of signal processing.

In addition, the charge transfer device of the present invention provides an external control signal from the outside to a charge transfer unit, a sample and hold circuit, and a switching circuit formed on the same chip as the signal generation circuit. Based on this, a sample hold pulse signal from the signal generation circuit and a signal for constantly turning on the sample hold switch are selectively supplied to the sample hold switch constituting the sample hold circuit. This makes it possible to select whether or not to perform sample and hold according to an external control signal without requiring an external additional circuit, thereby reducing the load on circuit design.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall circuit configuration of an example of the charge transfer device of the present invention, and FIG. 2 is a circuit configuration diagram of a main part of the example. DESCRIPTION OF SYMBOLS 1 ... CCD chip 2 ... Switching circuit 3 ... PMOS transistor 4,11-14 ... NMOS transistor 5 ... Signal generation circuit 6 ... First stage buffer 7 ... Output buffer 8 ... Sample hold capacitance 9 ... Charge Transfer unit 15-19 …… Inverters 21,22 …… External terminals

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-20799 (JP, A) JP-A-63-108598 (JP, A) Japanese Utility Model 60-134369 (JP, U)

Claims (1)

(57) [Scope of request for utility model registration] A first switching element for switching between a charge transfer section, a sample and hold capacitor, the sample and hold capacitor and the charge transfer section, and a second switching element connected in parallel to the first switching element. A sample and hold circuit that has a switching element and samples and holds a signal from the charge transfer unit; a signal generation circuit that generates a sample and hold pulse signal to be supplied to the first and second switching elements; And a switching circuit that is switched by an external control signal for selecting the first and second signals.
And a sample and hold pulse signal supplied from the signal generation circuit to the second switching element, and when the sample and hold is not performed, the first and second switching elements are always used as the first and second switching elements. A charge transfer device, wherein a drive unit for driving the first and second switching elements by supplying a signal for turning on the same is provided on the same chip.