KR910006586Y1 - Driving circuit of solid state image pick-up device - Google Patents

Abstract

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Description

Vertical driving circuit of solid state imaging device

1 is a schematic diagram showing a vertical driving circuit of a solid state imaging device that is commonly used.

FIG. 2 is a view showing the first and second level conversion units in the vertical driving circuit of the solid state image pickup device shown in FIG.

FIG. 3 is a view showing a decoder unit in the vertical driving circuit of the solid state image pickup device shown in FIG.

4 is a view showing the embodiment of the decoder unit of the vertical driving circuit of the solid state image pickup device according to the present invention.

* Explanation of symbols for main parts of the drawings

10: first level 10A: second level converter

20: decoder parts S1 to S4: pass transistor

I4, I5: Inverter

The present invention relates to a vertical driving circuit of a solid state image pickup device using the optical accumulation effect of a photodiode, and more particularly, to the signal charge when driving the electronic shutter of a charge coupled device (CCD) type solid state image pickup device. Vertical drive circuit that simplifies the configuration of a decoder for controlling a signal for transferring to a shift register accumulated in each pixel portion for transmission in a horizontal transfer CCD direction and a signal for transferring a signal transferred to the shift register in a vertical direction It is about.

In general, it is used as an image pickup tube of a video camera and the vertical driving circuit of the solid state image pickup device has an outline as shown in FIG. 1, which will be briefly described as follows.

The vertical driving circuit of the solid state photographer uses a signal output from each clock pulse generator not shown in the figure as an input signal of the input terminals IN1 and IN2, and a pulse having a level of about -7 at -13V (? 1). A signal for transferring the charge accumulated in each pixel unit to the shift register by combining the first and second level converters 10 and 10a for switching to output (ø2) and the pulses ø1 and ø2. VH) and a decoder 20 for outputting a signal VM (VL) for moving the signal transferred to the shift register in the vertical direction.

In the above description, the first and second level converters include an inverter circuit composed of N-channel field effect transistors M3 and M4 and P-channel field effect transistors M1 and M2, and a driver transistor M5 and M6, respectively. When the clock pulse, which is a "high" signal to the input terminal IN, is directly and inverted by the inverter I1 and applied to the gate terminal of the inverter circuit, that is, the transistors M1 to M4, the N-channel transistor M3. ) And the P-channel transistor M2 are in the "conducting" state, and the output signal (?) Of the output terminal is in the "high (VH)" state. Is supplied to the inverter circuit, the transistors M1 and M4 are in the "conducting" state, and when the transistor M1 is in the "conducting" state, the VH signal "high" is applied to the gate terminal of the transistor M6. The output signal? Of the output terminal becomes the voltage of the ground voltage supply terminal V _SS .

The NAND gate which selectively combines the first and second level conversion units 10 and 10A operating as described above with the output signals ø1 and ø2 or the inverted signals respectively from the inverters I2 and I3 ( The selector 21 selects the vertical drive signals VH (VM) VL of the solid state image pickup device in accordance with the level of the signals output from N1 to N4.

In order to integrate the first and second level converting units 10 and 10A and the decoder unit 20 having the structure as described above, the NAND gates N1 to N4 which are components of the decoder unit 0 are 20 pieces. Because of the need for transistors, there were some limitations in reducing the chip area.

Therefore, an object of the present invention is to simplify the internal configuration of the decoder unit in the driving circuit of the solid state image pickup device to reduce the chip area when integrating the driving circuit.

In order to achieve the above object, the decoder unit of the vertical driving circuit according to the present invention includes a pass transistor for switching the vertical driving signals VH and VM, respectively, by a signal output from the first level converter and an inverted signal thereof; And a pass transistor for switching the vertical drive signal VL different from the vertical drive signal through the pass transistor by a signal output from the second level converter and an inverted signal.

Hereinafter, the present invention will be described in more detail with reference to the drawings.

In the vertical driving circuit of the solid state image pickup device according to the present invention, the decoder unit 20 is a vertical driving signal by the signal ø1 output from the first level converting unit 10 and the output signal of the inverter I4 inverting the same. The pass transistor S1 is switched by the pass transistors S1 and S2 for switching VH and VM, the signal ø2 output from the second level converter 10A and the output signal of the inverter I5 to invert it. Pass transistors S1 and S2 for switching the signals VH and VM through S2, the signal ø2 output from the second level converter 10A, and the output signal of the inverter I5 inverting it. By this configuration, the pass transistors S3 and S4 switch the signals VH and VM through the pass transistors S1 and S2 and the other vertical driving signals VL, respectively.

The operation relationship of the vertical driving circuit of the solid state image pickup device having the decoder unit 20 having the above configuration will be described in detail.

The vertical drive signal VH in the decoder unit 20 according to the level of the signal? 1 (? 2) output from the first and second level converters 10 and 10A operating as described above according to the level of the clock pulse. The output of switching (VM) (VL) is shown below.

As can be seen from the above table, when the levels of the signals? 1 and? 2 output from the first and second level converters 10 and 10A are all "low", the P-channel field effect which is the pass transistor S1 is obtained. The gate terminal of the transistor B1 is in a "low" state, and a signal ø1 inverted by the inverter I4 is applied to the gate terminal of the N-channel field effect transistor A1. The transistors B1 and A1 are applied. Becomes a "conduction" state, and the vertical drive signal VH is applied to the transistor transistor S4 described later.

The signal ø2 inverted by the inverter I5 is applied to the gate terminal of the N-channel field effect transistor A4, which is the pass transistor S4, and the signal ø2 is applied to the P-channel field effect transistor B4. Since they are each applied, transistors A4 and B4 become " conducted. &Quot; Therefore, since the vertical driving signal VH supplied to the pass transistor S4 is output and applied to the solid state image pickup device, the charge accumulated in the pixel portion is transferred to the shift register.

On the other hand, as shown in the above table, when the signal? 1 (? 2) output from the first and second level converters 10 and 10A has the "low" and "high" levels, the signal passes as described above. The transistor S1 becomes " conducted, " the vertical drive signal VH is applied to the pass transistor S4. However, since the signal? 2 output from the second level converter 10A is at the " high " level, the pass transistor is applied. The vertical driving signal VH is cut off when S4 is in a non-conductive state, and the vertical driving signal VL supplied to the pass transistor S3 is outputted and applied to the solid state image pickup device, so that the charge in the shift register is vertical. Go to.

When the level of ø1 and ø2 output from the first and second level converters 10 and 10A is "high" and "low" states, the pass transistors S2 and S4 are respectively "conducted". Since the vertical driving signal VM is output to the output terminal OUT and applied to the solid state image pickup device, the charge accumulated in the shift register is vertically transferred, and the arc signal is eventually lead out.

As described above, by simplifying the configuration of the decoder unit to select the vertical driving signal of the solid state image pickup device, there is an advantage in that the area of the chip is reduced when the vertical driving circuit is integrated.

Claims (1)

In the first and second level converters 10 and 10a and the decoder unit 20, the decoder unit 20 outputs a signal ø1 output from the first level converter 10 and an inverter ( Pass transistors S1 and S2 for switching the vertical drive signals VH and VM respectively by the signal inverted in I4), and the vertical drive signals VM and VH through the pass transistors S1 and S2. The drive circuit is integrated by configuring another vertical drive signal VL by a pass transistor S3 and S4 which respectively switch the signal output from the second level converter 10A and the inverter I5 while the inverter I5 is inverted. The vertical driving circuit of the solid state image pickup device, characterized in that when the chip area is reduced.